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/linux-5.10/drivers/mtd/chips/
Djedec_probe.c26 #define AM29DL800BB 0x22CB
27 #define AM29DL800BT 0x224A
29 #define AM29F800BB 0x2258
30 #define AM29F800BT 0x22D6
31 #define AM29LV400BB 0x22BA
32 #define AM29LV400BT 0x22B9
33 #define AM29LV800BB 0x225B
34 #define AM29LV800BT 0x22DA
35 #define AM29LV160DT 0x22C4
36 #define AM29LV160DB 0x2249
[all …]
/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Dmmio.c12 [MT_TOP_CFG_BASE] = 0x01000,
13 [MT_HW_BASE] = 0x01000,
14 [MT_PCIE_REMAP_2] = 0x02504,
15 [MT_ARB_BASE] = 0x20c00,
16 [MT_HIF_BASE] = 0x04000,
17 [MT_CSR_BASE] = 0x07000,
18 [MT_PLE_BASE] = 0x08000,
19 [MT_PSE_BASE] = 0x0c000,
20 [MT_CFG_BASE] = 0x20200,
21 [MT_AGG_BASE] = 0x20a00,
[all …]
/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/linux-5.10/tools/arch/alpha/include/uapi/asm/
Dmman.h13 #define MADV_NORMAL 0
19 #define MAP_ANONYMOUS 0x10
20 #define MAP_DENYWRITE 0x02000
21 #define MAP_EXECUTABLE 0x04000
22 #define MAP_FILE 0
23 #define MAP_FIXED 0x100
24 #define MAP_GROWSDOWN 0x01000
25 #define MAP_HUGETLB 0x100000
26 #define MAP_LOCKED 0x08000
27 #define MAP_NONBLOCK 0x40000
[all …]
/linux-5.10/Documentation/devicetree/bindings/mfd/
Dmfd.txt29 the child's base address to 0, the physical address within parent's address
42 reg = <0x01000 0x1000>;
46 offset = <0x08>;
47 mask = <0x01>;
/linux-5.10/drivers/media/rc/
Dir-rc5-decoder.c50 return 0; in ir_rc5_decode()
61 return 0; in ir_rc5_decode()
88 return 0; in ir_rc5_decode()
117 return 0; in ir_rc5_decode()
119 xdata = (data->bits & 0x0003F) >> 0; in ir_rc5_decode()
120 command = (data->bits & 0x00FC0) >> 6; in ir_rc5_decode()
121 system = (data->bits & 0x1F000) >> 12; in ir_rc5_decode()
122 toggle = (data->bits & 0x20000) ? 1 : 0; in ir_rc5_decode()
123 command += (data->bits & 0x40000) ? 0 : 0x40; in ir_rc5_decode()
132 return 0; in ir_rc5_decode()
[all …]
/linux-5.10/drivers/net/ethernet/intel/ixgbevf/
Dregs.h7 #define IXGBE_VFCTRL 0x00000
8 #define IXGBE_VFSTATUS 0x00008
9 #define IXGBE_VFLINKS 0x00010
10 #define IXGBE_VFFRTIMER 0x00048
11 #define IXGBE_VFRXMEMWRAP 0x03190
12 #define IXGBE_VTEICR 0x00100
13 #define IXGBE_VTEICS 0x00104
14 #define IXGBE_VTEIMS 0x00108
15 #define IXGBE_VTEIMC 0x0010C
16 #define IXGBE_VTEIAC 0x00110
[all …]
/linux-5.10/drivers/block/
Dumem.h18 #define MEMCTRLSTATUS_MAGIC 0x00
19 #define MM_MAGIC_VALUE (unsigned char)0x59
21 #define MEMCTRLSTATUS_BATTERY 0x04
22 #define BATTERY_1_DISABLED 0x01
23 #define BATTERY_1_FAILURE 0x02
24 #define BATTERY_2_DISABLED 0x04
25 #define BATTERY_2_FAILURE 0x08
27 #define MEMCTRLSTATUS_MEMORY 0x07
28 #define MEM_128_MB 0xfe
29 #define MEM_256_MB 0xfc
[all …]
/linux-5.10/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/linux-5.10/arch/powerpc/include/asm/
Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/linux-5.10/arch/alpha/include/uapi/asm/
Dmman.h5 #define PROT_READ 0x1 /* page can be read */
6 #define PROT_WRITE 0x2 /* page can be written */
7 #define PROT_EXEC 0x4 /* page can be executed */
8 #define PROT_SEM 0x8 /* page may be used for atomic ops */
9 #define PROT_NONE 0x0 /* page can not be accessed */
10 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
11 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
13 /* 0x01 - 0x03 are defined in linux/mman.h */
14 #define MAP_TYPE 0x0f /* Mask for type of mapping (OSF/1 is _wrong_) */
15 #define MAP_FIXED 0x100 /* Interpret addr exactly */
[all …]
/linux-5.10/arch/mips/include/asm/sgi/
Dheart.h24 #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL))
47 * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
49 * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
56 * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
58 * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
60 * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
62 * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
64 * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
79 struct ip30_heart_regs { /* 0x0ff00000 */
80 u64 mode; /* + 0x00000 */
[all …]
Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
[all …]
/linux-5.10/drivers/i2c/busses/
Di2c-efm32.c17 #define REG_CTRL 0x00
18 #define REG_CTRL_EN 0x00001
19 #define REG_CTRL_SLAVE 0x00002
20 #define REG_CTRL_AUTOACK 0x00004
21 #define REG_CTRL_AUTOSE 0x00008
22 #define REG_CTRL_AUTOSN 0x00010
23 #define REG_CTRL_ARBDIS 0x00020
24 #define REG_CTRL_GCAMEN 0x00040
25 #define REG_CTRL_CLHR__MASK 0x00300
26 #define REG_CTRL_BITO__MASK 0x03000
[all …]
/linux-5.10/arch/arm/mach-imx/
Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/linux-5.10/drivers/net/wireless/intersil/prism54/
Disl_38xx.h19 #define ISL38XX_PSM_ACTIVE_STATE 0
23 #define ISL38XX_PCI_MEM_SIZE 0x02000
24 #define ISL38XX_MEMORY_WINDOW_SIZE 0x01000
25 #define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000
32 #define ISL38XX_HARDWARE_REG 0x0000
33 #define ISL38XX_CARDBUS_CIS 0x0800
34 #define ISL38XX_DIRECT_MEM_WIN 0x1000
37 #define ISL38XX_DEV_INT_REG 0x0000
38 #define ISL38XX_INT_IDENT_REG 0x0010
39 #define ISL38XX_INT_ACK_REG 0x0014
[all …]
/linux-5.10/drivers/video/console/
Dmdacon.c78 module_param(mda_first_vc, int, 0);
80 module_param(mda_last_vc, int, 0);
86 #define MDA_CURSOR_BLINKING 0x00
87 #define MDA_CURSOR_OFF 0x20
88 #define MDA_CURSOR_SLOWBLINK 0x60
90 #define MDA_MODE_GRAPHICS 0x02
91 #define MDA_MODE_VIDEO_EN 0x08
92 #define MDA_MODE_BLINK_EN 0x20
93 #define MDA_MODE_GFX_PAGE1 0x80
95 #define MDA_STATUS_HSYNC 0x01
[all …]
/linux-5.10/drivers/gpu/drm/lima/
Dlima_device.c51 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
52 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
53 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
54 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
55 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
56 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
57 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
58 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
59 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
60 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
[all …]
/linux-5.10/arch/arm/mach-ux500/
Ddb8500-regs.h10 #define U8500_ESRAM_BASE 0x40000000
11 #define U8500_ESRAM_BANK_SIZE 0x00020000
21 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
28 #define U8500_PER3_BASE 0x80000000
29 #define U8500_STM_BASE 0x80100000
30 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
31 #define U8500_PER2_BASE 0x80110000
32 #define U8500_PER1_BASE 0x80120000
33 #define U8500_B2R2_BASE 0x80130000
34 #define U8500_HSEM_BASE 0x80140000
[all …]
/linux-5.10/arch/powerpc/boot/dts/fsl/
Dmvme2500.dts29 ranges = <0x0 0 0xffe00000 0x100000>;
34 reg = <0x4c>;
39 reg = <0x68>;
40 interrupts = <8 1 0 0>;
45 reg = <0x54>;
50 reg = <0x52>;
55 reg = <0x53>;
60 reg = <0x50>;
68 flash@0 {
70 reg = <0>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml59 enum: [ 0, 1 ]
66 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
70 SPI interrupts are in the range [0-987]. PPI interrupts are in the
71 range [0-15].
74 bits[3:0] trigger type and level flags.
142 "^v2m@[0-9a-f]+$":
189 reg = <0xfff11000 0x1000>,
190 <0xfff10100 0x100>;
199 reg = <0x2c001000 0x1000>,
200 <0x2c002000 0x2000>,
[all …]
/linux-5.10/drivers/memstick/host/
Dtifm_ms.c29 #define TIFM_MS_STAT_DRQ 0x04000
30 #define TIFM_MS_STAT_MSINT 0x02000
31 #define TIFM_MS_STAT_RDY 0x01000
32 #define TIFM_MS_STAT_CRC 0x00200
33 #define TIFM_MS_STAT_TOE 0x00100
34 #define TIFM_MS_STAT_EMP 0x00020
35 #define TIFM_MS_STAT_FUL 0x00010
36 #define TIFM_MS_STAT_CED 0x00008
37 #define TIFM_MS_STAT_ERR 0x00004
38 #define TIFM_MS_STAT_BRQ 0x00002
[all …]
/linux-5.10/drivers/usb/gadget/udc/
Dgoku_udc.h12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
[all …]
/linux-5.10/drivers/usb/misc/sisusbvga/
Dsisusb.h45 #define SISUSB_VERSION 0
46 #define SISUSB_REVISION 0
60 #define SISUSB_IBUF_SIZE 0x01000
61 #define SISUSB_OBUF_SIZE 0x10000 /* fixed */
87 } while(0)
108 int isopen; /* !=0 if open */
109 int present; /* !=0 if device is present on the bus */
110 int ready; /* !=0 if device is ready for userland */
161 #define SISUSB_EP_GFX_IN 0x0e /* gfx std packet out(0e)/in(8e) */
162 #define SISUSB_EP_GFX_OUT 0x0e
[all …]
/linux-5.10/drivers/gpu/drm/rcar-du/
Drcar_du_regs.h13 #define DU0_REG_OFFSET 0x00000
14 #define DU1_REG_OFFSET 0x30000
15 #define DU2_REG_OFFSET 0x40000
16 #define DU3_REG_OFFSET 0x70000
22 #define DSYSR 0x00000 /* display 1 */
28 #define DSYSR_TVM_MASTER (0 << 6)
32 #define DSYSR_SCM_INT_NONE (0 << 4)
37 #define DSMR 0x00004
40 #define DSMR_DIPM_DISP (0 << 25)
50 #define DSMR_CDEM_CDE (0 << 13)
[all …]

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