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/linux-6.8/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml67 "spi@[0-9a-f]+$":
75 "i2c@[0-9a-f]+$":
80 "serial@[0-9a-f]+$":
104 "spi@[0-9a-f]+$": false
105 "serial@[0-9a-f]+$": false
131 reg = <0 0x008c0000 0 0x6000>;
141 reg = <0 0xa94000 0 0x4000>;
146 pinctrl-0 = <&qup_1_i2c_5_active>;
149 #size-cells = <0>;
154 reg = <0 0xa88000 0 0x7000>;
[all …]
/linux-6.8/drivers/media/platform/samsung/exynos4-is/
Dfimc-is.h41 #define FIMC_IS_CPU_MEM_SIZE (0xa00000)
43 #define FIMC_IS_REGION_SIZE 0x5000
45 #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000
46 #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000
54 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
55 #define FIMC_IS_EXTRA_FW_SIZE 0x180000
56 #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000
111 FIMC_IS_AF_IDLE = 0,
120 FIMC_IS_AF_UNLOCKED = 0,
125 FIMC_IS_AE_UNLOCKED = 0,
[all …]
/linux-6.8/crypto/
Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/linux-6.8/arch/arm64/boot/dts/qcom/
Dsdm670.dtsi33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
87 reg = <0x0 0x200>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x300>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dx1e80100.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
39 #clock-cells = <0>;
48 #clock-cells = <0>;
58 #size-cells = <0>;
60 CPU0: cpu@0 {
63 reg = <0x0 0x0>;
80 reg = <0x0 0x100>;
91 reg = <0x0 0x200>;
102 reg = <0x0 0x300>;
[all …]
Dsa8775p.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x200>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dmsm8996.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
53 clocks = <&kryocc 0>;
68 reg = <0x0 0x1>;
72 clocks = <&kryocc 0>;
82 reg = <0x0 0x100>;
101 reg = <0x0 0x101>;
[all …]
Dsc8180x.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
58 clocks = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
87 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi37 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #size-cells = <0>;
53 CPU0: cpu@0 {
56 reg = <0x0 0x0>;
57 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 CPU0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi32 #clock-cells = <0>;
39 #clock-cells = <0>;
47 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8650.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
48 #clock-cells = <0>;
57 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #size-cells = <0>;
74 CPU0: cpu@0 {
77 reg = <0 0>;
79 clocks = <&cpufreq_hw 0>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
78 clocks = <&cpufreq_hw 0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #size-cells = <0>;
72 CPU0: cpu@0 {
75 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi82 #clock-cells = <0>;
90 #clock-cells = <0>;
96 #size-cells = <0>;
98 CPU0: cpu@0 {
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
117 cache-size = <0x20000>;
123 cache-size = <0x400000>;
[all …]