Home
last modified time | relevance | path

Searched +full:0 +full:x008 (Results 1 – 25 of 469) sorted by relevance

12345678910>>...19

/linux-6.8/drivers/clk/mediatek/
Dclk-mt8192.c27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
32 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
33 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
34 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
35 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
36 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
[all …]
Dclk-mt6779.c640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
[all …]
Dclk-mt8183.c35 FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
36 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
37 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
38 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
39 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
40 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
41 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
42 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
43 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
44 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
[all …]
Dclk-mt7986-topckgen.c176 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
178 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
180 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
182 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
185 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
187 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
Dclk-mt7981-topckgen.c293 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
295 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
297 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
299 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
302 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
304 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
306 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
308 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
309 0x1C0, 7),
312 emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
[all …]
/linux-6.8/sound/pci/oxygen/
Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
Dwm8785.h5 #define WM8785_R0 0
11 #define WM8785_MCR_MASK 0x007
12 #define WM8785_MCR_SLAVE 0x000
13 #define WM8785_MCR_MASTER_128 0x001
14 #define WM8785_MCR_MASTER_192 0x002
15 #define WM8785_MCR_MASTER_256 0x003
16 #define WM8785_MCR_MASTER_384 0x004
17 #define WM8785_MCR_MASTER_512 0x005
18 #define WM8785_MCR_MASTER_768 0x006
19 #define WM8785_OSR_MASK 0x018
[all …]
Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/linux-6.8/drivers/net/ethernet/seeq/
Dsgiseeq.h35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
[all …]
/linux-6.8/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v3.h10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
Dphy-qcom-qmp.h54 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
55 #define QPHY_V3_DP_COM_SW_RESET 0x04
56 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
57 #define QPHY_V3_DP_COM_SWI_CTRL 0x0c
58 #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
59 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
60 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
63 # define QSERDES_V3_COM_BIAS_EN 0x0001
64 # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
65 # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
[all …]
Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
/linux-6.8/drivers/clk/meson/
Daxg-audio.h16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_PAD_CTRL0 0x01c
24 #define AUDIO_MST_PAD_CTRL1 0x020
25 #define AUDIO_SW_RESET 0x024
[all …]
/linux-6.8/sound/soc/codecs/
Dssm2602.h33 #define SSM2602_LINVOL 0x00
34 #define SSM2602_RINVOL 0x01
35 #define SSM2602_LOUT1V 0x02
36 #define SSM2602_ROUT1V 0x03
37 #define SSM2602_APANA 0x04
38 #define SSM2602_APDIGI 0x05
39 #define SSM2602_PWR 0x06
40 #define SSM2602_IFACE 0x07
41 #define SSM2602_SRATE 0x08
42 #define SSM2602_ACTIVE 0x09
[all …]
/linux-6.8/include/sound/sof/
Dheader.h23 * 0xGCCCNNNN where
34 #define SOF_GLB_TYPE_MASK (0xfUL << SOF_GLB_TYPE_SHIFT)
39 #define SOF_CMD_TYPE_MASK (0xfffL << SOF_CMD_TYPE_SHIFT)
43 #define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U)
44 #define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U)
45 #define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U)
46 #define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U)
47 #define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U)
48 #define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U)
49 #define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
[all …]
/linux-6.8/sound/firewire/dice/
Ddice-interface.h24 #define DICE_PRIVATE_SPACE 0xffffe0000000uLL
34 #define DICE_GLOBAL_OFFSET 0x00
35 #define DICE_GLOBAL_SIZE 0x04
36 #define DICE_TX_OFFSET 0x08
37 #define DICE_TX_SIZE 0x0c
38 #define DICE_RX_OFFSET 0x10
39 #define DICE_RX_SIZE 0x14
40 #define DICE_EXT_SYNC_OFFSET 0x18
41 #define DICE_EXT_SYNC_SIZE 0x1c
42 #define DICE_UNUSED2_OFFSET 0x20
[all …]
/linux-6.8/drivers/net/wireless/ath/carl9170/
Dhw.h43 #define AR9170_UART_REG_BASE 0x1c0000
46 #define AR9170_UART_REG_RX_BUFFER (AR9170_UART_REG_BASE + 0x000)
47 #define AR9170_UART_REG_TX_HOLDING (AR9170_UART_REG_BASE + 0x004)
48 #define AR9170_UART_REG_FIFO_CONTROL (AR9170_UART_REG_BASE + 0x010)
49 #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO 0x02
50 #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO 0x04
52 #define AR9170_UART_REG_LINE_CONTROL (AR9170_UART_REG_BASE + 0x014)
53 #define AR9170_UART_REG_MODEM_CONTROL (AR9170_UART_REG_BASE + 0x018)
54 #define AR9170_UART_MODEM_CTRL_DTR_BIT 0x01
55 #define AR9170_UART_MODEM_CTRL_RTS_BIT 0x02
[all …]
/linux-6.8/arch/arm64/boot/dts/hisilicon/
Dhikey960-pinctrl.dtsi18 reg = <0x0 0xe896c000 0x0 0x1f0>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
25 &range 0 7 0
26 &range 8 116 0>;
30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
33 0x100 MUX_M1 /* PMU_HKADC_SSI */
[all …]
/linux-6.8/include/linux/
Dtifm.h19 FM_SET_INTERRUPT_ENABLE = 0x008,
20 FM_CLEAR_INTERRUPT_ENABLE = 0x00c,
21 FM_INTERRUPT_STATUS = 0x014
26 SOCK_CONTROL = 0x004,
27 SOCK_PRESENT_STATE = 0x008,
28 SOCK_DMA_ADDRESS = 0x00c,
29 SOCK_DMA_CONTROL = 0x010,
30 SOCK_DMA_FIFO_INT_ENABLE_SET = 0x014,
31 SOCK_DMA_FIFO_INT_ENABLE_CLEAR = 0x018,
32 SOCK_DMA_FIFO_STATUS = 0x020,
[all …]
/linux-6.8/drivers/gpu/drm/vc4/
Dvc4_hdmi_regs.h8 #define VC4_HDMI_PACKET_STRIDE 0x24
11 VC4_INVALID = 0,
166 VC4_HD_REG(HDMI_M_CTL, 0x000c),
167 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
168 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
169 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
170 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
171 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
172 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
173 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
/linux-6.8/drivers/gpu/drm/amd/amdgpu/
Damdgpu_doorbell.h100 AMDGPU_DOORBELL_KIQ = 0x000,
101 AMDGPU_DOORBELL_HIQ = 0x001,
102 AMDGPU_DOORBELL_DIQ = 0x002,
103 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
104 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
105 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
106 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
107 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
108 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
109 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
[all …]
/linux-6.8/arch/mips/include/asm/
Dmips-cpc.h33 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
60 #define MIPS_CPC_GCB_OFS 0x0000
61 #define MIPS_CPC_CLCB_OFS 0x2000
62 #define MIPS_CPC_COCB_OFS 0x4000
81 CPC_ACCESSOR_RW(32, 0x000, access)
84 CPC_ACCESSOR_RW(32, 0x008, seqdel)
87 CPC_ACCESSOR_RW(32, 0x010, rail)
90 CPC_ACCESSOR_RW(32, 0x018, resetlen)
93 CPC_ACCESSOR_RO(32, 0x020, revision)
96 CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
[all …]
/linux-6.8/drivers/dma/dw-axi-dmac/
Ddw-axi-dmac.h23 #define DMAC_MAX_BLK_SIZE 0x200000
146 #define COMMON_REG_LEN 0x100
147 #define CHAN_REG_LEN 0x100
150 #define DMAC_ID 0x000 /* R DMAC ID */
151 #define DMAC_COMPVER 0x008 /* R DMAC Component Version */
152 #define DMAC_CFG 0x010 /* R/W DMAC Configuration */
153 #define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
154 #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
155 #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
156 #define DMAC_CHSUSPREG 0x020 /* R/W DMAC Channel Suspend */
[all …]

12345678910>>...19