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/linux-6.8/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml112 pinctrl-0:
163 '^opp-?[0-9]+$':
225 reg = <0 0x08804000 0 0x1000>;
235 iommus = <&apps_smmu 0x4a0 0x0>;
236 qcom,dll-config = <0x0007642c>;
237 qcom,ddr-config = <0x80040868>;
/linux-6.8/arch/arm64/boot/dts/qcom/
Dqdu1000.dtsi24 #size-cells = <0>;
26 CPU0: cpu@0 {
29 reg = <0x0 0x0>;
30 clocks = <&cpufreq_hw 0>;
34 qcom,freq-domains = <&cpufreq_hw 0>;
52 reg = <0x0 0x100>;
53 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domains = <&cpufreq_hw 0>;
70 reg = <0x0 0x200>;
71 clocks = <&cpufreq_hw 0>;
[all …]
Dsm6125.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]
Dqcm2290.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
48 clocks = <&cpufreq_hw 0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
66 reg = <0x0 0x1>;
67 clocks = <&cpufreq_hw 0>;
72 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6375.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6115.dtsi29 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #size-cells = <0>;
42 CPU0: cpu@0 {
45 reg = <0x0 0x0>;
46 clocks = <&cpufreq_hw 0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x1>;
65 clocks = <&cpufreq_hw 0>;
70 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7280.dtsi80 #clock-cells = <0>;
86 #clock-cells = <0>;
97 reg = <0x0 0x004cd000 0x0 0x1000>;
101 reg = <0x0 0x80000000 0x0 0x600000>;
106 reg = <0x0 0x80600000 0x0 0x200000>;
111 reg = <0x0 0x80800000 0x0 0x60000>;
116 reg = <0x0 0x80860000 0x0 0x20000>;
122 reg = <0x0 0x80884000 0x0 0x10000>;
127 reg = <0x0 0x808ff000 0x0 0x1000>;
132 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
Dsm8150.dtsi32 #clock-cells = <0>;
39 #clock-cells = <0>;
47 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8650.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
48 #clock-cells = <0>;
57 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #size-cells = <0>;
74 CPU0: cpu@0 {
77 reg = <0 0>;
79 clocks = <&cpufreq_hw 0>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #size-cells = <0>;
72 CPU0: cpu@0 {
75 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi82 #clock-cells = <0>;
90 #clock-cells = <0>;
96 #size-cells = <0>;
98 CPU0: cpu@0 {
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
117 cache-size = <0x20000>;
123 cache-size = <0x400000>;
[all …]