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/linux/arch/arm/boot/dts/ti/omap/
H A Domap4460.dtsi12 cpu0: cpu@0 {
32 reg = <0x4a002260 0x4
33 0x4a00232C 0x4
34 0x4a002378 0x18>;
36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
39 #thermal-sensor-cells = <0>;
45 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
46 <0x4A002268 0x4>;
52 1025000 0 0 0 0 0
53 1200000 0 0 0 0 0
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra30-emc.yaml35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
126 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf300tl.dts191 reg = <0x10>;
210 mount-matrix = "-1", "0", "0",
211 "0", "-1", "0",
212 "0", "0", "1";
216 mount-matrix = "-1", "0", "0",
217 "0", "1", "0",
218 "0", "0", "-1";
223 mount-matrix = "0", "-1", "0",
224 "-1", "0", "0",
225 "0", "0", "1";
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra30-asus-p1801-t.dts47 reg = <0x80000000 0x80000000>;
57 alloc-ranges = <0x80000000 0x30000000>;
58 size = <0x10000000>; /* 256MiB */
64 reg = <0xabe01000 (1920 * 1080 * 4)>;
69 reg = <0xbfe00000 0x200000>; /* 2MB */
75 reg = <0xfea00000 0x10000>; /* 64kB */
76 console-size = <0x8000>; /* 32kB */
77 record-size = <0x400>; /* 1kB */
108 <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
127 pinctrl-0 = <&state_default>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
80 reg = <0x01c00000 0x1000>;
87 reg = <0x00018000 0x1c000>;
90 ranges = <0 0x00018000 0x1c000>;
92 ve_sram: sram-section@0 {
95 reg = <0x000000 0x1c000>;
102 reg = <0x01c0e000 0x1000>;
113 reg = <0x01c15000 0x1000>;
[all …]
/linux/include/net/
H A Dieee80211_radiotap.h29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
/linux/lib/tests/
H A Dbitfield_kunit.c17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
22 } while (0)
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
37 } while (0)
46 "be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \
52 } while (0)
58 } while (0)
68 CHECK_ENC_GET(16, 1, 0x000f, 0x0001); in test_bitfields_constants()
69 CHECK_ENC_GET(16, 3, 0x00f0, 0x0030); in test_bitfields_constants()
70 CHECK_ENC_GET(16, 5, 0x0f00, 0x0500); in test_bitfields_constants()
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/linux/tools/arch/riscv/include/asm/
H A Dcsr.h12 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
13 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
14 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
15 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
16 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
17 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
18 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
20 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
21 #define SR_FS_OFF _AC(0x00000000, UL)
22 #define SR_FS_INITIAL _AC(0x00002000, UL)
[all …]
/linux/drivers/crypto/amcc/
H A Dcrypto4xx_reg_def.h15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2166x-common.dtsi22 ranges = <0 0x34000000 0x102f83ac>;
28 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
33 reg = <0x01001f00 0x24>;
38 reg = <0x01003000 0x524>;
51 reg = <0x01004800 0x7f4>;
56 reg = <0x01006000 0x1c>;
65 ranges = <0 0x3e000000 0x0001c070>;
69 uartb: serial@0 {
71 reg = <0x00000000 0x118>;
81 reg = <0x00001000 0x118>;
[all …]
/linux/include/linux/mfd/
H A Dcs42l43-regs.h13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
[all …]
/linux/drivers/net/wireless/ath/ath6kl/
H A Dtarget.h26 #define AR6004_BOARD_EXT_DATA_SZ 0
28 #define RESET_CONTROL_ADDRESS 0x00004000
29 #define RESET_CONTROL_COLD_RST 0x00000100
30 #define RESET_CONTROL_MBOX_RST 0x00000004
32 #define CPU_CLOCK_STANDARD_S 0
33 #define CPU_CLOCK_STANDARD 0x00000003
34 #define CPU_CLOCK_ADDRESS 0x00000020
36 #define CLOCK_CONTROL_ADDRESS 0x00000028
38 #define CLOCK_CONTROL_LF_CLK32 0x00000004
40 #define SYSTEM_SLEEP_ADDRESS 0x000000c4
[all …]
/linux/drivers/video/fbdev/
H A Dcg6.c70 #define CG6_ROM_OFFSET 0x0UL
71 #define CG6_BROOKTREE_OFFSET 0x200000UL
72 #define CG6_DHC_OFFSET 0x240000UL
73 #define CG6_ALT_OFFSET 0x280000UL
74 #define CG6_FHC_OFFSET 0x300000UL
75 #define CG6_THC_OFFSET 0x301000UL
76 #define CG6_FBC_OFFSET 0x700000UL
77 #define CG6_TEC_OFFSET 0x701000UL
78 #define CG6_RAM_OFFSET 0x800000UL
92 #define CG6_FHC_1024 (0 << 11)
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_catalog.c15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000.h14 #define GMAC_CONTROL 0x00000000 /* Configuration */
15 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
16 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
17 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
18 #define GMAC_MII_ADDR 0x00000010 /* MII Address */
19 #define GMAC_MII_DATA 0x00000014 /* MII Data */
20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
21 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
22 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
[all …]
/linux/drivers/net/fddi/
H A Ddefza.h25 #define FZA_REG_BASE 0x100000 /* register base address */
26 #define FZA_REG_RESET 0x100200 /* reset, r/w */
27 #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
28 #define FZA_REG_STATUS 0x100402 /* status, r/o */
29 #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
30 #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
31 #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
34 #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
35 #define FZA_RESET_INIT 0x0001 /* switch into the reset state */
[all …]
/linux/sound/soc/fsl/
H A Dp1022_rdk.c30 #define CCSR_GUTS_PMUXCR_UART0_I2C1_MASK 0x0001c000
31 #define CCSR_GUTS_PMUXCR_UART0_I2C1_UART0_SSI 0x00010000
32 #define CCSR_GUTS_PMUXCR_UART0_I2C1_SSI 0x00018000
34 #define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK 0x00000c00
35 #define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_SSI 0x00000000
49 * co: The DMA controller (0 or 1)
50 * ch: The channel on the DMA controller (0, 1, 2, or 3)
77 unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
78 unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
90 * Returns: %0 on success or negative errno value on error
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dvega10_ip_offset.h36 …t struct IP_BASE __maybe_unused NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400…
37 { { 0, 0, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } } } };
41 …t struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400…
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
[all …]

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