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12

/linux-5.10/arch/arm/boot/dts/
Domap4460.dtsi15 cpu0: cpu@0 {
42 reg = <0x4a002260 0x4
43 0x4a00232C 0x4
44 0x4a002378 0x18>;
46 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
49 #thermal-sensor-cells = <0>;
55 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
56 <0x4A002268 0x4>;
62 1025000 0 0 0 0 0
63 1200000 0 0 0 0 0
[all …]
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
Dbcm23550.dtsi48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0>;
61 secondary-boot-reg = <0x35004178>;
70 secondary-boot-reg = <0x35004178>;
79 secondary-boot-reg = <0x35004178>;
88 ranges = <0 0x34000000 0x102f83ac>;
94 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
99 reg = <0x01001f00 0x24>;
104 reg = <0x01003000 0x524>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml40 "^emc-timings-[0-9]+$":
49 "^timing-[0-9]+$":
62 minimum: 0
78 Mode Register 0.
85 minimum: 0
224 reg = <0x7000f400 0x400>;
225 interrupts = <0 78 4>;
236 nvidia,emc-auto-cal-interval = <0x001fffff>;
237 nvidia,emc-mode-1 = <0x80100002>;
238 nvidia,emc-mode-2 = <0x80200018>;
[all …]
/linux-5.10/arch/powerpc/boot/
Ddcr.h8 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
12 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
16 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
21 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
25 #define DCRN_SDRAM0_CFGADDR 0x010
26 #define DCRN_SDRAM0_CFGDATA 0x011
35 #define SDRAM0_B0CR 0x40
36 #define SDRAM0_B1CR 0x44
37 #define SDRAM0_B2CR 0x48
38 #define SDRAM0_B3CR 0x4c
[all …]
/linux-5.10/arch/riscv/include/asm/
Dcsr.h13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF _AC(0x00000000, UL)
23 #define SR_FS_INITIAL _AC(0x00002000, UL)
[all …]
/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
Dsun50i-a64.dtsi46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
[all …]
/linux-5.10/drivers/video/fbdev/mb862xx/
Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
/linux-5.10/lib/
Dbitfield_kunit.c17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
22 } while (0)
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
37 } while (0)
46 "be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \
52 } while (0)
58 } while (0)
68 CHECK_ENC_GET(16, 1, 0x000f, 0x0001); in test_bitfields_constants()
69 CHECK_ENC_GET(16, 3, 0x00f0, 0x0030); in test_bitfields_constants()
70 CHECK_ENC_GET(16, 5, 0x0f00, 0x0500); in test_bitfields_constants()
[all …]
/linux-5.10/drivers/gpu/drm/gma500/
Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/linux-5.10/drivers/crypto/amcc/
Dcrypto4xx_reg_def.h15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
[all …]
/linux-5.10/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux-5.10/drivers/net/wireless/ath/ath6kl/
Dtarget.h26 #define AR6004_BOARD_EXT_DATA_SZ 0
28 #define RESET_CONTROL_ADDRESS 0x00004000
29 #define RESET_CONTROL_COLD_RST 0x00000100
30 #define RESET_CONTROL_MBOX_RST 0x00000004
32 #define CPU_CLOCK_STANDARD_S 0
33 #define CPU_CLOCK_STANDARD 0x00000003
34 #define CPU_CLOCK_ADDRESS 0x00000020
36 #define CLOCK_CONTROL_ADDRESS 0x00000028
38 #define CLOCK_CONTROL_LF_CLK32 0x00000004
40 #define SYSTEM_SLEEP_ADDRESS 0x000000c4
[all …]
/linux-5.10/drivers/video/fbdev/
Dcg6.c70 #define CG6_ROM_OFFSET 0x0UL
71 #define CG6_BROOKTREE_OFFSET 0x200000UL
72 #define CG6_DHC_OFFSET 0x240000UL
73 #define CG6_ALT_OFFSET 0x280000UL
74 #define CG6_FHC_OFFSET 0x300000UL
75 #define CG6_THC_OFFSET 0x301000UL
76 #define CG6_FBC_OFFSET 0x700000UL
77 #define CG6_TEC_OFFSET 0x701000UL
78 #define CG6_RAM_OFFSET 0x800000UL
92 #define CG6_FHC_1024 (0 << 11)
[all …]
/linux-5.10/drivers/net/ethernet/broadcom/
Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h14 #define GMAC_CONTROL 0x00000000 /* Configuration */
15 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
16 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
17 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
18 #define GMAC_MII_ADDR 0x00000010 /* MII Address */
19 #define GMAC_MII_DATA 0x00000014 /* MII Data */
20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
21 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
22 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
[all …]
/linux-5.10/sound/soc/fsl/
Dp1022_rdk.c30 #define CCSR_GUTS_PMUXCR_UART0_I2C1_MASK 0x0001c000
31 #define CCSR_GUTS_PMUXCR_UART0_I2C1_UART0_SSI 0x00010000
32 #define CCSR_GUTS_PMUXCR_UART0_I2C1_SSI 0x00018000
34 #define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK 0x00000c00
35 #define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_SSI 0x00000000
49 * co: The DMA controller (0 or 1)
50 * ch: The channel on the DMA controller (0, 1, 2, or 3)
77 unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
78 unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
110 guts_set_dmuxcr(guts, mdata->dma_id[0], mdata->dma_channel_id[0], in p1022_rdk_machine_probe()
[all …]
Dp1022_ds.c23 #define CCSR_GUTS_PMUXCR_UART0_I2C1_MASK 0x0001c000
24 #define CCSR_GUTS_PMUXCR_UART0_I2C1_UART0_SSI 0x00010000
25 #define CCSR_GUTS_PMUXCR_UART0_I2C1_SSI 0x00018000
27 #define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK 0x00000c00
28 #define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_SSI 0x00000000
42 * co: The DMA controller (0 or 1)
43 * ch: The channel on the DMA controller (0, 1, 2, or 3)
70 unsigned int ssi_id; /* 0 = SSI1, 1 = SSI2, etc */
71 unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
72 unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
[all …]
/linux-5.10/drivers/net/fddi/
Ddefza.h25 #define FZA_REG_BASE 0x100000 /* register base address */
26 #define FZA_REG_RESET 0x100200 /* reset, r/w */
27 #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
28 #define FZA_REG_STATUS 0x100402 /* status, r/o */
29 #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
30 #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
31 #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
34 #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
35 #define FZA_RESET_INIT 0x0001 /* switch into the reset state */
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/
Dvega10_ip_offset.h38 static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0…
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } } } };
43 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0…
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } } } };
[all …]
Drenoir_ip_offset.h39 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0 } },
[all …]
/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h50 VG1 = 0,
60 MIXER0 = 0,
66 INTF_LCDC_DTV = 0,
78 FRAME_LINEAR = 0,
84 SCALE_FIR = 0,
90 DMA_P = 0,
95 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001
96 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002
97 #define MDP4_IRQ_DMA_S_DONE 0x00000004
98 #define MDP4_IRQ_DMA_E_DONE 0x00000008
[all …]
/linux-5.10/include/linux/ssb/
Dssb_driver_chipcommon.h8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
17 #define SSB_CHIPCO_CHIPID 0x0000
18 #define SSB_CHIPCO_IDMASK 0x0000FFFF
19 #define SSB_CHIPCO_REVMASK 0x000F0000
21 #define SSB_CHIPCO_PACKMASK 0x00F00000
23 #define SSB_CHIPCO_NRCORESMASK 0x0F000000
25 #define SSB_CHIPCO_CAP 0x0004 /* Capabilities */
26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
27 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
28 #define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */
[all …]

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