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12

/linux-5.10/arch/arm/boot/dts/
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
/linux-5.10/sound/soc/codecs/
Dcs35l36.h16 #define CS35L36_FIRSTREG 0x00000000
17 #define CS35L36_LASTREG 0x00E037FC
18 #define CS35L36_SW_RESET 0x00000000
19 #define CS35L36_SW_REV 0x00000004
20 #define CS35L36_HW_REV 0x00000008
21 #define CS35L36_TESTKEY_CTRL 0x00000020
22 #define CS35L36_USERKEY_CTL 0x00000024
23 #define CS35L36_OTP_MEM30 0x00000478
24 #define CS35L36_OTP_CTRL1 0x00000500
25 #define CS35L36_OTP_CTRL2 0x00000504
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml40 "^emc-timings-[0-9]+$":
49 "^timing-[0-9]+$":
62 minimum: 0
78 Mode Register 0.
85 minimum: 0
224 reg = <0x7000f400 0x400>;
225 interrupts = <0 78 4>;
236 nvidia,emc-auto-cal-interval = <0x001fffff>;
237 nvidia,emc-mode-1 = <0x80100002>;
238 nvidia,emc-mode-2 = <0x80200018>;
[all …]
/linux-5.10/drivers/net/ipa/
Dipa_reg.h68 #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038
70 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c
71 #define ENABLE_FMASK GENMASK(0, 0)
90 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044
91 #define RX_FMASK GENMASK(0, 0)
122 #define IPA_REG_ROUTE_OFFSET 0x00000048
123 #define ROUTE_DIS_FMASK GENMASK(0, 0)
130 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054
131 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0)
134 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074
[all …]
/linux-5.10/sound/pci/cs46xx/
Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux-5.10/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h31 #define XAE_OPTION_PROMISC (1 << 0)
74 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
75 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
76 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
77 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
79 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
80 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
81 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
82 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
84 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
[all …]
/linux-5.10/drivers/gpu/drm/rockchip/
Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux-5.10/drivers/video/fbdev/riva/
Driva_hw.c65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv3Busy()
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); in nv3Busy()
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv4Busy()
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv4Busy()
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv10Busy()
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv10Busy()
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
94 if(Lock) cr11 |= 0x80; in vgaLockUnlock()
95 else cr11 &= ~0x80; in vgaLockUnlock()
[all …]
/linux-5.10/drivers/net/wireless/ath/ath11k/
Dhw.c18 case 0: in ath11k_hw_ipq8074_mac_from_pdev_id()
19 return 0; in ath11k_hw_ipq8074_mac_from_pdev_id()
47 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; in ath11k_init_wmi_config_qca6390()
56 config->num_mcast_groups = 0; in ath11k_init_wmi_config_qca6390()
57 config->num_mcast_table_elems = 0; in ath11k_init_wmi_config_qca6390()
58 config->mcast2ucast_mode = 0; in ath11k_init_wmi_config_qca6390()
60 config->num_wds_entries = 0; in ath11k_init_wmi_config_qca6390()
61 config->dma_burst_size = 0; in ath11k_init_wmi_config_qca6390()
62 config->rx_skip_defrag_timeout_dup_detection_check = 0; in ath11k_init_wmi_config_qca6390()
65 config->num_msdu_desc = 0x400; in ath11k_init_wmi_config_qca6390()
[all …]
/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dpp_overdriver.c28 …{ 0x0213EA94DE0E4964, 0x00003C96, 0xFFFFE226, 0x00000656, 0x00002203, 0xFFFFF201, 0x000003FF, 0x00…
29 …{ 0x0213EA94DE0A1884, 0x00003CC5, 0xFFFFE23A, 0x0000064E, 0x00002258, 0xFFFFF1F7, 0x000003FC, 0x00…
30 …{ 0x0213EA94DE0E31A4, 0x00003CAF, 0xFFFFE36E, 0x00000602, 0x00001E98, 0xFFFFF569, 0x00000357, 0x00…
31 …{ 0x0213EA94DE2C1144, 0x0000391A, 0xFFFFE548, 0x000005C9, 0x00001B98, 0xFFFFF707, 0x00000324, 0x00…
32 …{ 0x0213EA94DE2C18C4, 0x00003821, 0xFFFFE674, 0x00000597, 0x00002196, 0xFFFFF361, 0x000003C0, 0x00…
33 …{ 0x0213EA94DE263884, 0x000044A2, 0xFFFFDCB7, 0x00000738, 0x0000325C, 0xFFFFE6A7, 0x000005E6, 0x00…
34 …{ 0x0213EA94DE082924, 0x00004057, 0xFFFFE1CF, 0x0000063C, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00…
35 …{ 0x0213EA94DE284924, 0x00003FD0, 0xFFFFDF0F, 0x000006E5, 0x0000267C, 0xFFFFEE2D, 0x000004AB, 0x00…
36 …{ 0x0213EA94DE280904, 0x00003F13, 0xFFFFE010, 0x000006AD, 0x000020E7, 0xFFFFF266, 0x000003EC, 0x00…
37 …{ 0x0213EA94DE082044, 0x00004088, 0xFFFFDFAB, 0x000006B6, 0x0000252B, 0xFFFFEFDB, 0x00000458, 0x00…
[all …]
/linux-5.10/drivers/mfd/
Dwm8998-tables.c22 { 0x0212, 0x0000 },
23 { 0x0211, 0x0014 },
24 { 0x04E4, 0x0E0D },
25 { 0x04E5, 0x0E0D },
26 { 0x04E6, 0x0E0D },
27 { 0x04EB, 0x060E },
28 { 0x0441, 0xC759 },
29 { 0x0442, 0x2A08 },
30 { 0x0443, 0x5CFA },
31 { 0x026E, 0x0064 },
[all …]
Dwm8997-tables.c18 { 0x80, 0x0003 },
19 { 0x214, 0x0008 },
20 { 0x458, 0x0000 },
21 { 0x0081, 0xE022 },
22 { 0x294, 0x0000 },
23 { 0x80, 0x0000 },
24 { 0x171, 0x0000 },
31 case 0: in wm8997_patch()
36 return 0; in wm8997_patch()
60 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[all …]
Dcs47l24-tables.c21 { 0x80, 0x3 },
22 { 0x27C, 0x0010 },
23 { 0x221, 0x0070 },
24 { 0x80, 0x0 },
36 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
37 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
183 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
184 { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
185 { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
186 { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
[all …]
Dcs47l15-tables.c19 { 0x8C, 0x5555 },
20 { 0x8C, 0xAAAA },
21 { 0x314, 0x0080 },
22 { 0x4A8, 0x6023 },
23 { 0x4A9, 0x6023 },
24 { 0x4D4, 0x0008 },
25 { 0x4CF, 0x0F00 },
26 { 0x4D7, 0x1B2B },
27 { 0x8C, 0xCCCC },
28 { 0x8C, 0x3333 },
[all …]
Dcs47l35-tables.c18 { 0x460, 0x0c40 },
19 { 0x461, 0xcd1a },
20 { 0x462, 0x0c40 },
21 { 0x463, 0xb53b },
22 { 0x464, 0x0c40 },
23 { 0x465, 0x7503 },
24 { 0x466, 0x0c40 },
25 { 0x467, 0x4a41 },
26 { 0x468, 0x0041 },
27 { 0x469, 0x3491 },
[all …]
Dwm5102-tables.c22 { 0x80, 0x0003 },
23 { 0x221, 0x0090 },
24 { 0x211, 0x0014 },
25 { 0x212, 0x0000 },
26 { 0x214, 0x000C },
27 { 0x171, 0x0002 },
28 { 0x171, 0x0000 },
29 { 0x461, 0x8000 },
30 { 0x463, 0x50F0 },
31 { 0x465, 0x4820 },
[all …]
Dcs47l92-tables.c21 { 0x3A2, 0x2C29 },
22 { 0x3A3, 0x0E00 },
23 { 0x281, 0x0000 },
24 { 0x282, 0x0000 },
25 { 0x4EA, 0x0100 },
26 { 0x22B, 0x0000 },
27 { 0x4A0, 0x0080 },
28 { 0x4A1, 0x0000 },
29 { 0x4A2, 0x0000 },
30 { 0x180B, 0x033F },
[all …]
Dwm5110-tables.c22 { 0x80, 0x3 },
23 { 0x44, 0x20 },
24 { 0x45, 0x40 },
25 { 0x46, 0x60 },
26 { 0x47, 0x80 },
27 { 0x48, 0xa0 },
28 { 0x51, 0x13 },
29 { 0x52, 0x33 },
30 { 0x53, 0x53 },
31 { 0x54, 0x73 },
[all …]
/linux-5.10/drivers/net/ethernet/broadcom/
Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/linux-5.10/drivers/gpu/drm/msm/adreno/
Da4xx.xml.h100 TILE4_LINEAR = 0,
259 DEPTH4_NONE = 0,
266 CCU_BUSY_CYCLES = 0,
285 CP_ALWAYS_COUNT = 0,
329 RAS_SUPER_TILES = 0,
346 TSE_INPUT_PRIM = 0,
366 HLSQ_SP_VS_STAGE_CONSTANT = 0,
394 PC_VIS_STREAMS_LOADED = 0,
437 PWR_CORE_CLOCK_CYCLES = 0,
442 RB_BUSY_CYCLES = 0,
[all …]
Da5xx.xml.h100 TILE5_LINEAR = 0,
261 DEPTH5_NONE = 0,
268 BLIT_MRT0 = 0,
281 PERF_CP_ALWAYS_COUNT = 0,
315 PERF_RBBM_ALWAYS_COUNT = 0,
332 PERF_PC_BUSY_CYCLES = 0,
372 PERF_VFD_BUSY_CYCLES = 0,
406 PERF_HLSQ_BUSY_CYCLES = 0,
424 PERF_VPC_BUSY_CYCLES = 0,
444 PERF_TSE_BUSY_CYCLES = 0,
[all …]
/linux-5.10/drivers/net/wireless/broadcom/b43/
Dtables_lpphy.c26 #define B206X_FLAG_A 0x01 /* Flag: Init in A mode */
27 #define B206X_FLAG_G 0x02 /* Flag: Init in G mode */
30 /* { .offset = B2062_N_COMM1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
31 /* { .offset = 0x0001, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
32 /* { .offset = B2062_N_COMM2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
33 /* { .offset = B2062_N_COMM3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
34 …{ .offset = B2062_N_COMM4, .value_a = 0x0001, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLA…
35 /* { .offset = B2062_N_COMM5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
36 /* { .offset = B2062_N_COMM6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
37 /* { .offset = B2062_N_COMM7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dpolaris10_pwrvirus.h27 #define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a
28 #define mmCP_HYP_MEC1_UCODE_DATA 0xf81b
29 #define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c
30 #define mmCP_HYP_MEC2_UCODE_DATA 0xf81d
49 { 0x00000000, mmRLC_CNTL },
50 { 0x00000002, mmRLC_SRM_CNTL },
51 { 0x15000000, mmCP_ME_CNTL },
52 { 0x50000000, mmCP_MEC_CNTL },
53 { 0x80000004, mmCP_DFY_CNTL },
54 { 0x0840800a, mmCP_RB0_CNTL },
[all …]

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