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/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/linux-5.10/arch/arm/boot/dts/
Dimx6dl-eckelmann-ci4x10.dts23 reg = <0x10000000 0x40000000>;
29 #clock-cells = <0>;
35 pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
47 pinctrl-0 = <&pinctrl_siox>;
57 pinctrl-0 = <&pinctrl_flexcan1>;
63 pinctrl-0 = <&pinctrl_flexcan2>;
69 pinctrl-0 = <&pinctrl_ecspi2>;
73 flash@0 {
75 reg = <0>;
82 pinctrl-0 = <&pinctrl_ecspi1>;
[all …]
/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar956x_initvals.h41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/linux-5.10/arch/sh/include/cpu-sh4/cpu/
Ddma-register.h17 #define CHCR_TS_LOW_MASK 0x00000018
19 #define CHCR_TS_HIGH_MASK 0
20 #define CHCR_TS_HIGH_SHIFT 0
26 #define CHCR_TS_LOW_MASK 0x00000018
28 #define CHCR_TS_HIGH_MASK 0x00300000
34 #define CHCR_TS_LOW_MASK 0x00000018
36 #define CHCR_TS_HIGH_MASK 0x00100000
42 XMIT_SZ_8BIT = 0,
48 XMIT_SZ_128BIT_BLK = 0xb,
49 XMIT_SZ_256BIT_BLK = 0xc,
[all …]
/linux-5.10/drivers/staging/media/rkisp1/
Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/linux-5.10/drivers/gpu/drm/msm/dp/
Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_1_0_sh_mask.h26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
/linux-5.10/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dg94.c35 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); in g94_bus_hwsq_exec()
36 nvkm_wr32(device, 0x001304, 0x00000000); in g94_bus_hwsq_exec()
37 nvkm_wr32(device, 0x001318, 0x00000000); in g94_bus_hwsq_exec()
38 for (i = 0; i < size; i++) in g94_bus_hwsq_exec()
39 nvkm_wr32(device, 0x080000 + (i * 4), data[i]); in g94_bus_hwsq_exec()
40 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); in g94_bus_hwsq_exec()
41 nvkm_wr32(device, 0x00130c, 0x00000001); in g94_bus_hwsq_exec()
44 if (!(nvkm_rd32(device, 0x001308) & 0x00000100)) in g94_bus_hwsq_exec()
46 ) < 0) in g94_bus_hwsq_exec()
49 return 0; in g94_bus_hwsq_exec()
Dnv50.c36 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); in nv50_bus_hwsq_exec()
37 nvkm_wr32(device, 0x001304, 0x00000000); in nv50_bus_hwsq_exec()
38 for (i = 0; i < size; i++) in nv50_bus_hwsq_exec()
39 nvkm_wr32(device, 0x001400 + (i * 4), data[i]); in nv50_bus_hwsq_exec()
40 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); in nv50_bus_hwsq_exec()
41 nvkm_wr32(device, 0x00130c, 0x00000003); in nv50_bus_hwsq_exec()
44 if (!(nvkm_rd32(device, 0x001308) & 0x00000100)) in nv50_bus_hwsq_exec()
46 ) < 0) in nv50_bus_hwsq_exec()
49 return 0; in nv50_bus_hwsq_exec()
57 u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); in nv50_bus_intr()
[all …]
/linux-5.10/include/linux/amba/
Dclcd-regs.h17 #define CLCD_TIM0 0x00000000
18 #define CLCD_TIM1 0x00000004
19 #define CLCD_TIM2 0x00000008
20 #define CLCD_TIM3 0x0000000c
21 #define CLCD_UBAS 0x00000010
22 #define CLCD_LBAS 0x00000014
24 #define CLCD_PL110_IENB 0x00000018
25 #define CLCD_PL110_CNTL 0x0000001c
26 #define CLCD_PL110_STAT 0x00000020
27 #define CLCD_PL110_INTR 0x00000024
[all …]
/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/linux-5.10/drivers/video/fbdev/mb862xx/
Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
/linux-5.10/drivers/gpu/drm/pl111/
Dpl111_drm.h29 #define CLCD_TIM0 0x00000000
30 #define CLCD_TIM1 0x00000004
31 #define CLCD_TIM2 0x00000008
32 #define CLCD_TIM3 0x0000000c
33 #define CLCD_UBAS 0x00000010
34 #define CLCD_LBAS 0x00000014
36 #define CLCD_PL110_IENB 0x00000018
37 #define CLCD_PL110_CNTL 0x0000001c
38 #define CLCD_PL110_STAT 0x00000020
39 #define CLCD_PL110_INTR 0x00000024
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dregsnv04.h5 #define NV04_PFB_BOOT_0 0x00100000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
9 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
10 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
11 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
12 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
13 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
14 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
/linux-5.10/tools/testing/selftests/powerpc/vphn/
Dtest-vphn.c29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_6_0_sh_mask.h26 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL
27 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
28 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L
29 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
30 #define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL
31 #define GPIOPAD_A__GPIO_A__SHIFT 0x00000000
32 #define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL
33 #define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000
34 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L
35 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005
[all …]
/linux-5.10/drivers/net/ethernet/qlogic/qed/
Dqed_init_ops.c25 0,
26 0,
27 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
28 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
29 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
30 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
31 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
32 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
33 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
34 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/linux-5.10/sound/soc/atmel/
Datmel-pdmic.h7 #define PDMIC_CR 0x00000000
9 #define PDMIC_CR_SWRST 0x1
10 #define PDMIC_CR_SWRST_MASK BIT(0)
11 #define PDMIC_CR_SWRST_SHIFT (0)
13 #define PDMIC_CR_ENPDM_DIS 0x0
14 #define PDMIC_CR_ENPDM_EN 0x1
18 #define PDMIC_MR 0x00000004
20 #define PDMIC_MR_CLKS_PCK 0x0
21 #define PDMIC_MR_CLKS_GCK 0x1
28 #define PDMIC_CDR 0x00000014
[all …]
/linux-5.10/include/video/
Dnewport.h34 #define DM1_PLANES 0x00000007
35 #define DM1_NOPLANES 0x00000000
36 #define DM1_RGBPLANES 0x00000001
37 #define DM1_RGBAPLANES 0x00000002
38 #define DM1_OLAYPLANES 0x00000004
39 #define DM1_PUPPLANES 0x00000005
40 #define DM1_CIDPLANES 0x00000006
42 #define NPORT_DMODE1_DDMASK 0x00000018
43 #define NPORT_DMODE1_DD4 0x00000000
44 #define NPORT_DMODE1_DD8 0x00000008
[all …]

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