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/linux-5.10/drivers/pinctrl/spear/
Dpinctrl-spear300.c21 #define PMX_CONFIG_REG 0x00
22 #define MODE_CONFIG_REG 0x04
25 #define NAND_MODE (1 << 0)
43 .mask = 0x0000000F,
44 .val = 0x00,
51 .mask = 0x0000000F,
52 .val = 0x01,
59 .mask = 0x0000000F,
60 .val = 0x02,
67 .mask = 0x0000000F,
[all …]
/linux-5.10/arch/x86/kernel/cpu/
Dscattered.c27 { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
28 { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
29 { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
30 { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
31 { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
32 { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
33 { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
34 { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
35 { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
36 { X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/linux-5.10/net/core/
Dptp_classifier.c16 * jneq #0x800, test_ipv6 ; ETH_P_IP ?
20 * jset #0x1fff, drop_ipv4 ; don't allow fragments
21 * ldxb 4*([14]&0xf) ; load IP header len
25 * and #0xf ; mask PTP_CLASS_VMASK
26 * or #0x10 ; PTP_CLASS_IPV4
28 * drop_ipv4: ret #0x0 ; PTP_CLASS_NONE
32 * jneq #0x86dd, test_8021q ; ETH_P_IPV6 ?
38 * and #0xf ; mask PTP_CLASS_VMASK
39 * or #0x20 ; PTP_CLASS_IPV6
41 * drop_ipv6: ret #0x0 ; PTP_CLASS_NONE
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
Dsdma0_4_1_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/linux-5.10/drivers/scsi/lpfc/
Dlpfc_hw4.h35 * #define example_bit_field_MASK 0x03
46 * bf_set(example_bit_field, &t1, 0);
70 #define lpfc_sli_intf_valid_MASK 0x00000007
74 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
76 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
78 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
80 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
84 #define lpfc_sli_intf_if_type_MASK 0x0000000F
86 #define LPFC_SLI_INTF_IF_TYPE_0 0
91 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/linux-5.10/drivers/gpu/drm/etnaviv/
Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
[all …]
/linux-5.10/drivers/net/wireless/ralink/rt2x00/
Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
/linux-5.10/drivers/gpu/drm/radeon/
Dsi_blit_shaders.c33 0xc0066900,
34 0x00000000,
35 0x00000060, /* DB_RENDER_CONTROL */
36 0x00000000, /* DB_COUNT_CONTROL */
37 0x00000000, /* DB_DEPTH_VIEW */
38 0x0000002a, /* DB_RENDER_OVERRIDE */
39 0x00000000, /* DB_RENDER_OVERRIDE2 */
40 0x00000000, /* DB_HTILE_DATA_BASE */
42 0xc0046900,
43 0x00000008,
[all …]
Dcik_blit_shaders.c33 0xc0066900,
34 0x00000000,
35 0x00000060, /* DB_RENDER_CONTROL */
36 0x00000000, /* DB_COUNT_CONTROL */
37 0x00000000, /* DB_DEPTH_VIEW */
38 0x0000002a, /* DB_RENDER_OVERRIDE */
39 0x00000000, /* DB_RENDER_OVERRIDE2 */
40 0x00000000, /* DB_HTILE_DATA_BASE */
42 0xc0046900,
43 0x00000008,
[all …]
Dcayman_blit_shaders.c43 0xc0066900,
44 0x00000000,
45 0x00000060, /* DB_RENDER_CONTROL */
46 0x00000000, /* DB_COUNT_CONTROL */
47 0x00000000, /* DB_DEPTH_VIEW */
48 0x0000002a, /* DB_RENDER_OVERRIDE */
49 0x00000000, /* DB_RENDER_OVERRIDE2 */
50 0x00000000, /* DB_HTILE_DATA_BASE */
52 0xc0026900,
53 0x0000000a,
[all …]
/linux-5.10/drivers/bus/
Dda8xx-mstpri.c29 #define DA8XX_MSTPRI0_OFFSET 0
34 DA8XX_MSTPRI_ARM_I = 0,
62 .shift = 0,
63 .mask = 0x0000000f,
68 .mask = 0x000000f0,
73 .mask = 0x000f0000,
78 .mask = 0x00f00000,
82 .shift = 0,
83 .mask = 0x0000000f,
88 .mask = 0x000000f0,
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgp100.c40 nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]); in gp100_gr_zbc_clear_color()
41 nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]); in gp100_gr_zbc_clear_color()
42 nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]); in gp100_gr_zbc_clear_color()
43 nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]); in gp100_gr_zbc_clear_color()
46 nvkm_mask(device, 0x418100 + ((znum / 4) * 4), in gp100_gr_zbc_clear_color()
47 0x0000007f << ((znum % 4) * 7), in gp100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds); in gp100_gr_zbc_clear_depth()
60 nvkm_mask(device, 0x41814c + ((znum / 4) * 4), in gp100_gr_zbc_clear_depth()
61 0x0000007f << ((znum % 4) * 7), in gp100_gr_zbc_clear_depth()
75 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gp100_gr_init_shader_exceptions()
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s.h3 /* 0x0000: ctx_dma */
4 /* 0x0000: ctx_dma_query */
5 0x00000000,
6 /* 0x0004: ctx_dma_src */
7 0x00000000,
8 /* 0x0008: ctx_dma_dst */
9 0x00000000,
10 /* 0x000c: ctx_query_address_high */
11 0x00000000,
12 /* 0x0010: ctx_query_address_low */
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/
Dnv50.c59 if ((ctx->outp[0] & 0x0000000f) != ctx->desc.outp_type) in mxm_match_dcb()
66 if ((desc & 0x00000000000000f0) >= 0x20) { in mxm_match_dcb()
69 if ((ctx->outp[0] & 0x0f000000) != (link & 0x0f) << 24) in mxm_match_dcb()
73 link = (link & 0x30) >> 4; in mxm_match_dcb()
74 if ((link & ((ctx->outp[1] & 0x00000030) >> 4)) != link) in mxm_match_dcb()
83 data[0] &= ~0xf0; in mxm_match_dcb()
85 mxms_foreach(mxm, 0x01, mxm_match_tmds_partner, ctx)) { in mxm_match_dcb()
86 data[0] |= 0x20; /* modify descriptor to match TMDS now */ in mxm_match_dcb()
88 data[0] |= 0xf0; in mxm_match_dcb()
105 if (mxms_foreach(mxm, 0x01, mxm_match_dcb, &ctx)) { in mxm_dcb_sanitise_entry()
[all …]
/linux-5.10/drivers/net/wireless/ath/ath9k/
Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]

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