Home
last modified time | relevance | path

Searched +full:0 +full:x00000007 (Results 1 – 25 of 348) sorted by relevance

12345678910>>...14

/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/linux-5.10/arch/arm/boot/dts/
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
Dtegra20-acer-a500-picasso.dts36 memory@0 {
37 reg = <0x00000000 0x40000000>;
47 reg = <0x2ffe0000 0x10000>; /* 64kB */
48 console-size = <0x8000>; /* 32kB */
49 record-size = <0x400>; /* 1kB */
55 alloc-ranges = <0x30000000 0x10000000>;
56 size = <0x10000000>; /* 256MiB */
67 port@0 {
91 pinctrl-0 = <&state_default>;
406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2_internal.h21 #define HW_ATL2_MAC_UC 0U
27 #define HW_ATL2_INT_MASK (0xFFFFFFFFU)
37 #define HW_ATL2_INTR_MODER_MAX 0x1FF
38 #define HW_ATL2_INTR_MODER_MIN 0xFF
48 #define HW_ATL2_FW_SM_ACT_RSLVR 0x3U
50 #define HW_ATL2_RPF_TAG_UC_OFFSET 0x0
51 #define HW_ATL2_RPF_TAG_ALLMC_OFFSET 0x6
52 #define HW_ATL2_RPF_TAG_ET_OFFSET 0x7
53 #define HW_ATL2_RPF_TAG_VLAN_OFFSET 0xA
54 #define HW_ATL2_RPF_TAG_UNTAG_OFFSET 0xE
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/
Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
/linux-5.10/arch/mips/pic32/pic32mzda/
Dearly_clk.c11 #define ICLK_MASK 0x00000080
12 #define PLLDIV_MASK 0x00000007
13 #define CUROSC_MASK 0x00000007
14 #define PLLMUL_MASK 0x0000007F
15 #define PB_MASK 0x00000007
16 #define FRC1 0
24 #define OSCCON 0x0000
25 #define SPLLCON 0x0020
26 #define PB1DIV 0x0140
30 u32 osc_freq = 0; in pic32_get_sysclk()
[all …]
/linux-5.10/scripts/
Dextract_xc3028.pl25 my $debug=0;
50 while ($length > 0) {
66 my $msb = ($val >> 8) &0xff;
67 my $lsb = $val & 0xff;
75 my $l3 = ($val >> 24) & 0xff;
76 my $l2 = ($val >> 16) & 0xff;
77 my $l1 = ($val >> 8) & 0xff;
78 my $l0 = $val & 0xff;
87 my $l7 = ($msb_val >> 24) & 0xff;
88 my $l6 = ($msb_val >> 16) & 0xff;
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl837d.h28 #define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0…
29 #define NV837D_SOR_SET_CONTROL_OWNER 3:0
30 #define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
31 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
32 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
34 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
35 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
36 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
37 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
39 #define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
[all …]
Dcl887d.h27 #define NV887D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0…
28 #define NV887D_SOR_SET_CONTROL_OWNER 3:0
29 #define NV887D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
30 #define NV887D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
31 #define NV887D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
33 #define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
34 #define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
35 #define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
36 #define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
38 #define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml40 "^emc-timings-[0-9]+$":
49 "^timing-[0-9]+$":
62 minimum: 0
78 Mode Register 0.
85 minimum: 0
224 reg = <0x7000f400 0x400>;
225 interrupts = <0 78 4>;
236 nvidia,emc-auto-cal-interval = <0x001fffff>;
237 nvidia,emc-mode-1 = <0x80100002>;
238 nvidia,emc-mode-2 = <0x80200018>;
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_1_0_sh_mask.h26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/linux-5.10/arch/m68k/include/asm/
Dm54xxgpt.h20 #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
21 #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
22 #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
23 #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
24 #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
25 #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
26 #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
27 #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
28 #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
29 #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
[all …]
/linux-5.10/drivers/media/pci/cx88/
Dcx88-tvaudio.c52 "Radio deemphasis time constant, 0=None, 1=50us (elsewhere), 2=75us (USA)");
58 } while (0)
96 for (i = 0; l[i].reg; i++) { in set_audio_registers()
120 cx_write(AUD_INIT_LD, 0x0001); in set_audio_start()
121 cx_write(AUD_SOFT_RESET, 0x0001); in set_audio_start()
130 cx_write(AUD_RATE_THRES_DMD, 0x000000C0); in set_audio_finish()
142 cx_write(AUD_I2SCNTL, 0); in set_audio_finish()
143 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */ in set_audio_finish()
151 cx_write(AUD_SOFT_RESET, 0x0000); in set_audio_finish()
166 {AUD_AFE_12DB_EN, 0x00000001}, in set_audio_standard_BTSC()
[all …]
/linux-5.10/drivers/net/wireless/ath/
Dreg.h20 #define AR_MIBC 0x0040
21 #define AR_MIBC_COW 0x00000001
22 #define AR_MIBC_FMC 0x00000002
23 #define AR_MIBC_CMC 0x00000004
24 #define AR_MIBC_MCS 0x00000008
26 #define AR_STA_ID0 0x8000
27 #define AR_STA_ID1 0x8004
28 #define AR_STA_ID1_SADH_MASK 0x0000ffff
34 #define AR_BSSMSKL 0x80e0
35 #define AR_BSSMSKU 0x80e4
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]
/linux-5.10/tools/testing/selftests/powerpc/vphn/
Dtest-vphn.c29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]

12345678910>>...14