| /linux-5.10/arch/arm/boot/dts/ |
| D | tegra124-apalis-emc.dtsi | 94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
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| D | tegra124-nyan-blaze-emc.dtsi | 78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
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| D | tegra124-nyan-big-emc.dtsi | 229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
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| D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
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| D | tegra20-acer-a500-picasso.dts | 36 memory@0 {
37 reg = <0x00000000 0x40000000>;
47 reg = <0x2ffe0000 0x10000>; /* 64kB */
48 console-size = <0x8000>; /* 32kB */
49 record-size = <0x400>; /* 1kB */
55 alloc-ranges = <0x30000000 0x10000000>;
56 size = <0x10000000>; /* 256MiB */
67 port@0 {
91 pinctrl-0 = <&state_default>;
406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]
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| D | tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
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| D | tegra20-colibri.dtsi | 11 memory@0 {
17 reg = <0x00000000 0x10000000>;
32 pinctrl-0 = <&state_default>;
424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
440 nand@0 {
441 reg = <0>;
449 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
477 reg = <0x34>;
506 regulator-name = "VDD_CPU_1.0V";
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
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| /linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | hsw_clear_kernel.c | 9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x00000160,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
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| D | ivb_clear_kernel.c | 9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x0000002c,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/ |
| D | vega10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
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| D | navi10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
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| /linux-5.10/tools/testing/selftests/powerpc/vphn/ |
| D | test-vphn.c | 29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
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| /linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/ |
| D | cl5039.h | 26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
[all …]
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| D | cla0b5.h | 27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
[all …]
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| D | cl837d.h | 28 #define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0…
29 #define NV837D_SOR_SET_CONTROL_OWNER 3:0
30 #define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
31 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
32 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
34 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
35 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
36 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
37 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
39 #define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
[all …]
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| D | cl907c.h | 28 #define NV907C_SET_PRESENT_CONTROL (0x00000084)
30 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
31 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
32 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
33 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_AT_FRAME (0x00000003)
35 #define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
36 #define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
40 #define NV907C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0…
41 #define NV907C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
42 #define NV907C_SET_BASE_LUT_LO (0x000000E0)
[all …]
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| D | cl907d.h | 27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_sh_mask.h | 26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/ |
| D | dce_6_0_sh_mask.h | 26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
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| /linux-5.10/drivers/staging/rtl8188eu/hal/ |
| D | mac_cfg.c | 14 0x026, 0x00000041,
15 0x027, 0x00000035,
16 0x428, 0x0000000A,
17 0x429, 0x00000010,
18 0x430, 0x00000000,
19 0x431, 0x00000001,
20 0x432, 0x00000002,
21 0x433, 0x00000004,
22 0x434, 0x00000005,
23 0x435, 0x00000006,
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 38 "^emc-timings-[0-9]+$":
48 "^timing-[0-9]+$":
79 minimum: 0
142 minimum: 0
340 reg = <0x70019000 0x1000>;
352 reg = <0x7001b000 0x1000>;
358 emc-timings-0 {
361 timing-0 {
364 nvidia,emc-auto-cal-config = <0xa1430000>;
365 nvidia,emc-auto-cal-config2 = <0x00000000>;
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_sh_mask.h | 26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_1_0_sh_mask.h | 26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
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