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/kvm-unit-tests/arm/
H A Dcstart64.S33 * Bootloader params are in x0-x3. See kernel doc
102 bl setup // x0 is the addr of the dtb
105 adrp x0, __argc
106 ldr w0, [x0, :lo12:__argc]
134 * x0 -- return code
155 \instr #0
160 stp x0, x1, [x10, #0]
181 adrp x0, auxinfo
182 ldr x0, [x0, :lo12:auxinfo + 8]
183 and x0, x0, #AUXINFO_MMU_OFF
[all …]
H A Dselftest.c34 int nr_tests = 0, len, i; in check_setup()
37 for (i = 0; i < argc; ++i) { in check_setup()
43 argv[i][len] = '\0'; in check_setup()
46 if (strcmp(argv[i], "mem") == 0) { in check_setup()
56 } else if (strcmp(argv[i], "smp") == 0) { in check_setup()
74 phys_addr_t highest_end = 0; in check_pabt_init()
118 "mov r0, %0\n" \
139 for (i = 0; i < ARRAY_SIZE(regs->uregs); ++i) { in check_regs()
157 test_exception("", "mcr p2, 0, r0, c0, c0", "", "r0"); in check_und()
166 u32 svc = *(u32 *)(regs->ARM_pc - 4) & 0xffffff; in svc_handler()
[all …]
H A Ddebug.c13 #define MDSCR_SS (1 << 0)
15 #define DBGBCR_LEN8 (0xff << 5)
16 #define DBGBCR_EXEC (0x0 << 3)
17 #define DBGBCR_EL1 (0x1 << 1)
18 #define DBGBCR_E (0x1 << 0)
20 #define DBGWCR_LEN8 (0xff << 5)
21 #define DBGWCR_RD (0x1 << 3)
22 #define DBGWCR_WR (0x2 << 3)
23 #define DBGWCR_EL1 (0x1 << 1)
24 #define DBGWCR_E (0x1 << 0)
[all …]
/kvm-unit-tests/s390x/snippets/asm/
H A Dpv-icpt-112.S5 * We setup and share a prefix at 0x0 and 0x8000 which the hypervisor
21 diag 0,0,0x44
31 .insn rrf,0xB9A40000,0,1,0,0
35 diag 0,0,0x44
37 /* Host: icpt: PV instruction diag 0x44 */
42 l %r2, 0(%r1)
45 /* Change the prefix to 0x8000 and re-try */
49 spx 0(%r2)
56 stg %r2, 0(%r3)
58 .insn rrf,0xB9A40000,0,2,0,0
[all …]
H A Dpv-diag-308.S3 * Diagnose 0x308 snippet used for PV IPL and reset testing
17 diag 0, 0, 0x500
21 * of SIE and therefore effectively loop forever. 0 is a valid PSW
26 * For subcode 0/1 there are no PGMs to consider.
31 /* Set up the reset psw at 0x0 */
35 stg %r5, 0
38 diag %r0, %r2, 0x308
41 diag 0, 0, 0x44
46 diag %r1, 0, 0x9c
51 .quad 0x0008000180000000
/kvm-unit-tests/x86/
H A Dpmu_pebs.c66 GP = 0,
71 0x00c4, /* PERF_COUNT_HW_BRANCH_INSTRUCTIONS */
72 0x00c5, /* PERF_COUNT_HW_BRANCH_MISSES */
73 0x0300, /* PERF_COUNT_HW_REF_CPU_CYCLES */
74 0x003c, /* PERF_COUNT_HW_CPU_CYCLES */
75 0x00c0, /* PERF_COUNT_HW_INSTRUCTIONS */
76 0x013c, /* PERF_COUNT_HW_BUS_CYCLES */
77 0x4f2e, /* PERF_COUNT_HW_CACHE_REFERENCES */
78 0x412e, /* PERF_COUNT_HW_CACHE_MISSES */
84 0,
[all …]
H A Dtsc_adjust.c13 report(rdmsr(MSR_IA32_TSC_ADJUST) == 0x0, in main()
23 t3 = 0x0; in main()
H A Dcstart.S7 ipi_vector = 0x20
21 i = 0
23 .long 0x1e7 | (i << 22)
31 mb_magic = 0x1BADB002
32 mb_flags = 0x0
35 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
49 mov $0x10, %ax
81 bts $0, %eax
H A Ds3.c8 #define RTC_ALARM_DONT_CARE 0xC0
14 #define REG_A_UIP 0x80
15 #define REG_B_AIE 0x20
19 outb(reg, 0x70); in rtc_in()
20 return inb(0x71); in rtc_in()
25 outb(reg, 0x70); in rtc_out()
26 outb(val, 0x71); in rtc_out()
35 char *addr, *resume_vec = (void*)0x1000; in main()
47 outw(0x400, fadt->pm1a_evt_blk + 2); in main()
50 while ((rtc_in(RTC_REG_A) & REG_A_UIP) == 0); in main()
[all …]
H A Dioapic.c18 set_irq_line(line, 0); in toggle_irq_line()
26 version_offset = 0x01; in ioapic_reg_version()
28 data_write = data_read ^ 0xffffffff; in ioapic_reg_version()
40 id_offset = 0x0; in ioapic_reg_id()
42 data_write = data_read ^ 0xffffffff; in ioapic_reg_id()
47 report(diff == 0x0f000000, "id register only bits [24:27] writable"); in ioapic_reg_id()
55 id_offset = 0x0; in ioapic_arbitration_id()
56 arb_offset = 0x2; in ioapic_arbitration_id()
57 write = 0x0f000000; in ioapic_arbitration_id()
63 ioapic_write_reg(arb_offset, 0x0); in ioapic_arbitration_id()
[all …]
H A Dcstart64.S5 ipi_vector = 0x20
19 i = 0
21 .quad 0x1e7 | (i << 21)
27 .quad ptl2 + 7 + 0 * 4096
42 mb_boot_info: .quad 0
51 mb_magic = 0x1BADB002
52 mb_flags = 0x0
55 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
101 .quad 0
102 .quad 0x00cf9b000000ffff // flat 32-bit code segment
[all …]
H A Dcet.c12 static unsigned long invalid_offset = 0xffffffffffffff;
19 asm volatile (".byte 0xf3, 0x48, 0x0f, 0x1e, 0xc8" : "=a"(ssp)); in cet_shstk_func()
21 asm("movq %%rbp,%0" : "=r"(ret_addr)); in cet_shstk_func()
22 printf("The return-address in shadow-stack = 0x%lx, in normal stack = 0x%lx\n", in cet_shstk_func()
27 * while function is returning. The error-code is 0x1, meaning it's in cet_shstk_func()
32 *(ret_addr + 1) = 0xdeaddead; in cet_shstk_func()
34 return 0; in cet_shstk_func()
41 * endbr64, it'll trigger #CP with error code 0x3, and the execution in cet_ibt_func()
51 return 0; in cet_ibt_func()
54 #define ENABLE_SHSTK_BIT 0x1
[all …]
/kvm-unit-tests/lib/x86/
H A Dapic-defs.h10 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
17 #define APIC_ID 0x20
19 #define APIC_LVR 0x30
20 #define APIC_LVR_MASK 0xFF00FF
21 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
22 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
24 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
28 #define APIC_XAPIC(x) ((x) >= 0x14)
29 #define APIC_TASKPRI 0x80
[all …]
/kvm-unit-tests/arm/efi/
H A Dcrt0-efi-aarch64.S31 .short 0
33 .short 0xaa64 // AArch64
35 .long 0 // TimeDateStamp
36 .long 0 // PointerToSymbolTable
37 .long 0 // NumberOfSymbols
39 .short 0x206 // Characteristics.
44 .short 0x20b // PE32+ format
45 .byte 0x02 // MajorLinkerVersion
46 .byte 0x14 // MinorLinkerVersion
49 .long 0 // SizeOfUninitializedData
[all …]
H A Delf_aarch64_efi.lds6 .text 0x0 : {
63 .comment 0 : { *(.comment) }
/kvm-unit-tests/lib/s390x/
H A Dsnippet.h40 #define SNIPPET_PV_TWEAK0 0x42UL
41 #define SNIPPET_PV_TWEAK1 0UL
42 #define SNIPPET_UNPACK_OFF 0
46 * C snippet instructions start at 0x4000 due to the prefix and the
50 #define SNIPPET_ENTRY_ADDR 0x4000
66 * @off: Offset from guest absolute 0x0 where snippet is copied to
96 * @off: Offset from guest absolute 0x0 where snippet is copied to
112 uv_unpack(vm, off, gbin_len, tweak[0]); in snippet_pv_init()
117 * - lowcore 0x0 - 0x1000 (asm) in snippet_pv_init()
118 * - stack 0x3000 (C) in snippet_pv_init()
[all …]
/kvm-unit-tests/lib/arm64/asm/
H A Dsysreg.h17 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
23 .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt)
27 .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt)
35 asm volatile("mrs %0, " xstr(r) : "=r" (__val)); \
41 asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val)); \
42 } while (0)
46 asm volatile("mrs_s %0, " xstr(r) : "=r" (__val)); \
52 asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\
53 } while (0)
62 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
[all …]
/kvm-unit-tests/lib/powerpc/asm/
H A Dhcall.h9 #define SC1 0x44000022
10 #define SC1_REPLACEMENT 0x7c000268
12 #define H_SUCCESS 0
18 #define H_SET_SPRG0 0x24
19 #define H_SET_DABR 0x28
20 #define H_PAGE_INIT 0x2c
21 #define H_REGISTER_VPA 0xDC
22 #define H_CEDE 0xE0
23 #define H_GET_TERM_CHAR 0x54
24 #define H_PUT_TERM_CHAR 0x58
[all …]
/kvm-unit-tests/x86/efi/
H A Defistart64.S16 smp_stacktop: .long 0
53 lcall $0x18, $0x0
57 .quad 0
58 .quad 0x00cf9b000000ffff // flat 32-bit code segment
59 .quad 0x00cf93000000ffff // flat 32-bit data segment
60 .quad 0 // call gate to 32-bit AP entrypoint
66 .word 0
67 .long 0
/kvm-unit-tests/lib/
H A Dpci-edu.h21 #define PCI_VENDOR_ID_QEMU 0x1234
22 #define PCI_DEVICE_ID_EDU 0x11e8
25 #define EDU_BAR 0
26 #define EDU_MAGIC 0xed
27 #define EDU_VERSION 0x100
31 #define EDU_REG_ID 0x0
32 #define EDU_REG_ALIVE 0x4
33 #define EDU_REG_FACTORIAL 0x8
34 #define EDU_REG_STATUS 0x20
35 #define EDU_REG_INTR_STATUS 0x24
[all …]
/kvm-unit-tests/s390x/
H A Dcpu.S17 * %r2 subcode (0 or 1)
29 larl %r1, 0f
32 /* Store it at the reset PSW location (real 0x0) */
33 stg %r0, 0
36 diag %r0,%r2,0x308
42 0: larl %r1, initial_cr0
43 lctlg %c0, %c0, 0(%r1)
60 larl %r14, 0f
63 0: j 0
67 .quad 0x0008000180000000
H A Dpfmf.c24 pfmf(0, pagebuf); in test_priv()
34 .reg.key = 0x30, in test_4k_key()
46 report(skey.val == 0x30, "set storage keys"); in test_4k_key()
58 .reg.key = 0x30, in test_1m_key()
69 for (i = 0; i < 256; i++) { in test_1m_key()
72 if (skey.val != 0x30) { in test_1m_key()
104 unsigned long sum = 0; in test_1m_clear()
109 for (i = 0; i < PAGE_SIZE * 256; i++) in test_1m_clear()
124 report_prefix_push("0x1000"); in test_low_addr_prot()
127 pfmf(r1.val, (void *)0x1000); in test_low_addr_prot()
[all …]
/kvm-unit-tests/s390x/snippets/
H A DMakefile24 …$(GEN_SE_HEADER) -k $(HOST_KEY_DOCUMENT) -c $<,0x0,0x00000000000000420000000000000000 --psw-addr 0…
/kvm-unit-tests/lib/arm64/
H A Dprocessor.c74 for (i = 29; i >= 0; --i) { in show_regs()
76 if (i % 2 == 0) in show_regs()
86 asm volatile("mrs %0, far_el1": "=r" (*far)); in get_far()
96 if ((esr & 0x3f /* DFSC */) != 0x10 in get_far()
97 || !(esr & 0x400 /* FnV */)) in get_far()
153 ti->exception_handlers[v][0] = (exception_fn)fn; in install_irq_handler()
181 (irq_handler_fn)ti->exception_handlers[v][0]; in default_vector_irq_handler()
189 irq_handler = (irq_handler_fn)ti->exception_handlers[v][0]; in default_vector_irq_handler()
237 memset(ti, 0, sizeof(struct thread_info)); in __thread_info_init()
256 "mov x0, %0\n" in start_usr()
[all …]
/kvm-unit-tests/riscv/
H A Dflat.lds22 * +----------------------+ <-- physical address 0x0

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