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/qemu/tests/tcg/arm/
H A Dfcvt.ref12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
44 20 SINGLE: 6.55030000000000000000e+04 / 0x477fdf00 (0 => OK)
46 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
48 22 SINGLE: 6.55050000000000000000e+04 / 0x477fe100 (0 => OK)
75 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
76 04 DOUBLE: -1.11100004769645909791e+31 / 0x00c661874b20000000 (0 => OK)
107 20 SINGLE: 6.55030000000000000000e+04 / 0x477fdf00 (0 => OK)
108 20 DOUBLE: 6.55030000000000000000e+04 / 0x0040effbe000000000 (0 => OK)
109 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
[all …]
/qemu/tests/tcg/aarch64/
H A Dfcvt.ref12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
44 20 SINGLE: 6.55030000000000000000e+04 / 0x477fdf00 (0 => OK)
46 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
48 22 SINGLE: 6.55050000000000000000e+04 / 0x477fe100 (0 => OK)
75 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
76 04 DOUBLE: -1.11100004769645909791e+31 / 0x00c661874b20000000 (0 => OK)
107 20 SINGLE: 6.55030000000000000000e+04 / 0x477fdf00 (0 => OK)
108 20 DOUBLE: 6.55030000000000000000e+04 / 0x0040effbe000000000 (0 => OK)
109 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
[all …]
/qemu/hw/nvram/
H A Dtrace-events8 fw_cfg_select(void *s, uint16_t key_value, const char *key_name, int ret) "%p key 0x%04" PRIx16 " '…
10 fw_cfg_add_bytes(uint16_t key_value, const char *key_name, size_t len) "key 0x%04" PRIx16 " '%s', %…
12 fw_cfg_add_string(uint16_t key_value, const char *key_name, const char *value) "key 0x%04" PRIx16 "…
13 fw_cfg_add_i16(uint16_t key_value, const char *key_name, uint16_t value) "key 0x%04" PRIx16 " '%s',…
14 fw_cfg_add_i32(uint16_t key_value, const char *key_name, uint32_t value) "key 0x%04" PRIx16 " '%s',…
15 fw_cfg_add_i64(uint16_t key_value, const char *key_name, uint64_t value) "key 0x%04" PRIx16 " '%s',…
18 macio_nvram_read(uint32_t addr, uint8_t val) "read addr=0x%04"PRIx32" val=0x%02x"
19 macio_nvram_write(uint32_t addr, uint8_t val) "write addr=0x%04"PRIx32" val=0x%02x"
/qemu/hw/sh4/
H A Dtrace-events2 …16_t cur, uint16_t pdtr, uint16_t pctr) "porta changed from 0x%04x to 0x%04x (pdtra=0x%04x, pctra=…
3 …16_t cur, uint16_t pdtr, uint16_t pctr) "portb changed from 0x%04x to 0x%04x (pdtrb=0x%04x, pctrb=…
/qemu/tests/tcg/i386/
H A Dtest-i386-shift.h40 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", in exec_opq()
54 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", in exec_opl()
67 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", in exec_opw()
91 printf("%-10s A=" FMTLX " B=" FMTLX " C=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", in exec_opq()
105 printf("%-10s A=" FMTLX " B=" FMTLX " C=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", in exec_opl()
118 printf("%-10s A=" FMTLX " B=" FMTLX " C=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", in exec_opw()
134 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", in exec_opb()
H A Dtest-i386-muldiv.h16 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n", in glue()
34 printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n", in glue()
52 printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n", in glue()
71 printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n", in glue()
H A Dtest-i386.h16 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", \
27 printf("%-10s A=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", \
/qemu/hw/net/
H A Dtrace-events14 lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
15 lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
20 lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
21 lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
37 open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x"
38 open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x"
47 open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x"
48 open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x"
348 …write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII write addr 0x%x reg 0x%02x val 0x%04x"
349 …i_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII read addr 0x%x reg 0x%02x val 0x%04x"
[all …]
H A Dnpcm_pcs.c155 "%s: SR_CTL read offset 0x%04" HWADDR_PRIx in npcm_pcs_read_sr_ctl()
170 "%s: SR_MII read offset 0x%04" HWADDR_PRIx in npcm_pcs_read_sr_mii()
185 "%s: SR_TIM read offset 0x%04" HWADDR_PRIx in npcm_pcs_read_sr_tim()
200 "%s: VR_MII read offset 0x%04" HWADDR_PRIx in npcm_pcs_read_vr_mii()
215 "%s: SR_CTL write offset 0x%04" HWADDR_PRIx in npcm_pcs_write_sr_ctl()
230 "%s: SR_MII write offset 0x%04" HWADDR_PRIx in npcm_pcs_write_sr_mii()
250 "%s: SR_TIM write offset 0x%04" HWADDR_PRIx in npcm_pcs_write_sr_tim()
265 "%s: VR_MII write offset 0x%04" HWADDR_PRIx in npcm_pcs_write_vr_mii()
H A Drtl8139.c37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
244 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
533 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", in prom9346_decode_command()
616 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", in prom9346_shift_clock()
626 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", in prom9346_shift_clock()
645 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); in prom9346_shift_clock()
711 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, in rtl8139_update_irq()
1140 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " in rtl8139_do_receive()
1141 "read 0x%04x === available 0x%04x need 0x%04zx\n", in rtl8139_do_receive()
[all …]
/qemu/hw/pci/
H A Dpci-hmp-cmds.c39 monitor_printf(mon, "Class %04" PRId64, dev->class_info->q_class); in hmp_info_pci_device()
42 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n", in hmp_info_pci_device()
45 monitor_printf(mon, " PCI subsystem %04" PRIx64 ":%04" PRIx64 "\n", in hmp_info_pci_device()
62 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", in hmp_info_pci_device()
87 monitor_printf(mon, "I/O at 0x%04" PRIx64 in hmp_info_pci_device()
88 " [0x%04" PRIx64 "]\n", in hmp_info_pci_device()
149 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); in pcibus_dev_print()
153 "pci id %04x:%04x (sub %04x:%04x)\n", in pcibus_dev_print()
H A Dtrace-events9 …t bad_rom_magic, uint16_t good_rom_magic) "Bad ROM magic number: %04"PRIX16". Should be: %04"PRIX16
11 … rom_vendor_id, uint16_t rom_device_id) "%s: ROM ID %04"PRIx16":%04"PRIx16" | PCI ID %04"PRIx16":%…
/qemu/hw/usb/
H A Dtrace-events81 usb_ehci_opreg_read(uint32_t addr, const char *str, uint32_t val) "rd mmio 0x%04x [%s] = 0x%x"
82 usb_ehci_opreg_write(uint32_t addr, const char *str, uint32_t val) "wr mmio 0x%04x [%s] = 0x%x"
83 usb_ehci_opreg_change(uint32_t addr, const char *str, uint32_t new, uint32_t old) "ch mmio 0x%04x […
84 usb_ehci_portsc_read(uint32_t addr, uint32_t port, uint32_t val) "rd mmio 0x%04x [port %d] = 0x%x"
85 usb_ehci_portsc_write(uint32_t addr, uint32_t port, uint32_t val) "wr mmio 0x%04x [port %d] = 0x%x"
86 usb_ehci_portsc_change(uint32_t addr, uint32_t port, uint32_t new, uint32_t old) "ch mmio 0x%04x [p…
105 …evel, uint32_t frindex, uint32_t sts, uint32_t mask) "level %d, frindex 0x%04x, sts 0x%x, mask 0x%…
120 usb_uhci_mmio_readw(uint32_t addr, uint32_t val) "addr 0x%04x, ret 0x%04x"
121 usb_uhci_mmio_writew(uint32_t addr, uint32_t val) "addr 0x%04x, val 0x%04x"
146 usb_xhci_cap_read(uint32_t off, uint32_t val) "off 0x%04x, ret 0x%08x"
[all …]
/qemu/hw/block/
H A Dtrace-events14 …int64_t offset, unsigned size, uint32_t value) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x"
15 …int64_t offset, unsigned size, uint32_t value) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x"
16 … size, uint32_t value, uint64_t counter) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x count…
17 pflash_device_id(const char *name, uint16_t id) "%s: read device ID: 0x%04x"
18 pflash_device_info(const char *name, uint64_t offset) "%s: read device information offset:0x%04" PR…
21 …uint32_t value, uint8_t cmd, uint8_t wcycle) "%s: offset:0x%04" PRIx64 " size:%u value:0x%04x cmd:…
22 …ned int size, uint32_t value, uint8_t wcycle) "%s: offset:0x%04"PRIx64" size:%u value:0x%04x wcycl…
23 pflash_manufacturer_id(const char *name, uint16_t id) "%s: read manufacturer ID: 0x%04x"
32 …ame, uint64_t offset, uint8_t cmd, uint16_t addr0) "%s: unlock0 failed 0x%" PRIx64 " 0x%02x 0x%04x"
/qemu/hw/riscv/
H A Dtrace-events4 riscv_iommu_new(const char *id, unsigned b, unsigned d, unsigned f) "%s: device attached %04x:%02x.…
5 …ned b, unsigned d, unsigned f, uint64_t reason, uint64_t iova) "%s: fault %04x:%02x.%u reason: 0x%…
6 …*id, unsigned b, unsigned d, unsigned f, uint64_t iova) "%s: page request %04x:%02x.%u iova: 0x%"P…
7 …gned pasid, const char *dir, uint64_t iova, uint64_t phys) "%s: translate %04x:%02x.%u #%u %s 0x%"…
8 …d b, unsigned d, unsigned f, uint64_t iova, uint64_t phys) "%s: translate %04x:%02x.%u MSI 0x%"PRI…
15 …unsigned b, unsigned d, unsigned f, uint64_t iova) "%s: translate request %04x:%02x.%u iova: 0x%"P…
/qemu/hw/adc/
H A Dtrace-events4 …d(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
5 …te(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
/qemu/hw/s390x/
H A Dtrace-events8 …n, uint8_t cssid, uint8_t ssid, uint16_t schid, uint16_t devno) "CSS: %s %x.%x.%04x (devno 0x%04x)"
9 …m, uint8_t isc, const char *conditional) "CSS: I/O interrupt on sch %x.%x.%04x (intparm 0x%08x, is…
14 virtio_ccw_interpret_ccw(int cssid, int ssid, int schid, int cmd_code) "VIRTIO-CCW: %x.%x.%04x: int…
15 …chid, int devno, const char *devno_mode) "VIRTIO-CCW: add subchannel %x.%x.%04x, devno 0x%04x (%s)"
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc70 "03:04:84:b2","03:04:84:a7",0,0,0,0)
72 "03:04:94:b2","03:04:94:a7",0,0,0,0)
74 "03:04:a4:b2","03:04:a4:a7",0,0,0,0)
76 "03:04:b4:b2","03:04:b4:a7",0,0,0,0)
78 "03:04:c4:b2","03:04:c4:a7",0,0,0,0)
80 "03:04:d4:b2","03:04:d4:a7",0,0,0,0)
82 "03:04:e4:b2","03:04:e4:a7",0,0,0,0)
84 "03:04:f4:b2","03:04:f4:a7",0,0,0,0)
86 "03:04:04:c3","03:04:04:c1",0,0,0,0)
88 "03:04:14:c3","03:04:44:c1",0,0,0,0)
[all …]
/qemu/.gitlab-ci.d/custom-runners/
H A Dubuntu-22.04-aarch64.yml10 - ubuntu_22.04
31 - ubuntu_22.04
53 - ubuntu_22.04
75 - ubuntu_22.04
94 - ubuntu_22.04
115 - ubuntu_22.04
136 - ubuntu_22.04
H A Dubuntu-22.04-s390x.yml10 - ubuntu_22.04
29 - ubuntu_22.04
48 - ubuntu_22.04
71 - ubuntu_22.04
92 - ubuntu_22.04
113 - ubuntu_22.04
/qemu/hw/rtc/
H A Dtrace-events30 m48txx_nvram_io_read(uint64_t addr, uint64_t value) "io read addr:0x%04" PRIx64 " value:0x%02" PRIx…
31 m48txx_nvram_io_write(uint64_t addr, uint64_t value) "io write addr:0x%04" PRIx64 " value:0x%02" PR…
32 m48txx_nvram_mem_read(uint32_t addr, uint32_t value) "mem read addr:0x%04x value:0x%02x"
33 m48txx_nvram_mem_write(uint32_t addr, uint32_t value) "mem write addr:0x%04x value:0x%02x"
/qemu/target/s390x/
H A Dtrace-events5 ioinst_sch_id(const char *insn, int cssid, int ssid, int schid) "IOINST: %s (%x.%x.%04x)"
7 ioinst_chsc_cmd(uint16_t cmd, uint16_t len) "IOINST: chsc command 0x%04x, len 0x%04x"
/qemu/hw/i2c/
H A Dtrace-events20 smbus_ioport_readb(uint16_t addr, uint8_t data) "[0x%04" PRIx16 "] -> val=0x%02x"
21 smbus_ioport_writeb(uint16_t addr, uint8_t data) "[0x%04" PRIx16 "] <- val=0x%02x"
45 …t char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%…
46 …t char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%…
/qemu/hw/misc/
H A Dtrace-events70 …signed width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"P…
90 slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x"
91 slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x"
134 npcm_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
135 npcm_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
138 npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64
139 npcm_gcr_write(uint64_t offset, uint64_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx64
142 …onst char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
143 …onst char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
150 npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x…
[all …]
H A Dallwinner-a10-dramc.c68 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", in allwinner_a10_dramc_read()
72 qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n", in allwinner_a10_dramc_read()
102 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", in allwinner_a10_dramc_write()
106 qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", in allwinner_a10_dramc_write()

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