| /linux-5.10/sound/drivers/ ! |
| D | serial-u16550.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Added support for the Midiator MS-124T and for the MS-124W in
17 * More documentation can be found in serial-u16550.txt.
40 #define SNDRV_SERIAL_MS124T 1 /* Midiator MS-124T */
41 #define SNDRV_SERIAL_MS124W_SA 2 /* Midiator MS-124W in S/A mode */
42 #define SNDRV_SERIAL_MS124W_MB 3 /* Midiator MS-124W in M/B mode */
47 "MS-124T",
48 "MS-124W S/A",
49 "MS-124W M/B",
54 #define SNDRV_SERIAL_DROPBUFF 1 /* Non-blocking discard operation */
[all …]
|
| /linux-5.10/Documentation/devicetree/bindings/serial/ ! |
| D | fsl-imx-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <fabio.estevam@nxp.com>
13 - $ref: "serial.yaml"
14 - $ref: "rs485.yaml"
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
[all …]
|
| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
[all …]
|
| D | mtk-uart.txt | 1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible should contain:
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
[all …]
|
| D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
[all …]
|
| D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
14 - if:
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
21 - if:
24 const: mrvl,mmp-uart
[all …]
|
| D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
[all …]
|
| D | samsung_uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P and Exynos SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - samsung,s3c2410-uart
[all …]
|
| D | amlogic,meson-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson SoC UART Serial Interface
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
15 of SoCs, and can be present either in the "Always-On" power domain or the
16 "Everything-Else" power domain.
18 The particularity of the "Always-On" Serial Interface is that the hardware
[all …]
|
| D | omap_serial.txt | 1 OMAP UART controller
4 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
5 - compatible : should be "ti,am654-uart" for AM654 controllers
6 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
7 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
8 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
9 - compatible : should be "ti,am4372-uart" for AM437x controllers
10 - compatible : should be "ti,am3352-uart" for AM335x controllers
11 - compatible : should be "ti,dra742-uart" for DRA7x controllers
12 - reg : address and length of the register space
[all …]
|
| D | sprd-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/serial/sprd-uart.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Spreadtrum serial UART
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - items:
19 - enum:
[all …]
|
| /linux-5.10/drivers/tty/serial/ ! |
| D | men_z135_uart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MEN 16z135 High Speed UART
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
145 reg = ioread32(port->membase + addr); in men_z135_reg_set()
[all …]
|
| D | timbuart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
[all …]
|
| D | arc_uart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARC On-Chip(fpga) UART Driver
5 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Decoupled the driver from arch/arc
10 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
13 * -Is uart_tx_stopped() not done in tty write path as it has already been
17 * -New Serial Core based ARC UART driver
18 * -Derived largely from blackfin driver albiet with some major tweaks
21 * -check if sysreq works
37 * ARC UART Hardware Specs
[all …]
|
| /linux-5.10/drivers/tty/serial/8250/ ! |
| D | 8250_tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
30 status = p->serial_in(p, UART_LSR); in tegra_uart_handle_break()
32 status = p->serial_in(p, UART_RX); in tegra_uart_handle_break()
35 if (--tmout == 0) in tegra_uart_handle_break()
44 struct tegra_uart *uart; in tegra_uart_probe() local
49 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
50 if (!uart) in tegra_uart_probe()
51 return -ENOMEM; in tegra_uart_probe()
56 spin_lock_init(&port->lock); in tegra_uart_probe()
58 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | in tegra_uart_probe()
[all …]
|
| D | 8250_core.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
9 * Supports: ISA-compatible 8250/16550 ports
12 * userspace-configurable "phantom" ports
47 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
48 * is unsafe when used on edge-triggered interrupts.
62 * SERIAL_PORT_DFNS tells us about built-in ports that have no
103 * line has been de-asserted.
116 spin_lock(&i->lock); in serial8250_interrupt()
118 l = i->head; in serial8250_interrupt()
[all …]
|
| D | 8250_lpc18xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Serial port driver for NXP LPC18xx/43xx UART
43 if (rs485->flags & SER_RS485_ENABLED) in lpc18xx_rs485_config()
44 memset(rs485->padding, 0, sizeof(rs485->padding)); in lpc18xx_rs485_config()
48 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | in lpc18xx_rs485_config()
51 if (rs485->flags & SER_RS485_ENABLED) { in lpc18xx_rs485_config()
55 if (rs485->flags & SER_RS485_RTS_ON_SEND) { in lpc18xx_rs485_config()
57 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpc18xx_rs485_config()
59 rs485->flags |= SER_RS485_RTS_AFTER_SEND; in lpc18xx_rs485_config()
63 if (rs485->delay_rts_after_send) { in lpc18xx_rs485_config()
[all …]
|
| D | 8250_ingenic.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
47 return readl(port->membase + (offset << 2)); in early_in()
52 writel(value, port->membase + (offset << 2)); in early_out()
69 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
87 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
93 struct uart_port *port = &dev->port; in ingenic_early_console_setup()
97 if (!dev->port.membase) in ingenic_early_console_setup()
[all …]
|
| D | 8250_pxa.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
38 serial8250_suspend_port(data->line); in serial_pxa_suspend()
47 serial8250_resume_port(data->line); in serial_pxa_resume()
57 { .compatible = "mrvl,pxa-uart", },
58 { .compatible = "mrvl,mmp-uart", },
63 /* Uart divisor latch write */
83 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
86 clk_prepare_enable(data->clk); in serial_pxa_pm()
88 clk_disable_unprepare(data->clk); in serial_pxa_pm()
[all …]
|
| D | 8250_hp300.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * by Kars de Jong <jongk@linux-m68k.org>, May 2004.
63 /* Offset to UART registers from base of DCA */
78 * Where we find the 8250-like APCI ports, and how far apart they are.
139 /* Enable board-interrupts */ in hp300_setup_serial_console()
160 struct uart_8250_port uart; in hpdca_init_one() local
164 if (hp300_uart_scode == d->scode) { in hpdca_init_one()
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
[all …]
|
| /linux-5.10/arch/mips/kernel/ ! |
| D | cps-vec-ns16550.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
46 * @a0: pointer to NULL-terminated ASCII string
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
[all …]
|
| /linux-5.10/arch/arm/include/debug/ ! |
| D | tegra.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
12 * Portions based on mach-omap2's debug-macro.S
13 * Copyright (C) 1994-1999 Russell King
40 * Must be section-aligned since a section mapping is used early on.
41 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
[all …]
|
| /linux-5.10/include/uapi/linux/ ! |
| D | serial_core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
32 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
33 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
36 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
37 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
41 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
[all …]
|
| /linux-5.10/arch/arm/ ! |
| D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0
44 once the kernel has booted up - it's a one time check.
96 1 - undefined instruction events
97 2 - system calls
98 4 - invalid data aborts
99 8 - SIGSEGV faults
100 16 - SIGBUS faults
104 bool "Kernel low-level debugging functions (read help!)"
112 UART definition, as specified below. Attempting to boot the kernel
117 prompt "Kernel low-level debugging port"
[all …]
|
| /linux-5.10/drivers/firmware/ ! |
| D | pcdp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) Copyright 2002, 2003, 2004 Hewlett-Packard Development Company, L.P.
20 setup_serial_console(struct pcdp_uart *uart) in setup_serial_console() argument
27 mmio = (uart->addr.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY); in setup_serial_console()
29 mmio ? "mmio" : "io", uart->addr.address); in setup_serial_console()
30 if (uart->baud) { in setup_serial_console()
31 p += sprintf(p, ",%llu", uart->baud); in setup_serial_console()
32 if (uart->bits) { in setup_serial_console()
33 switch (uart->parity) { in setup_serial_console()
38 p += sprintf(p, "%c%d", parity, uart->bits); in setup_serial_console()
[all …]
|