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/linux-6.8/arch/m68k/math-emu/
Dfp_util.S23 * the restrictions contained in a BSD-style copyright.)
49 * something here. %d0 and %d1 is always usable, sometimes %d2 (or
63 tst.l (TASK_MM-8,%a2)
65 tst.l (TASK_MM-4,%a2)
69 1: printf ,"oops:%p,%p,%p\n",3,%a2@(TASK_MM-8),%a2@(TASK_MM-4),%a2@(TASK_MM)
94 | args: %d0 = source (32-bit long)
98 printf PCONV,"l2e: %p -> %p(",2,%d0,%a0
125 | args: %d0 = source (single-precision fp value)
129 printf PCONV,"s2e: %p -> %p(",2,%d0,%a0
139 add.w #0x3fff-0x7f,%d1 | re-bias the exponent.
[all …]
Dfp_movem.S23 * the restrictions contained in a BSD-style copyright.)
52 btst #11,%d2
54 bfextu %d2{#24,#8},%d0 | static register list
56 1: bfextu %d2{#25,#3},%d0 | dynamic register list
67 btst #12,%d2
69 printf PDECODE,"-" | decremental move
72 2: btst #13,%d2
74 printf PDECODE,"->" | fpu -> cpu
76 1: printf PDECODE,"<-" | fpu <- cpu
135 btst #12,%d2
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Dfp_decode.h23 * the restrictions contained in a BSD-style copyright.)
46 * d0 - will contain source operand for data direct mode,
48 * d1 - upper 16bit are reserved for caller
51 * d2 - contains first two instruction words,
53 * a0 - will point to source/dest operand for any indirect mode
55 * a1 - scratch register
56 * a2 - base addr to the task structure
73 bfextu %d2{#8,#2},%d0
85 bfextu %d2{#16,#3},%d0
99 bfextu %d2{#19,#3},%d0
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Dfp_move.S23 * the restrictions contained in a BSD-style copyright.)
82 lea (-8,%a1),%a0
84 move.l %d1,%d2
99 swap %d2
100 move.w %d2,%d0
103 move.w %d2,%d1
111 swap %d2
112 move.w %d2,%d0
115 move.l %d2,%d1
122 swap %d2
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/linux-6.8/arch/m68k/lib/
Dudivsi3.S1 /* libgcc1 routines for 68000 w/o floating-point hardware.
33 D. V. Henkel-Wallace (gumby@cygnus.com) Fete Bastille, 1992
69 #define d2 REG (d2) macro
90 movel d2, sp@-
96 movel d0, d2
97 clrw d2
98 swap d2
99 divu d1, d2 /* high quotient in lower word */
100 movew d2, d0 /* save high quotient */
102 movew sp@(10), d2 /* get low dividend + high rest */
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Ddivsi3.S1 /* libgcc1 routines for 68000 w/o floating-point hardware.
33 D. V. Henkel-Wallace (gumby@cygnus.com) Fete Bastille, 1992
71 #define d2 REG (d2) macro
91 movel d2, sp@-
93 moveq IMM (1), d2 /* sign of result stored in d2 (=1 or =-1) */
98 negb d2 /* change sign because divisor <0 */
100 negl d2 /* change sign because divisor <0 */
106 negb d2
108 negl d2
111 L2: movel d1, sp@-
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/linux-6.8/drivers/block/
Dswim_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * low-level functions for the SWIM floppy controller
13 * 2004-08-21 (lv) - Initial implementation
14 * 2008-11-05 (lv) - add get_swim_mode
48 moveml %d1-%d5/%a0-%a4,%sp@-
51 moveml %sp@+, %d1-%d5/%a0-%a4
64 moveq #-1, %d0
65 movew #seek_time, %d2
68 tstb %a3@(read_error - read_mark)
69 moveb #0x18, %a3@(write_mode0 - read_mark)
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/linux-6.8/drivers/net/wan/
Dwanxlfw.S1 /* SPDX-License-Identifier: GPL-2.0-only */
14 0x000 - 0x050 TX#0 0x050 - 0x140 RX#0
15 0x140 - 0x190 TX#1 0x190 - 0x280 RX#1
16 0x280 - 0x2D0 TX#2 0x2D0 - 0x3C0 RX#2
17 0x3C0 - 0x410 TX#3 0x410 - 0x500 RX#3
20 000 5FF 1536 Bytes Dual-Port RAM User Data / BDs
21 600 6FF 256 Bytes Dual-Port RAM User Data / BDs
22 700 7FF 256 Bytes Dual-Port RAM User Data / BDs
23 C00 CBF 192 Bytes Dual-Port RAM Parameter RAM Page 1
24 D00 DBF 192 Bytes Dual-Port RAM Parameter RAM Page 2
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/linux-6.8/arch/m68k/fpsp040/
Dround.S21 | round --- round result according to precision/mode
36 | a0 is preserved and the g-r-s bits in d0 are cleared.
37 | The result is not typed - the tag field is invalid. The
41 | inexact (i.e. if any of the g-r-s bits were set).
51 | ;the appropriate g-r-s bits.
117 asll #1,%d0 |shift g-bit to c-bit
124 | ext_grs --- extract guard, round and sticky bits
144 moveml %d2/%d3,-(%a7) |make some temp registers
148 bfextu LOCAL_HI(%a0){#24:#2},%d3 |sgl prec. g-r are 2 bits right
149 movel #30,%d2 |of the sgl prec. limits
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Dbinstr.S5 | Description: Converts a 64-bit binary integer to bcd.
7 | Input: 64-bit binary integer in d2:d3, desired length (LEN) in
12 | Output: LEN bcd digits representing the 64-bit integer.
15 | The 64-bit binary is assumed to have a decimal point before
26 | Copy the fraction in d2:d3 to d4:d5.
28 | A3. Multiply the fraction in d2:d3 by 8 using bit-field
29 | extracts and shifts. The three msbs from d2 will go into
35 | A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5
36 | into d2:d3. D1 will contain the bcd digit formed.
38 | A6. Test d7. If zero, the digit formed is the ms digit. If non-
[all …]
Dsrem_mod.S9 | -----
10 | Double-extended value Y is pointed to by address in register
11 | A0. Double-extended value X is located in -12(A0). The values
17 | ------
21 | ---------
28 | Step 2. Set L := expo(X)-expo(Y), k := 0, Q := 0.
32 | R := 2^(-L)X, j := L.
37 | 3.2 If R > Y, then { R := R - Y, Q := Q + 1}
39 | 3.4 k := k + 1, j := j - 1, Q := 2Q, R := 2R. Go to
42 | Step 4. At this point, R = X - QY = MOD(X,Y). Set
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Ddecbin.S5 | register A6 to extended-precision value in FP0.
9 | Output: Exact floating-point representation of the packed bcd value.
11 | Saves and Modifies: D2-D5
20 | Expected is a normal bcd (i.e. non-exceptional; all inf, zero,
33 | assumed following the least-significant digit.
43 | SM = 0 a non-zero digit in the integer position
44 | SM = 1 a non-zero digit in Mant0, lsd of the fraction
47 | representation (ex. 0.1E2, 1E1, 10E0, 100E-1), is converted
121 moveml %d2-%d5,-(%a7)
135 | (*) d2: digit count
[all …]
Dscale.S12 | Input: Double-extended destination operand in FPTEMP,
13 | double-extended source operand in ETEMP.
170 movel %d2,-(%a7) |free d2 for norm
172 movel FPTEMP_LO(%a6),%d2
177 roxrl #1,%d2 |mantissa to the right
188 | Test for zero. If zero, simply use fmove to return +/- zero
198 movel %d2,FPTEMP_LO(%a6)
199 movel (%a7)+,%d2
301 moveml %d2/%d3,-(%a7)
303 movel FPTEMP_HI(%a6),%d2
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/linux-6.8/arch/m68k/ifpsp060/src/
Ditest.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
30 set SREGS, -64
31 set IREGS, -128
32 set SCCR, -130
33 set ICCR, -132
34 set TESTCTR, -136
35 set EAMEM, -140
36 set EASTORE, -144
37 set DATA, -160
[all …]
Dilsp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
63 # _060LSP__idivu64_(): Emulate 64-bit unsigned div instruction. #
64 # _060LSP__idivs64_(): Emulate 64-bit signed div instruction. #
68 # 64-bit divide instruction. #
85 # sign info for later. Separate out special cases like divide-by-zero #
86 # or 32-bit divides if possible. Else, use a special math algorithm #
90 # zero, then perform a divide-by-zero using a 16-bit implemented #
96 set POSNEG, -1
97 set NDIVISOR, -2
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/linux-6.8/arch/s390/crypto/
Dchacha-s390.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Original implementation written by Andy Polyakov, @dot-asm.
6 * Copyright (C) 2006-2019 CRYPTOGAMS by <appro@openssl.org>. All Rights Reserved.
10 #include <asm/nospec-insn.h>
11 #include <asm/vx-insn.h>
20 .long 0x61707865,0x3320646e,0x79622d32,0x6b206574 # endian-neutral
304 aghi LEN,-0x40
330 aghi LEN,-0x40
357 aghi LEN,-0x40
453 #define D2 %v11 macro
[all …]
/linux-6.8/include/asm-generic/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-generic/xor.h
5 * Generic optimized RAID-5 checksumming functions.
27 } while (--lines > 0); in xor_8regs_2()
49 } while (--lines > 0); in xor_8regs_3()
73 } while (--lines > 0); in xor_8regs_4()
99 } while (--lines > 0); in xor_8regs_5()
109 register long d0, d1, d2, d3, d4, d5, d6, d7; in xor_32regs_2() local
112 d2 = p1[2]; in xor_32regs_2()
120 d2 ^= p2[2]; in xor_32regs_2()
[all …]
/linux-6.8/arch/mips/crypto/
Dpoly1305-mips.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, originally for the OpenSSL
16 # R1x000 ~5.5/+130% (big-endian)
17 # Octeon II 2.50/+70% (little-endian)
21 # Add 32-bit code path.
25 # Modulo-scheduling reduction allows to omit dependency chain at the
30 # R1x000 ~9.8/? (big-endian)
31 # Octeon II 3.65/+140% (little-endian)
32 # MT7621/1004K 4.75/? (little-endian)
48 # - never ever touch $tp, "thread pointer", former $gp [o32 can be
[all …]
/linux-6.8/arch/x86/crypto/
Dpoly1305-x86_64-cryptogams.pl2 # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
4 # Copyright (C) 2017-2018 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
5 # Copyright (C) 2017-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
6 # Copyright (C) 2006-2017 CRYPTOGAMS by <appro@openssl.org>. All Rights Reserved.
35 # Skylake-X system performance. Since we are likely to suppress
36 # AVX512F capability flag [at least on Skylake-X], conversion serves
43 # IALU/gcc-4.8(*) AVX(**) AVX2 AVX-512
44 # P4 4.46/+120% -
45 # Core 2 2.41/+90% -
46 # Westmere 1.88/+120% -
[all …]
/linux-6.8/lib/842/
D842_decompress.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 { D4, D2, I2, N0 },
24 { D4, I2, D2, N0 },
27 { D2, I2, D4, N0 },
28 { D2, I2, D2, I2 },
29 { D2, I2, I2, D2 },
30 { D2, I2, I2, I2 },
31 { D2, I2, I4, N0 },
32 { I2, D2, D4, N0 },
34 { I2, D2, I2, D2 },
[all …]
/linux-6.8/arch/arm/crypto/
Dpoly1305-armv4.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
9 # IALU(*)/gcc-4.4 NEON
11 # ARM11xx(ARMv6) 7.78/+100% -
12 # Cortex-A5 6.35/+130% 3.00
13 # Cortex-A8 6.25/+115% 2.36
14 # Cortex-A9 5.10/+95% 2.55
15 # Cortex-A15 3.85/+85% 1.25(**)
18 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
19 # (**) these are trade-off results, they can be improved by ~8% but at
[all …]
Dcurve25519-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
13 .arch armv7-a
18 push {r4-r11, lr}
31 vst1.8 {d2-d3}, [r6, : 128]!
32 vst1.8 {d0-d1}, [r6, : 128]!
33 vst1.8 {d4-d5}, [r6, : 128]
36 vst1.8 {d4-d5}, [r6, : 128]!
37 vst1.8 {d4-d5}, [r6, : 128]!
46 vld1.8 {d4-d5}, [r1]!
[all …]
/linux-6.8/arch/arm64/crypto/
Dpoly1305-armv8.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
15 # IALU/gcc-4.9 NEON
18 # Cortex-A53 2.69/+58% 1.47
19 # Cortex-A57 2.70/+7% 1.14
21 # X-Gene 2.13/+68% 2.27
35 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
36 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
37 die "can't locate arm-xlate.pl";
47 my ($h0,$h1,$h2,$r0,$r1,$s1,$t0,$t1,$d0,$d1,$d2) = map("x$_",(4..14));
[all …]
/linux-6.8/drivers/iio/adc/
Dtwl6030-gpadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2013 Texas Instruments Inc.
13 * Based on twl4030-madc.c
74 * struct twl6030_chnl_calib - channel calibration
86 * struct twl6030_ideal_code - GPADC calibration parameters
107 * struct twl6030_gpadc_platform_data - platform specific data
126 * struct twl6030_gpadc_data - GPADC data
323 [11] = { /* ch 11, internal, VBUS DC-DC output current */
387 complete(&gpadc->irq_complete); in twl6030_gpadc_irq_handler()
440 const struct twl6030_ideal_code *ideal = pdata->ideal; in twl6030_channel_calibrated()
[all …]
/linux-6.8/arch/x86/lib/
Dstring_32.c1 // SPDX-License-Identifier: GPL-2.0
3 * Most of the string-functions are rather heavily hand-optimized,
7 * used through-out, making for "slightly" unclear code :-)
21 int d0, d1, d2; in strcpy() local
26 : "=&S" (d0), "=&D" (d1), "=&a" (d2) in strcpy()
36 int d0, d1, d2, d3; in strncpy() local
46 : "=&S" (d0), "=&D" (d1), "=&c" (d2), "=&a" (d3) in strncpy()
56 int d0, d1, d2, d3; in strcat() local
64 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) in strcat()
74 int d0, d1, d2, d3; in strncat() local
[all …]

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