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/linux-6.8/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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Dthead,c900-aclint-mtimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo CLINT Timer
10 - Inochi Amaoto <inochiama@outlook.com>
15 - enum:
16 - sophgo,sg2042-aclint-mtimer
17 - const: thead,c900-aclint-mtimer
21 - description: MTIMECMP Registers
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/linux-6.8/drivers/clocksource/
Dtimer-clint.c1 // SPDX-License-Identifier: GPL-2.0
5 * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
6 * CLINT MMIO timer device.
9 #define pr_fmt(fmt) "clint: " fmt
18 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <asm/clint.h>
35 /* CLINT manages IPI and Timer for RISC-V M-mode */
133 ce->cpumask = cpumask_of(cpu); in clint_timer_starting_cpu()
149 * via generic IPI-Mux in clint_timer_dying_cpu()
159 evdev->event_handler(evdev); in clint_timer_interrupt()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_TIMER_OF) += timer-of.o
3 obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
4 obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
5 obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
6 obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o
7 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
8 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
9 obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
10 obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
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/linux-6.8/arch/riscv/boot/dts/sophgo/
Dcv1800b.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
16 &clint {
17 compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
Dcv1812h.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
19 compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
22 &clint {
23 compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
Dcv18xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <25000000>;
22 d-cache-block-size = <64>;
23 d-cache-sets = <512>;
24 d-cache-size = <65536>;
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/linux-6.8/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux-6.8/arch/riscv/include/asm/
Dclint.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * This lives in the CLINT driver, but is accessed directly by timex.h to avoid
17 * The ISA defines mtime as a 64-bit memory-mapped register that increments at
21 * like "riscv_mtime", to signify that these non-ISA assumptions must hold.
Dtimex.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/clint.h>
/linux-6.8/Documentation/devicetree/bindings/interrupt-controller/
Dthead,c900-aclint-mswi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
10 - Inochi Amaoto <inochiama@outlook.com>
15 - enum:
16 - sophgo,sg2042-aclint-mswi
17 - const: thead,c900-aclint-mswi
22 interrupts-extended:
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/linux-6.8/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
27 i-cache-block-size = <64>;
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/linux-6.8/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux-6.8/drivers/irqchip/
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
25 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
34 * On RISC-V systems local interrupts are masked or unmasked by writing
42 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
47 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
53 * The RISC-V INTC driver uses handle_percpu_devid_irq() flow in riscv_intc_irq_eoi()
54 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
55 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
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/linux-6.8/arch/riscv/boot/dts/canaan/
Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
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