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/qemu/docs/devel/migration/
H A Duadk-compression.rst4 UADK is a general-purpose user space accelerator framework that uses shared
8 UADK includes Unified/User-space-access-intended Accelerator Framework (UACCE),
24 different character devices with UACCE by using kernel-mode drivers of the
25 vendors. A user can access the hardware accelerators by performing user-mode
30 +----------------------------------+
32 +----+------------------------+----+
35 +-------+--------+ +-------+-------+
37 +-------+--------+ +-------+-------+
41 | +--------+------+
43 | +-+-------------+
[all …]
H A Dqatzip-compression.rst21 |-----------|--------|---------|----------|----------|------|------|
24 |-----------|--------|---------|----------|----------|------|------|
26 |-----------|--------|---------|----------|----------|------|------|
28 |-----------|--------|---------|----------|----------|------|------|
30 |-----------|--------|---------|----------|----------|------|------|
41 <https://github.com/intel/QATzip?tab=readme-ov-file#introductionl>`_
45 +----------------+
47 +-------+--------+
50 +-------+--------+
52 +-------+--------+
[all …]
/qemu/target/hexagon/imported/
H A Dencode_pp.def2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
26 DEF_CLASS32("---- ---- -------- PP------ --------",ALL_PP)
27 DEF_FIELD32("---- ---- -------- !!------ --------",Parse,"Packet/Loop parse bits")
28 DEF_FIELD32("!!!! ---- -------- PP------ --------",ICLASS,"Instruction Class")
57 DEF_CLASS32(ICLASS_EXTENDER" ---- -------- PP------ --------",EXTENDER)
70 DEF_CLASS32(ICLASS_V2LDST" ---- -------- PP------ --------",V2LDST)
71 DEF_CLASS32(ICLASS_V2LDST" ---1 -------- PP------ --------",V2LD)
72 DEF_CLASS32(ICLASS_V2LDST" ---0 -------- PP------ --------",V2ST)
73 DEF_CLASS32(ICLASS_V2LDST" 0--1 -------- PP------ --------",PLD)
74 DEF_CLASS32(ICLASS_V2LDST" 0--0 -------- PP------ --------",PST)
[all …]
/qemu/docs/system/ppc/
H A Dpseries.rst5 The Power machine para-virtualized environment described by the Linux on Power
18 - POWER7, POWER7+
19 - POWER8, POWER8NVL
20 - POWER9
21 - Power10
22 - Power11
23 - Support for POWER5+ also exists, works with correct kernel/userspace
25 - XICS (POWER8)
26 - XIVE (Supported by below:)
27 - POWER9
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/qemu/docs/system/i386/
H A Damd-memory-encryption.rst6 SEV is an extension to the AMD-V architecture which supports running encrypted
15 AMD secure processor (AMD-SP), which is present in AMD SOCs. Firmware running
16 inside the AMD-SP provides commands to support a common VM lifecycle. This
21 Secure Encrypted Virtualization - Encrypted State (SEV-ES) builds on the SEV
28 Launching (SEV and SEV-ES)
29 --------------------------
38 For a SEV-ES guest, the ``LAUNCH_UPDATE_VMSA`` command is also used to encrypt the
43 its public Diffie-Hellman key (PDH) and session parameters. These inputs
44 should be treated as a binary blob and must be passed as-is to the SEV firmware.
48 in bad measurement). The guest policy is a 4-byte data structure containing
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
65 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
90 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
109 /*----------------------------------------------------------------------
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/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
66 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
91 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
102 /*----------------------------------------------------------------------
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/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
65 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
90 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
111 /*----------------------------------------------------------------------
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/qemu/hw/misc/
H A Dgrlib_ahb_apb_pnp.c74 * 31 -------- 23 -------- 11 ----- 9 -------- 4 --- 0 in grlib_ahb_pnp_add_entry()
76 * -------------------------------------------------- in grlib_ahb_pnp_add_entry()
78 * -------------------------------------------------- in grlib_ahb_pnp_add_entry()
80 * -------------------------------------------------- in grlib_ahb_pnp_add_entry()
82 * -------------------------------------------------- in grlib_ahb_pnp_add_entry()
84 * -------------------------------------------------- in grlib_ahb_pnp_add_entry()
85 * 31 ----------- 20 --- 15 ----------------- 3 ---- 0 in grlib_ahb_pnp_add_entry()
87 * -------------------------------------------------- in grlib_ahb_pnp_add_entry()
88 * 31 ----------- 20 --- 15 ----------------- 3 ---- 0 in grlib_ahb_pnp_add_entry()
90 * -------------------------------------------------- in grlib_ahb_pnp_add_entry()
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/qemu/target/arm/tcg/
H A Dsme-fa64.decode24 # The Scalable Matrix Extension (SME), for Armv9-A
28 OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0]
29 OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0]
30 OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0]
31 OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0]
32 OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0]
33 OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0]
34 OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0]
36 FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations
41 OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar)
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/qemu/docs/specs/
H A Dacpi_pci_hotplug.rst1 QEMU<->ACPI BIOS PCI hotplug interface
7 ACPI GPE block (IO ports 0xafe0-0xafe3, byte access)
8 ----------------------------------------------------
13 PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access)
14 ------------------------------------------------------------------------------
19 events. Read-only.
21 PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access)
22 --------------------------------------------------------------------
27 events. Read-only.
29 PCI device eject (IO port 0xae08-0xae0b, 4-byte access)
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H A Dppc-xive.rst19 The XIVE IC is composed of three sub-engines, each taking care of a
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
25 controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
40 +------------------------------------+ IPIs
41 | +---------+ +---------+ +--------+ | +-------+
42 | |IVRE | |Common Q | |IVPE |----> | CORES |
43 | | esb | | | | |----> | |
44 | | eas | | Bridge | | tctx |----> | |
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/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2019 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
88 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
[all …]
/qemu/docs/
H A DCOLO-FT.txt1 COarse-grained LOck-stepping Virtual Machines for Non-stop Service
2 ----------------------------------------
8 See the COPYING file in the top-level directory.
14 application-agnostic software-implemented hardware fault tolerance,
15 also known as "non-stop service".
17 COLO (COarse-grained LOck-stepping) is a high availability solution.
45 +------------+ +-----------------------+ +------------------------+ +------------+
46 | | | HeartBeat +<----->+ HeartBeat | | |
47 | Primary VM | +-----------+-----------+ +-----------+------------+ |Secondary VM|
49 | | +-----------|-----------+ +-----------|------------+ | |
[all …]
H A Dpcie.txt25 QEMU does not have a clear socket-device matching mechanism
43 Note: Integrated Endpoints are not hot-pluggable.
51 (2) PCI Express Root Ports (pcie-root-port), for starting exclusively
54 (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy PCI
57 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses
61 ----------------------------------------------------------------------------
63 ----------- ------------------ ------------------- --------------
64 | PCI Dev | | PCIe Root Port | | PCIe-PCI Bridge | | pxb-pcie |
65 ----------- ------------------ ------------------- --------------
68 -device <dev>[,bus=pcie.0]
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/qemu/docs/devel/
H A Dvfio-iommufd.rst9 for assigned devices. While the legacy kernel interface is group-centric,
10 the new iommufd interface is device-centric, relying on device fd and iommufd.
25 +-------+ +----------+ +-----+ +-----+
27 +---+---+ +----+-----+ +--+--+ +--+--+ +----------------------+
29 | | | | +------------+---------+
30 +---V-----------V-----------V--------V----+ /
31 | VFIOAddressSpace | <------------+
34 +-------+----------------------------+----+
37 +-------V------+ +--------V----------+
40 +-------+------+ +--------+----------+
[all …]
H A Datomics.rst1 .. _atomics-ref:
8 but this can be a problem for CPU-CPU interaction (including interactions
9 between QEMU and the guest). Multi-threaded programs use various tools
17 the most performance-critical parts of QEMU in particular require
26 - compiler barriers: ``barrier()``;
28 - weak atomic access and manual memory barriers: ``qatomic_read()``,
33 - sequentially consistent atomic access: everything else.
36 used data structures (e.g. the lock-free singly-linked list operations
39 atomic operations and memory barriers should be limited to inter-thread
70 ``qemu/atomic.h`` provides the following set of atomic read-modify-write
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/qemu/scripts/
H A Dmeson-buildoptions.sh1 # This file is generated by meson-buildoptions.py, do not edit!
3 printf "%s\n" ' --audio-drv-list=CHOICES Set audio driver list [default] (choices: alsa/co'
6 printf "%s\n" ' --bindir=VALUE Executable directory [bin]'
7 printf "%s\n" ' --block-drv-ro-whitelist=VALUE'
8 printf "%s\n" ' set block driver read-only whitelist (by default'
9 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
10 printf "%s\n" ' --block-drv-rw-whitelist=VALUE'
11 printf "%s\n" ' set block driver read-write whitelist (by default'
12 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
13 printf "%s\n" ' --datadir=VALUE Data file directory [share]'
[all …]
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
[all …]
/qemu/tests/qemu-iotests/
H A D149.out1 # ================= dm-crypt aes-256-xts-plain64-sha1 =================
3 truncate TEST_DIR/luks-aes-256-xts-plain64-sha1.img --size 4194304MB
5 …-q -v luksFormat --type luks1 --cipher aes-xts-plain64 --key-size 512 --hash sha1 --key-slot 0 --k…
7 sudo cryptsetup -q -v luksOpen TEST_DIR/luks-aes-256-xts-plain64-sha1.img qiotest-145-aes-256-xts-p…
9 sudo chown UID:GID /dev/mapper/qiotest-145-aes-256-xts-plain64-sha1
10 qemu-io -c write -P 0xa7 100M 10M --image-opts driver=host_device,filename=/dev/mapper/qiotest-145-…
15 sudo chown UID:GID /dev/mapper/qiotest-145-aes-256-xts-plain64-sha1
16 qemu-io -c write -P 0x13 3145728M 10M --image-opts driver=host_device,filename=/dev/mapper/qiotest-…
21 sudo cryptsetup -q -v luksClose qiotest-145-aes-256-xts-plain64-sha1
23 …-io -c read -P 0xa7 100M 10M --object secret,id=sec0,data=MTIzNDU2,format=base64 --image-opts driv…
[all …]
/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
88 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
[all …]
/qemu/docs/system/devices/
H A Dccid.rst5 ---------------
27 --------
34 yum install libcacard-devel
38 apt-get install libcacard-dev
42 ./configure --enable-smartcard && make
44 Using ccid-card-emulated with hardware
45 --------------------------------------
47 user, using libcacard, QEMU acts as another client using ccid-card-emulated::
49 qemu -usb -device usb-ccid -device ccid-card-emulated
51 Using ccid-card-emulated with certificates stored in files
[all …]
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2016 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
[all …]
/qemu/include/hw/xen/interface/io/
H A Dnetif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified network-device I/O interface for Xen guest OSes.
7 * Copyright (c) 2003-2004, Keir Fraser
38 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume
43 * "feature-split-event-channels" is introduced to separate guest TX
49 * "event-channel-tx" and "event-channel-rx" respectively. If frontend
50 * doesn't want to use this feature, it just writes "event-channel"
56 * If supported, the backend will write the key "multi-queue-max-queues" to
60 * key "multi-queue-num-queues", set to the number they wish to use, which
62 * in "multi-queue-max-queues".
[all …]
/qemu/docs/interop/
H A Dvhost-user-gpu.rst2 Vhost-user-gpu Protocol
7 version 2 or later. See the COPYING file in the top-level
15 The vhost-user-gpu protocol is aiming at sharing the rendering result
16 of a virtio-gpu, done from a vhost-user back-end process to a vhost-user
17 front-end process (such as QEMU). It bears a resemblance to a display
19 back-end as the client, but in a very limited way. Typically, it will
29 Requests are sent by the *back-end*, and the optional replies by the
30 *front-end*.
38 A vhost-user-gpu message (request and reply) consists of 3 header
41 +---------+-------+------+---------+
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