1 /*
2 * QEMU Xtensa CPU
3 *
4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "cpu.h"
34 #include "fpu/softfloat.h"
35 #include "qemu/module.h"
36 #include "migration/vmstate.h"
37 #include "hw/qdev-clock.h"
38 #include "accel/tcg/cpu-ops.h"
39 #ifndef CONFIG_USER_ONLY
40 #include "system/memory.h"
41 #endif
42
43
xtensa_cpu_set_pc(CPUState * cs,vaddr value)44 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
45 {
46 XtensaCPU *cpu = XTENSA_CPU(cs);
47
48 cpu->env.pc = value;
49 }
50
xtensa_cpu_get_pc(CPUState * cs)51 static vaddr xtensa_cpu_get_pc(CPUState *cs)
52 {
53 XtensaCPU *cpu = XTENSA_CPU(cs);
54
55 return cpu->env.pc;
56 }
57
xtensa_get_tb_cpu_state(CPUState * cs)58 static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs)
59 {
60 CPUXtensaState *env = cpu_env(cs);
61 uint32_t flags = 0;
62 target_ulong cs_base = 0;
63
64 flags |= xtensa_get_ring(env);
65 if (env->sregs[PS] & PS_EXCM) {
66 flags |= XTENSA_TBFLAG_EXCM;
67 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
68 target_ulong lend_dist =
69 env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
70
71 /*
72 * 0 in the csbase_lend field means that there may not be a loopback
73 * for any instruction that starts inside this page. Any other value
74 * means that an instruction that ends at this offset from the page
75 * start may loop back and will need loopback code to be generated.
76 *
77 * lend_dist is 0 when LEND points to the start of the page, but
78 * no instruction that starts inside this page may end at offset 0,
79 * so it's still correct.
80 *
81 * When an instruction ends at a page boundary it may only start in
82 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
83 * for the TB that contains this instruction.
84 */
85 if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
86 target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
87
88 cs_base = lend_dist;
89 if (lbeg_off < 256) {
90 cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
91 }
92 }
93 }
94 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
95 (env->sregs[LITBASE] & 1)) {
96 flags |= XTENSA_TBFLAG_LITBASE;
97 }
98 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
99 if (xtensa_get_cintlevel(env) < env->config->debug_level) {
100 flags |= XTENSA_TBFLAG_DEBUG;
101 }
102 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
103 flags |= XTENSA_TBFLAG_ICOUNT;
104 }
105 }
106 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
107 flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
108 }
109 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
110 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
111 uint32_t windowstart = xtensa_replicate_windowstart(env) >>
112 (env->sregs[WINDOW_BASE] + 1);
113 uint32_t w = ctz32(windowstart | 0x8);
114
115 flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
116 flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
117 PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
118 } else {
119 flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
120 }
121 if (env->yield_needed) {
122 flags |= XTENSA_TBFLAG_YIELD;
123 }
124
125 return (TCGTBCPUState){
126 .pc = env->pc,
127 .flags = flags,
128 .cs_base = cs_base,
129 };
130 }
131
xtensa_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)132 static void xtensa_restore_state_to_opc(CPUState *cs,
133 const TranslationBlock *tb,
134 const uint64_t *data)
135 {
136 XtensaCPU *cpu = XTENSA_CPU(cs);
137
138 cpu->env.pc = data[0];
139 }
140
141 #ifndef CONFIG_USER_ONLY
xtensa_cpu_has_work(CPUState * cs)142 static bool xtensa_cpu_has_work(CPUState *cs)
143 {
144 CPUXtensaState *env = cpu_env(cs);
145
146 return !env->runstall && env->pending_irq_level;
147 }
148 #endif /* !CONFIG_USER_ONLY */
149
xtensa_cpu_mmu_index(CPUState * cs,bool ifetch)150 static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch)
151 {
152 return xtensa_get_cring(cpu_env(cs));
153 }
154
155 #ifdef CONFIG_USER_ONLY
156 static bool abi_call0;
157
xtensa_set_abi_call0(void)158 void xtensa_set_abi_call0(void)
159 {
160 abi_call0 = true;
161 }
162
xtensa_abi_call0(void)163 bool xtensa_abi_call0(void)
164 {
165 return abi_call0;
166 }
167 #endif
168
xtensa_cpu_reset_hold(Object * obj,ResetType type)169 static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
170 {
171 CPUState *cs = CPU(obj);
172 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
173 CPUXtensaState *env = cpu_env(cs);
174 bool dfpu = xtensa_option_enabled(env->config,
175 XTENSA_OPTION_DFP_COPROCESSOR);
176
177 if (xcc->parent_phases.hold) {
178 xcc->parent_phases.hold(obj, type);
179 }
180
181 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
182 env->sregs[LITBASE] &= ~1;
183 #ifndef CONFIG_USER_ONLY
184 env->sregs[PS] = xtensa_option_enabled(env->config,
185 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
186 env->pending_irq_level = 0;
187 #else
188 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
189 if (xtensa_option_enabled(env->config,
190 XTENSA_OPTION_WINDOWED_REGISTER) &&
191 !xtensa_abi_call0()) {
192 env->sregs[PS] |= PS_WOE;
193 }
194 env->sregs[CPENABLE] = 0xff;
195 #endif
196 env->sregs[VECBASE] = env->config->vecbase;
197 env->sregs[IBREAKENABLE] = 0;
198 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
199 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
200 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
201 env->sregs[CONFIGID0] = env->config->configid[0];
202 env->sregs[CONFIGID1] = env->config->configid[1];
203 env->exclusive_addr = -1;
204
205 #ifndef CONFIG_USER_ONLY
206 reset_mmu(env);
207 cs->halted = env->runstall;
208 #endif
209 /* For inf * 0 + NaN, return the input NaN */
210 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
211 set_no_signaling_nans(!dfpu, &env->fp_status);
212 /* Default NaN value: sign bit clear, set frac msb */
213 set_float_default_nan_pattern(0b01000000, &env->fp_status);
214 xtensa_use_first_nan(env, !dfpu);
215 }
216
xtensa_cpu_class_by_name(const char * cpu_model)217 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
218 {
219 ObjectClass *oc;
220 char *typename;
221
222 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
223 oc = object_class_by_name(typename);
224 g_free(typename);
225
226 return oc;
227 }
228
xtensa_cpu_disas_set_info(CPUState * cs,disassemble_info * info)229 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
230 {
231 XtensaCPU *cpu = XTENSA_CPU(cs);
232
233 info->private_data = cpu->env.config->isa;
234 info->print_insn = print_insn_xtensa;
235 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
236 : BFD_ENDIAN_LITTLE;
237 }
238
xtensa_cpu_realizefn(DeviceState * dev,Error ** errp)239 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
240 {
241 CPUState *cs = CPU(dev);
242 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
243 Error *local_err = NULL;
244
245 #ifndef CONFIG_USER_ONLY
246 xtensa_irq_init(&XTENSA_CPU(dev)->env);
247 #endif
248
249 cpu_exec_realizefn(cs, &local_err);
250 if (local_err != NULL) {
251 error_propagate(errp, local_err);
252 return;
253 }
254
255 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
256
257 qemu_init_vcpu(cs);
258
259 xcc->parent_realize(dev, errp);
260 }
261
xtensa_cpu_initfn(Object * obj)262 static void xtensa_cpu_initfn(Object *obj)
263 {
264 XtensaCPU *cpu = XTENSA_CPU(obj);
265 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
266 CPUXtensaState *env = &cpu->env;
267
268 env->config = xcc->config;
269
270 #ifndef CONFIG_USER_ONLY
271 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
272 env->system_er = g_malloc(sizeof(*env->system_er));
273 memory_region_init_io(env->system_er, obj, NULL, env, "er",
274 UINT64_C(0x100000000));
275 address_space_init(env->address_space_er, env->system_er, "ER");
276
277 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
278 clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
279 #endif
280 }
281
xtensa_cpu_create_with_clock(const char * cpu_type,Clock * cpu_refclk)282 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
283 {
284 DeviceState *cpu;
285
286 cpu = qdev_new(cpu_type);
287 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
288 qdev_realize(cpu, NULL, &error_abort);
289
290 return XTENSA_CPU(cpu);
291 }
292
293 #ifndef CONFIG_USER_ONLY
294 static const VMStateDescription vmstate_xtensa_cpu = {
295 .name = "cpu",
296 .unmigratable = 1,
297 };
298
299 #include "hw/core/sysemu-cpu-ops.h"
300
301 static const struct SysemuCPUOps xtensa_sysemu_ops = {
302 .has_work = xtensa_cpu_has_work,
303 .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
304 };
305 #endif
306
307 static const TCGCPUOps xtensa_tcg_ops = {
308 /* Xtensa processors have a weak memory model */
309 .guest_default_memory_order = 0,
310 .mttcg_supported = true,
311
312 .initialize = xtensa_translate_init,
313 .translate_code = xtensa_translate_code,
314 .debug_excp_handler = xtensa_breakpoint_handler,
315 .get_tb_cpu_state = xtensa_get_tb_cpu_state,
316 .restore_state_to_opc = xtensa_restore_state_to_opc,
317 .mmu_index = xtensa_cpu_mmu_index,
318
319 #ifndef CONFIG_USER_ONLY
320 .tlb_fill = xtensa_cpu_tlb_fill,
321 .pointer_wrap = cpu_pointer_wrap_uint32,
322 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
323 .cpu_exec_halt = xtensa_cpu_has_work,
324 .cpu_exec_reset = cpu_reset,
325 .do_interrupt = xtensa_cpu_do_interrupt,
326 .do_transaction_failed = xtensa_cpu_do_transaction_failed,
327 .do_unaligned_access = xtensa_cpu_do_unaligned_access,
328 .debug_check_breakpoint = xtensa_debug_check_breakpoint,
329 #endif /* !CONFIG_USER_ONLY */
330 };
331
xtensa_cpu_class_init(ObjectClass * oc,const void * data)332 static void xtensa_cpu_class_init(ObjectClass *oc, const void *data)
333 {
334 DeviceClass *dc = DEVICE_CLASS(oc);
335 CPUClass *cc = CPU_CLASS(oc);
336 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
337 ResettableClass *rc = RESETTABLE_CLASS(oc);
338
339 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
340 &xcc->parent_realize);
341
342 resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL,
343 &xcc->parent_phases);
344
345 cc->class_by_name = xtensa_cpu_class_by_name;
346 cc->dump_state = xtensa_cpu_dump_state;
347 cc->set_pc = xtensa_cpu_set_pc;
348 cc->get_pc = xtensa_cpu_get_pc;
349 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
350 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
351 cc->gdb_stop_before_watchpoint = true;
352 #ifndef CONFIG_USER_ONLY
353 cc->sysemu_ops = &xtensa_sysemu_ops;
354 dc->vmsd = &vmstate_xtensa_cpu;
355 #endif
356 cc->disas_set_info = xtensa_cpu_disas_set_info;
357 cc->tcg_ops = &xtensa_tcg_ops;
358 }
359
360 static const TypeInfo xtensa_cpu_type_info = {
361 .name = TYPE_XTENSA_CPU,
362 .parent = TYPE_CPU,
363 .instance_size = sizeof(XtensaCPU),
364 .instance_align = __alignof(XtensaCPU),
365 .instance_init = xtensa_cpu_initfn,
366 .abstract = true,
367 .class_size = sizeof(XtensaCPUClass),
368 .class_init = xtensa_cpu_class_init,
369 };
370
xtensa_cpu_register_types(void)371 static void xtensa_cpu_register_types(void)
372 {
373 type_register_static(&xtensa_cpu_type_info);
374 }
375
376 type_init(xtensa_cpu_register_types)
377