1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #include <linux/module.h>
9 #include <linux/spinlock.h>
10 #include <linux/tcp.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/clk.h>
14 #include <linux/if_ether.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/phy.h>
17 #include <net/vxlan.h>
18
19 #include "xgbe.h"
20 #include "xgbe-common.h"
21
22 static unsigned int ecc_sec_info_threshold = 10;
23 static unsigned int ecc_sec_warn_threshold = 10000;
24 static unsigned int ecc_sec_period = 600;
25 static unsigned int ecc_ded_threshold = 2;
26 static unsigned int ecc_ded_period = 600;
27
28 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
29 /* Only expose the ECC parameters if supported */
30 module_param(ecc_sec_info_threshold, uint, 0644);
31 MODULE_PARM_DESC(ecc_sec_info_threshold,
32 " ECC corrected error informational threshold setting");
33
34 module_param(ecc_sec_warn_threshold, uint, 0644);
35 MODULE_PARM_DESC(ecc_sec_warn_threshold,
36 " ECC corrected error warning threshold setting");
37
38 module_param(ecc_sec_period, uint, 0644);
39 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
40
41 module_param(ecc_ded_threshold, uint, 0644);
42 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
43
44 module_param(ecc_ded_period, uint, 0644);
45 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
46 #endif
47
48 static int xgbe_one_poll(struct napi_struct *, int);
49 static int xgbe_all_poll(struct napi_struct *, int);
50 static void xgbe_stop(struct xgbe_prv_data *);
51
xgbe_alloc_node(size_t size,int node)52 static void *xgbe_alloc_node(size_t size, int node)
53 {
54 void *mem;
55
56 mem = kzalloc_node(size, GFP_KERNEL, node);
57 if (!mem)
58 mem = kzalloc(size, GFP_KERNEL);
59
60 return mem;
61 }
62
xgbe_free_channels(struct xgbe_prv_data * pdata)63 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
64 {
65 unsigned int i;
66
67 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
68 if (!pdata->channel[i])
69 continue;
70
71 kfree(pdata->channel[i]->rx_ring);
72 kfree(pdata->channel[i]->tx_ring);
73 kfree(pdata->channel[i]);
74
75 pdata->channel[i] = NULL;
76 }
77
78 pdata->channel_count = 0;
79 }
80
xgbe_alloc_channels(struct xgbe_prv_data * pdata)81 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
82 {
83 struct xgbe_channel *channel;
84 struct xgbe_ring *ring;
85 unsigned int count, i;
86 unsigned int cpu;
87 int node;
88
89 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
90 for (i = 0; i < count; i++) {
91 /* Attempt to use a CPU on the node the device is on */
92 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
93
94 /* Set the allocation node based on the returned CPU */
95 node = cpu_to_node(cpu);
96
97 channel = xgbe_alloc_node(sizeof(*channel), node);
98 if (!channel)
99 goto err_mem;
100 pdata->channel[i] = channel;
101
102 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
103 channel->pdata = pdata;
104 channel->queue_index = i;
105 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
106 (DMA_CH_INC * i);
107 channel->node = node;
108 cpumask_set_cpu(cpu, &channel->affinity_mask);
109
110 if (pdata->per_channel_irq)
111 channel->dma_irq = pdata->channel_irq[i];
112
113 if (i < pdata->tx_ring_count) {
114 ring = xgbe_alloc_node(sizeof(*ring), node);
115 if (!ring)
116 goto err_mem;
117
118 spin_lock_init(&ring->lock);
119 ring->node = node;
120
121 channel->tx_ring = ring;
122 }
123
124 if (i < pdata->rx_ring_count) {
125 ring = xgbe_alloc_node(sizeof(*ring), node);
126 if (!ring)
127 goto err_mem;
128
129 spin_lock_init(&ring->lock);
130 ring->node = node;
131
132 channel->rx_ring = ring;
133 }
134
135 netif_dbg(pdata, drv, pdata->netdev,
136 "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
137
138 netif_dbg(pdata, drv, pdata->netdev,
139 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
140 channel->name, channel->dma_regs, channel->dma_irq,
141 channel->tx_ring, channel->rx_ring);
142 }
143
144 pdata->channel_count = count;
145
146 return 0;
147
148 err_mem:
149 xgbe_free_channels(pdata);
150
151 return -ENOMEM;
152 }
153
xgbe_tx_avail_desc(struct xgbe_ring * ring)154 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
155 {
156 return (ring->rdesc_count - (ring->cur - ring->dirty));
157 }
158
xgbe_rx_dirty_desc(struct xgbe_ring * ring)159 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
160 {
161 return (ring->cur - ring->dirty);
162 }
163
xgbe_maybe_stop_tx_queue(struct xgbe_channel * channel,struct xgbe_ring * ring,unsigned int count)164 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
165 struct xgbe_ring *ring, unsigned int count)
166 {
167 struct xgbe_prv_data *pdata = channel->pdata;
168
169 if (count > xgbe_tx_avail_desc(ring)) {
170 netif_info(pdata, drv, pdata->netdev,
171 "Tx queue stopped, not enough descriptors available\n");
172 netif_stop_subqueue(pdata->netdev, channel->queue_index);
173 ring->tx.queue_stopped = 1;
174
175 /* If we haven't notified the hardware because of xmit_more
176 * support, tell it now
177 */
178 if (ring->tx.xmit_more)
179 pdata->hw_if.tx_start_xmit(channel, ring);
180
181 return NETDEV_TX_BUSY;
182 }
183
184 return 0;
185 }
186
xgbe_calc_rx_buf_size(struct net_device * netdev,unsigned int mtu)187 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
188 {
189 unsigned int rx_buf_size;
190
191 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
192 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
193
194 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
195 ~(XGBE_RX_BUF_ALIGN - 1);
196
197 return rx_buf_size;
198 }
199
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)200 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
201 struct xgbe_channel *channel)
202 {
203 struct xgbe_hw_if *hw_if = &pdata->hw_if;
204 enum xgbe_int int_id;
205
206 if (channel->tx_ring && channel->rx_ring)
207 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
208 else if (channel->tx_ring)
209 int_id = XGMAC_INT_DMA_CH_SR_TI;
210 else if (channel->rx_ring)
211 int_id = XGMAC_INT_DMA_CH_SR_RI;
212 else
213 return;
214
215 hw_if->enable_int(channel, int_id);
216 }
217
xgbe_enable_rx_tx_ints(struct xgbe_prv_data * pdata)218 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
219 {
220 unsigned int i;
221
222 for (i = 0; i < pdata->channel_count; i++)
223 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
224 }
225
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)226 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
227 struct xgbe_channel *channel)
228 {
229 struct xgbe_hw_if *hw_if = &pdata->hw_if;
230 enum xgbe_int int_id;
231
232 if (channel->tx_ring && channel->rx_ring)
233 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
234 else if (channel->tx_ring)
235 int_id = XGMAC_INT_DMA_CH_SR_TI;
236 else if (channel->rx_ring)
237 int_id = XGMAC_INT_DMA_CH_SR_RI;
238 else
239 return;
240
241 hw_if->disable_int(channel, int_id);
242 }
243
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)244 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
245 {
246 unsigned int i;
247
248 for (i = 0; i < pdata->channel_count; i++)
249 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
250 }
251
xgbe_ecc_sec(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)252 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
253 unsigned int *count, const char *area)
254 {
255 if (time_before(jiffies, *period)) {
256 (*count)++;
257 } else {
258 *period = jiffies + (ecc_sec_period * HZ);
259 *count = 1;
260 }
261
262 if (*count > ecc_sec_info_threshold)
263 dev_warn_once(pdata->dev,
264 "%s ECC corrected errors exceed informational threshold\n",
265 area);
266
267 if (*count > ecc_sec_warn_threshold) {
268 dev_warn_once(pdata->dev,
269 "%s ECC corrected errors exceed warning threshold\n",
270 area);
271 return true;
272 }
273
274 return false;
275 }
276
xgbe_ecc_ded(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)277 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
278 unsigned int *count, const char *area)
279 {
280 if (time_before(jiffies, *period)) {
281 (*count)++;
282 } else {
283 *period = jiffies + (ecc_ded_period * HZ);
284 *count = 1;
285 }
286
287 if (*count > ecc_ded_threshold) {
288 netdev_alert(pdata->netdev,
289 "%s ECC detected errors exceed threshold\n",
290 area);
291 return true;
292 }
293
294 return false;
295 }
296
xgbe_ecc_isr_bh_work(struct work_struct * work)297 static void xgbe_ecc_isr_bh_work(struct work_struct *work)
298 {
299 struct xgbe_prv_data *pdata = from_work(pdata, work, ecc_bh_work);
300 unsigned int ecc_isr;
301 bool stop = false;
302
303 /* Mask status with only the interrupts we care about */
304 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
305 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
306 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
307
308 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
309 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
310 &pdata->tx_ded_count, "TX fifo");
311 }
312
313 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
314 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
315 &pdata->rx_ded_count, "RX fifo");
316 }
317
318 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
319 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
320 &pdata->desc_ded_count,
321 "descriptor cache");
322 }
323
324 if (stop) {
325 pdata->hw_if.disable_ecc_ded(pdata);
326 schedule_work(&pdata->stopdev_work);
327 goto out;
328 }
329
330 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
331 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
332 &pdata->tx_sec_count, "TX fifo"))
333 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
334 }
335
336 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
337 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
338 &pdata->rx_sec_count, "RX fifo"))
339 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
340
341 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
342 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
343 &pdata->desc_sec_count, "descriptor cache"))
344 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
345
346 out:
347 /* Clear all ECC interrupts */
348 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
349
350 /* Reissue interrupt if status is not clear */
351 if (pdata->vdata->irq_reissue_support)
352 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
353 }
354
xgbe_ecc_isr(int irq,void * data)355 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
356 {
357 struct xgbe_prv_data *pdata = data;
358
359 if (pdata->isr_as_bh_work)
360 queue_work(system_bh_wq, &pdata->ecc_bh_work);
361 else
362 xgbe_ecc_isr_bh_work(&pdata->ecc_bh_work);
363
364 return IRQ_HANDLED;
365 }
366
xgbe_isr_bh_work(struct work_struct * work)367 static void xgbe_isr_bh_work(struct work_struct *work)
368 {
369 struct xgbe_prv_data *pdata = from_work(pdata, work, dev_bh_work);
370 struct xgbe_hw_if *hw_if = &pdata->hw_if;
371 struct xgbe_channel *channel;
372 unsigned int dma_isr, dma_ch_isr;
373 unsigned int mac_isr, mac_tssr, mac_mdioisr;
374 unsigned int i;
375
376 /* The DMA interrupt status register also reports MAC and MTL
377 * interrupts. So for polling mode, we just need to check for
378 * this register to be non-zero
379 */
380 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
381 if (!dma_isr)
382 goto isr_done;
383
384 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
385
386 for (i = 0; i < pdata->channel_count; i++) {
387 if (!(dma_isr & (1 << i)))
388 continue;
389
390 channel = pdata->channel[i];
391
392 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
393 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
394 i, dma_ch_isr);
395
396 /* The TI or RI interrupt bits may still be set even if using
397 * per channel DMA interrupts. Check to be sure those are not
398 * enabled before using the private data napi structure.
399 */
400 if (!pdata->per_channel_irq &&
401 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
402 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
403 if (napi_schedule_prep(&pdata->napi)) {
404 /* Disable Tx and Rx interrupts */
405 xgbe_disable_rx_tx_ints(pdata);
406
407 /* Turn on polling */
408 __napi_schedule(&pdata->napi);
409 }
410 } else {
411 /* Don't clear Rx/Tx status if doing per channel DMA
412 * interrupts, these will be cleared by the ISR for
413 * per channel DMA interrupts.
414 */
415 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
416 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
417 }
418
419 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
420 pdata->ext_stats.rx_buffer_unavailable++;
421
422 /* Restart the device on a Fatal Bus Error */
423 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
424 schedule_work(&pdata->restart_work);
425
426 /* Clear interrupt signals */
427 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
428 }
429
430 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
431 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
432
433 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
434 mac_isr);
435
436 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
437 hw_if->tx_mmc_int(pdata);
438
439 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
440 hw_if->rx_mmc_int(pdata);
441
442 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
443 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
444
445 netif_dbg(pdata, intr, pdata->netdev,
446 "MAC_TSSR=%#010x\n", mac_tssr);
447
448 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
449 /* Read Tx Timestamp to clear interrupt */
450 pdata->tx_tstamp =
451 xgbe_get_tx_tstamp(pdata);
452 queue_work(pdata->dev_workqueue,
453 &pdata->tx_tstamp_work);
454 }
455 }
456
457 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
458 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
459
460 netif_dbg(pdata, intr, pdata->netdev,
461 "MAC_MDIOISR=%#010x\n", mac_mdioisr);
462
463 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
464 SNGLCOMPINT))
465 complete(&pdata->mdio_complete);
466 }
467 }
468
469 isr_done:
470 /* If there is not a separate AN irq, handle it here */
471 if (pdata->dev_irq == pdata->an_irq)
472 pdata->phy_if.an_isr(pdata);
473
474 /* If there is not a separate ECC irq, handle it here */
475 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
476 xgbe_ecc_isr_bh_work(&pdata->ecc_bh_work);
477
478 /* If there is not a separate I2C irq, handle it here */
479 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
480 pdata->i2c_if.i2c_isr(pdata);
481
482 /* Reissue interrupt if status is not clear */
483 if (pdata->vdata->irq_reissue_support) {
484 unsigned int reissue_mask;
485
486 reissue_mask = 1 << 0;
487 if (!pdata->per_channel_irq)
488 reissue_mask |= 0xffff << 4;
489
490 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
491 }
492 }
493
xgbe_isr(int irq,void * data)494 static irqreturn_t xgbe_isr(int irq, void *data)
495 {
496 struct xgbe_prv_data *pdata = data;
497
498 if (pdata->isr_as_bh_work)
499 queue_work(system_bh_wq, &pdata->dev_bh_work);
500 else
501 xgbe_isr_bh_work(&pdata->dev_bh_work);
502
503 return IRQ_HANDLED;
504 }
505
xgbe_dma_isr(int irq,void * data)506 static irqreturn_t xgbe_dma_isr(int irq, void *data)
507 {
508 struct xgbe_channel *channel = data;
509 struct xgbe_prv_data *pdata = channel->pdata;
510 unsigned int dma_status;
511
512 /* Per channel DMA interrupts are enabled, so we use the per
513 * channel napi structure and not the private data napi structure
514 */
515 if (napi_schedule_prep(&channel->napi)) {
516 /* Disable Tx and Rx interrupts */
517 if (pdata->channel_irq_mode)
518 xgbe_disable_rx_tx_int(pdata, channel);
519 else
520 disable_irq_nosync(channel->dma_irq);
521
522 /* Turn on polling */
523 __napi_schedule_irqoff(&channel->napi);
524 }
525
526 /* Clear Tx/Rx signals */
527 dma_status = 0;
528 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
529 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
530 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
531
532 return IRQ_HANDLED;
533 }
534
xgbe_tx_timer(struct timer_list * t)535 static void xgbe_tx_timer(struct timer_list *t)
536 {
537 struct xgbe_channel *channel = timer_container_of(channel, t,
538 tx_timer);
539 struct xgbe_prv_data *pdata = channel->pdata;
540 struct napi_struct *napi;
541
542 DBGPR("-->xgbe_tx_timer\n");
543
544 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
545
546 if (napi_schedule_prep(napi)) {
547 /* Disable Tx and Rx interrupts */
548 if (pdata->per_channel_irq)
549 if (pdata->channel_irq_mode)
550 xgbe_disable_rx_tx_int(pdata, channel);
551 else
552 disable_irq_nosync(channel->dma_irq);
553 else
554 xgbe_disable_rx_tx_ints(pdata);
555
556 /* Turn on polling */
557 __napi_schedule(napi);
558 }
559
560 channel->tx_timer_active = 0;
561
562 DBGPR("<--xgbe_tx_timer\n");
563 }
564
xgbe_service(struct work_struct * work)565 static void xgbe_service(struct work_struct *work)
566 {
567 struct xgbe_prv_data *pdata = container_of(work,
568 struct xgbe_prv_data,
569 service_work);
570
571 pdata->phy_if.phy_status(pdata);
572 }
573
xgbe_service_timer(struct timer_list * t)574 static void xgbe_service_timer(struct timer_list *t)
575 {
576 struct xgbe_prv_data *pdata = timer_container_of(pdata, t,
577 service_timer);
578 struct xgbe_channel *channel;
579 unsigned int i;
580
581 queue_work(pdata->dev_workqueue, &pdata->service_work);
582
583 mod_timer(&pdata->service_timer, jiffies + HZ);
584
585 if (!pdata->tx_usecs)
586 return;
587
588 for (i = 0; i < pdata->channel_count; i++) {
589 channel = pdata->channel[i];
590 if (!channel->tx_ring || channel->tx_timer_active)
591 break;
592 channel->tx_timer_active = 1;
593 mod_timer(&channel->tx_timer,
594 jiffies + usecs_to_jiffies(pdata->tx_usecs));
595 }
596 }
597
xgbe_init_timers(struct xgbe_prv_data * pdata)598 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
599 {
600 struct xgbe_channel *channel;
601 unsigned int i;
602
603 timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
604
605 for (i = 0; i < pdata->channel_count; i++) {
606 channel = pdata->channel[i];
607 if (!channel->tx_ring)
608 break;
609
610 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
611 }
612 }
613
xgbe_start_timers(struct xgbe_prv_data * pdata)614 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
615 {
616 mod_timer(&pdata->service_timer, jiffies + HZ);
617 }
618
xgbe_stop_timers(struct xgbe_prv_data * pdata)619 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
620 {
621 struct xgbe_channel *channel;
622 unsigned int i;
623
624 timer_delete_sync(&pdata->service_timer);
625
626 for (i = 0; i < pdata->channel_count; i++) {
627 channel = pdata->channel[i];
628 if (!channel->tx_ring)
629 break;
630
631 /* Deactivate the Tx timer */
632 timer_delete_sync(&channel->tx_timer);
633 channel->tx_timer_active = 0;
634 }
635 }
636
xgbe_get_all_hw_features(struct xgbe_prv_data * pdata)637 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
638 {
639 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
640 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
641
642 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
643 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
644 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
645
646 memset(hw_feat, 0, sizeof(*hw_feat));
647
648 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
649
650 /* Hardware feature register 0 */
651 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
652 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
653 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
654 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
655 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
656 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
657 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
658 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
659 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
660 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
661 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
662 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
663 ADDMACADRSEL);
664 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
665 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
666 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
667
668 /* Hardware feature register 1 */
669 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
670 RXFIFOSIZE);
671 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
672 TXFIFOSIZE);
673 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
674 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
675 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
676 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
677 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
678 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
679 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
680 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
681 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
682 HASHTBLSZ);
683 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
684 L3L4FNUM);
685
686 /* Hardware feature register 2 */
687 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
688 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
689 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
690 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
691 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
692 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
693
694 /* Translate the Hash Table size into actual number */
695 switch (hw_feat->hash_table_size) {
696 case 0:
697 break;
698 case 1:
699 hw_feat->hash_table_size = 64;
700 break;
701 case 2:
702 hw_feat->hash_table_size = 128;
703 break;
704 case 3:
705 hw_feat->hash_table_size = 256;
706 break;
707 }
708
709 /* Translate the address width setting into actual number */
710 switch (hw_feat->dma_width) {
711 case 0:
712 hw_feat->dma_width = 32;
713 break;
714 case 1:
715 hw_feat->dma_width = 40;
716 break;
717 case 2:
718 hw_feat->dma_width = 48;
719 break;
720 default:
721 hw_feat->dma_width = 32;
722 }
723
724 /* The Queue, Channel and TC counts are zero based so increment them
725 * to get the actual number
726 */
727 hw_feat->rx_q_cnt++;
728 hw_feat->tx_q_cnt++;
729 hw_feat->rx_ch_cnt++;
730 hw_feat->tx_ch_cnt++;
731 hw_feat->tc_cnt++;
732
733 /* Translate the fifo sizes into actual numbers */
734 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
735 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
736
737 if (netif_msg_probe(pdata)) {
738 dev_dbg(pdata->dev, "Hardware features:\n");
739
740 /* Hardware feature register 0 */
741 dev_dbg(pdata->dev, " 1GbE support : %s\n",
742 hw_feat->gmii ? "yes" : "no");
743 dev_dbg(pdata->dev, " VLAN hash filter : %s\n",
744 hw_feat->vlhash ? "yes" : "no");
745 dev_dbg(pdata->dev, " MDIO interface : %s\n",
746 hw_feat->sma ? "yes" : "no");
747 dev_dbg(pdata->dev, " Wake-up packet support : %s\n",
748 hw_feat->rwk ? "yes" : "no");
749 dev_dbg(pdata->dev, " Magic packet support : %s\n",
750 hw_feat->mgk ? "yes" : "no");
751 dev_dbg(pdata->dev, " Management counters : %s\n",
752 hw_feat->mmc ? "yes" : "no");
753 dev_dbg(pdata->dev, " ARP offload : %s\n",
754 hw_feat->aoe ? "yes" : "no");
755 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n",
756 hw_feat->ts ? "yes" : "no");
757 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n",
758 hw_feat->eee ? "yes" : "no");
759 dev_dbg(pdata->dev, " TX checksum offload : %s\n",
760 hw_feat->tx_coe ? "yes" : "no");
761 dev_dbg(pdata->dev, " RX checksum offload : %s\n",
762 hw_feat->rx_coe ? "yes" : "no");
763 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n",
764 hw_feat->addn_mac);
765 dev_dbg(pdata->dev, " Timestamp source : %s\n",
766 (hw_feat->ts_src == 1) ? "internal" :
767 (hw_feat->ts_src == 2) ? "external" :
768 (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
769 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n",
770 hw_feat->sa_vlan_ins ? "yes" : "no");
771 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n",
772 hw_feat->vxn ? "yes" : "no");
773
774 /* Hardware feature register 1 */
775 dev_dbg(pdata->dev, " RX fifo size : %u\n",
776 hw_feat->rx_fifo_size);
777 dev_dbg(pdata->dev, " TX fifo size : %u\n",
778 hw_feat->tx_fifo_size);
779 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n",
780 hw_feat->adv_ts_hi ? "yes" : "no");
781 dev_dbg(pdata->dev, " DMA width : %u\n",
782 hw_feat->dma_width);
783 dev_dbg(pdata->dev, " Data Center Bridging : %s\n",
784 hw_feat->dcb ? "yes" : "no");
785 dev_dbg(pdata->dev, " Split header : %s\n",
786 hw_feat->sph ? "yes" : "no");
787 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n",
788 hw_feat->tso ? "yes" : "no");
789 dev_dbg(pdata->dev, " Debug memory interface : %s\n",
790 hw_feat->dma_debug ? "yes" : "no");
791 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n",
792 hw_feat->rss ? "yes" : "no");
793 dev_dbg(pdata->dev, " Traffic Class count : %u\n",
794 hw_feat->tc_cnt);
795 dev_dbg(pdata->dev, " Hash table size : %u\n",
796 hw_feat->hash_table_size);
797 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n",
798 hw_feat->l3l4_filter_num);
799
800 /* Hardware feature register 2 */
801 dev_dbg(pdata->dev, " RX queue count : %u\n",
802 hw_feat->rx_q_cnt);
803 dev_dbg(pdata->dev, " TX queue count : %u\n",
804 hw_feat->tx_q_cnt);
805 dev_dbg(pdata->dev, " RX DMA channel count : %u\n",
806 hw_feat->rx_ch_cnt);
807 dev_dbg(pdata->dev, " TX DMA channel count : %u\n",
808 hw_feat->rx_ch_cnt);
809 dev_dbg(pdata->dev, " PPS outputs : %u\n",
810 hw_feat->pps_out_num);
811 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n",
812 hw_feat->aux_snap_num);
813 }
814 }
815
xgbe_vxlan_set_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)816 static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table,
817 unsigned int entry, struct udp_tunnel_info *ti)
818 {
819 struct xgbe_prv_data *pdata = netdev_priv(netdev);
820
821 pdata->vxlan_port = be16_to_cpu(ti->port);
822 pdata->hw_if.enable_vxlan(pdata);
823
824 return 0;
825 }
826
xgbe_vxlan_unset_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)827 static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table,
828 unsigned int entry, struct udp_tunnel_info *ti)
829 {
830 struct xgbe_prv_data *pdata = netdev_priv(netdev);
831
832 pdata->hw_if.disable_vxlan(pdata);
833 pdata->vxlan_port = 0;
834
835 return 0;
836 }
837
838 static const struct udp_tunnel_nic_info xgbe_udp_tunnels = {
839 .set_port = xgbe_vxlan_set_port,
840 .unset_port = xgbe_vxlan_unset_port,
841 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
842 .tables = {
843 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
844 },
845 };
846
xgbe_get_udp_tunnel_info(void)847 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void)
848 {
849 return &xgbe_udp_tunnels;
850 }
851
xgbe_napi_enable(struct xgbe_prv_data * pdata,unsigned int add)852 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
853 {
854 struct xgbe_channel *channel;
855 unsigned int i;
856
857 if (pdata->per_channel_irq) {
858 for (i = 0; i < pdata->channel_count; i++) {
859 channel = pdata->channel[i];
860 if (add)
861 netif_napi_add(pdata->netdev, &channel->napi,
862 xgbe_one_poll);
863
864 napi_enable(&channel->napi);
865 }
866 } else {
867 if (add)
868 netif_napi_add(pdata->netdev, &pdata->napi,
869 xgbe_all_poll);
870
871 napi_enable(&pdata->napi);
872 }
873 }
874
xgbe_napi_disable(struct xgbe_prv_data * pdata,unsigned int del)875 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
876 {
877 struct xgbe_channel *channel;
878 unsigned int i;
879
880 if (pdata->per_channel_irq) {
881 for (i = 0; i < pdata->channel_count; i++) {
882 channel = pdata->channel[i];
883 napi_disable(&channel->napi);
884
885 if (del)
886 netif_napi_del(&channel->napi);
887 }
888 } else {
889 napi_disable(&pdata->napi);
890
891 if (del)
892 netif_napi_del(&pdata->napi);
893 }
894 }
895
xgbe_request_irqs(struct xgbe_prv_data * pdata)896 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
897 {
898 struct xgbe_channel *channel;
899 struct net_device *netdev = pdata->netdev;
900 unsigned int i;
901 int ret;
902
903 INIT_WORK(&pdata->dev_bh_work, xgbe_isr_bh_work);
904 INIT_WORK(&pdata->ecc_bh_work, xgbe_ecc_isr_bh_work);
905
906 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
907 netdev_name(netdev), pdata);
908 if (ret) {
909 netdev_alert(netdev, "error requesting irq %d\n",
910 pdata->dev_irq);
911 return ret;
912 }
913
914 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
915 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
916 0, pdata->ecc_name, pdata);
917 if (ret) {
918 netdev_alert(netdev, "error requesting ecc irq %d\n",
919 pdata->ecc_irq);
920 goto err_dev_irq;
921 }
922 }
923
924 if (!pdata->per_channel_irq)
925 return 0;
926
927 for (i = 0; i < pdata->channel_count; i++) {
928 channel = pdata->channel[i];
929 snprintf(channel->dma_irq_name,
930 sizeof(channel->dma_irq_name) - 1,
931 "%s-TxRx-%u", netdev_name(netdev),
932 channel->queue_index);
933
934 ret = devm_request_irq(pdata->dev, channel->dma_irq,
935 xgbe_dma_isr, 0,
936 channel->dma_irq_name, channel);
937 if (ret) {
938 netdev_alert(netdev, "error requesting irq %d\n",
939 channel->dma_irq);
940 goto err_dma_irq;
941 }
942
943 irq_set_affinity_hint(channel->dma_irq,
944 &channel->affinity_mask);
945 }
946
947 return 0;
948
949 err_dma_irq:
950 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
951 for (i--; i < pdata->channel_count; i--) {
952 channel = pdata->channel[i];
953
954 irq_set_affinity_hint(channel->dma_irq, NULL);
955 devm_free_irq(pdata->dev, channel->dma_irq, channel);
956 }
957
958 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
959 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
960
961 err_dev_irq:
962 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
963
964 return ret;
965 }
966
xgbe_free_irqs(struct xgbe_prv_data * pdata)967 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
968 {
969 struct xgbe_channel *channel;
970 unsigned int i;
971
972 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
973
974 cancel_work_sync(&pdata->dev_bh_work);
975 cancel_work_sync(&pdata->ecc_bh_work);
976
977 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
978 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
979
980 if (!pdata->per_channel_irq)
981 return;
982
983 for (i = 0; i < pdata->channel_count; i++) {
984 channel = pdata->channel[i];
985
986 irq_set_affinity_hint(channel->dma_irq, NULL);
987 devm_free_irq(pdata->dev, channel->dma_irq, channel);
988 }
989 }
990
xgbe_init_tx_coalesce(struct xgbe_prv_data * pdata)991 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
992 {
993 struct xgbe_hw_if *hw_if = &pdata->hw_if;
994
995 DBGPR("-->xgbe_init_tx_coalesce\n");
996
997 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
998 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
999
1000 hw_if->config_tx_coalesce(pdata);
1001
1002 DBGPR("<--xgbe_init_tx_coalesce\n");
1003 }
1004
xgbe_init_rx_coalesce(struct xgbe_prv_data * pdata)1005 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1006 {
1007 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1008
1009 DBGPR("-->xgbe_init_rx_coalesce\n");
1010
1011 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1012 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1013 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1014
1015 hw_if->config_rx_coalesce(pdata);
1016
1017 DBGPR("<--xgbe_init_rx_coalesce\n");
1018 }
1019
xgbe_free_tx_data(struct xgbe_prv_data * pdata)1020 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1021 {
1022 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1023 struct xgbe_ring *ring;
1024 struct xgbe_ring_data *rdata;
1025 unsigned int i, j;
1026
1027 DBGPR("-->xgbe_free_tx_data\n");
1028
1029 for (i = 0; i < pdata->channel_count; i++) {
1030 ring = pdata->channel[i]->tx_ring;
1031 if (!ring)
1032 break;
1033
1034 for (j = 0; j < ring->rdesc_count; j++) {
1035 rdata = XGBE_GET_DESC_DATA(ring, j);
1036 desc_if->unmap_rdata(pdata, rdata);
1037 }
1038 }
1039
1040 DBGPR("<--xgbe_free_tx_data\n");
1041 }
1042
xgbe_free_rx_data(struct xgbe_prv_data * pdata)1043 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1044 {
1045 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1046 struct xgbe_ring *ring;
1047 struct xgbe_ring_data *rdata;
1048 unsigned int i, j;
1049
1050 DBGPR("-->xgbe_free_rx_data\n");
1051
1052 for (i = 0; i < pdata->channel_count; i++) {
1053 ring = pdata->channel[i]->rx_ring;
1054 if (!ring)
1055 break;
1056
1057 for (j = 0; j < ring->rdesc_count; j++) {
1058 rdata = XGBE_GET_DESC_DATA(ring, j);
1059 desc_if->unmap_rdata(pdata, rdata);
1060 }
1061 }
1062
1063 DBGPR("<--xgbe_free_rx_data\n");
1064 }
1065
xgbe_phy_reset(struct xgbe_prv_data * pdata)1066 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1067 {
1068 pdata->phy_link = -1;
1069 pdata->phy_speed = SPEED_UNKNOWN;
1070
1071 return pdata->phy_if.phy_reset(pdata);
1072 }
1073
xgbe_powerdown(struct net_device * netdev,unsigned int caller)1074 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1075 {
1076 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1077 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1078 unsigned long flags;
1079
1080 DBGPR("-->xgbe_powerdown\n");
1081
1082 if (!netif_running(netdev) ||
1083 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1084 netdev_alert(netdev, "Device is already powered down\n");
1085 DBGPR("<--xgbe_powerdown\n");
1086 return -EINVAL;
1087 }
1088
1089 spin_lock_irqsave(&pdata->lock, flags);
1090
1091 if (caller == XGMAC_DRIVER_CONTEXT)
1092 netif_device_detach(netdev);
1093
1094 netif_tx_stop_all_queues(netdev);
1095
1096 xgbe_stop_timers(pdata);
1097 flush_workqueue(pdata->dev_workqueue);
1098
1099 hw_if->powerdown_tx(pdata);
1100 hw_if->powerdown_rx(pdata);
1101
1102 xgbe_napi_disable(pdata, 0);
1103
1104 pdata->power_down = 1;
1105
1106 spin_unlock_irqrestore(&pdata->lock, flags);
1107
1108 DBGPR("<--xgbe_powerdown\n");
1109
1110 return 0;
1111 }
1112
xgbe_powerup(struct net_device * netdev,unsigned int caller)1113 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1114 {
1115 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1116 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1117 unsigned long flags;
1118
1119 DBGPR("-->xgbe_powerup\n");
1120
1121 if (!netif_running(netdev) ||
1122 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1123 netdev_alert(netdev, "Device is already powered up\n");
1124 DBGPR("<--xgbe_powerup\n");
1125 return -EINVAL;
1126 }
1127
1128 spin_lock_irqsave(&pdata->lock, flags);
1129
1130 pdata->power_down = 0;
1131
1132 xgbe_napi_enable(pdata, 0);
1133
1134 hw_if->powerup_tx(pdata);
1135 hw_if->powerup_rx(pdata);
1136
1137 if (caller == XGMAC_DRIVER_CONTEXT)
1138 netif_device_attach(netdev);
1139
1140 netif_tx_start_all_queues(netdev);
1141
1142 xgbe_start_timers(pdata);
1143
1144 spin_unlock_irqrestore(&pdata->lock, flags);
1145
1146 DBGPR("<--xgbe_powerup\n");
1147
1148 return 0;
1149 }
1150
xgbe_free_memory(struct xgbe_prv_data * pdata)1151 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1152 {
1153 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1154
1155 /* Free the ring descriptors and buffers */
1156 desc_if->free_ring_resources(pdata);
1157
1158 /* Free the channel and ring structures */
1159 xgbe_free_channels(pdata);
1160 }
1161
xgbe_alloc_memory(struct xgbe_prv_data * pdata)1162 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1163 {
1164 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1165 struct net_device *netdev = pdata->netdev;
1166 int ret;
1167
1168 if (pdata->new_tx_ring_count) {
1169 pdata->tx_ring_count = pdata->new_tx_ring_count;
1170 pdata->tx_q_count = pdata->tx_ring_count;
1171 pdata->new_tx_ring_count = 0;
1172 }
1173
1174 if (pdata->new_rx_ring_count) {
1175 pdata->rx_ring_count = pdata->new_rx_ring_count;
1176 pdata->new_rx_ring_count = 0;
1177 }
1178
1179 /* Calculate the Rx buffer size before allocating rings */
1180 pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1181
1182 /* Allocate the channel and ring structures */
1183 ret = xgbe_alloc_channels(pdata);
1184 if (ret)
1185 return ret;
1186
1187 /* Allocate the ring descriptors and buffers */
1188 ret = desc_if->alloc_ring_resources(pdata);
1189 if (ret)
1190 goto err_channels;
1191
1192 /* Initialize the service and Tx timers */
1193 xgbe_init_timers(pdata);
1194
1195 return 0;
1196
1197 err_channels:
1198 xgbe_free_memory(pdata);
1199
1200 return ret;
1201 }
1202
xgbe_start(struct xgbe_prv_data * pdata)1203 static int xgbe_start(struct xgbe_prv_data *pdata)
1204 {
1205 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1206 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1207 struct net_device *netdev = pdata->netdev;
1208 unsigned int i;
1209 int ret;
1210
1211 /* Set the number of queues */
1212 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1213 if (ret) {
1214 netdev_err(netdev, "error setting real tx queue count\n");
1215 return ret;
1216 }
1217
1218 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1219 if (ret) {
1220 netdev_err(netdev, "error setting real rx queue count\n");
1221 return ret;
1222 }
1223
1224 /* Set RSS lookup table data for programming */
1225 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1226 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1227 i % pdata->rx_ring_count);
1228
1229 ret = hw_if->init(pdata);
1230 if (ret)
1231 return ret;
1232
1233 xgbe_napi_enable(pdata, 1);
1234
1235 ret = xgbe_request_irqs(pdata);
1236 if (ret)
1237 goto err_napi;
1238
1239 ret = phy_if->phy_start(pdata);
1240 if (ret)
1241 goto err_irqs;
1242
1243 hw_if->enable_tx(pdata);
1244 hw_if->enable_rx(pdata);
1245
1246 udp_tunnel_nic_reset_ntf(netdev);
1247
1248 netif_tx_start_all_queues(netdev);
1249
1250 xgbe_start_timers(pdata);
1251 queue_work(pdata->dev_workqueue, &pdata->service_work);
1252
1253 clear_bit(XGBE_STOPPED, &pdata->dev_state);
1254
1255 return 0;
1256
1257 err_irqs:
1258 xgbe_free_irqs(pdata);
1259
1260 err_napi:
1261 xgbe_napi_disable(pdata, 1);
1262
1263 hw_if->exit(pdata);
1264
1265 return ret;
1266 }
1267
xgbe_stop(struct xgbe_prv_data * pdata)1268 static void xgbe_stop(struct xgbe_prv_data *pdata)
1269 {
1270 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1271 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1272 struct xgbe_channel *channel;
1273 struct net_device *netdev = pdata->netdev;
1274 struct netdev_queue *txq;
1275 unsigned int i;
1276
1277 DBGPR("-->xgbe_stop\n");
1278
1279 if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1280 return;
1281
1282 netif_tx_stop_all_queues(netdev);
1283 netif_carrier_off(pdata->netdev);
1284
1285 xgbe_stop_timers(pdata);
1286 flush_workqueue(pdata->dev_workqueue);
1287
1288 xgbe_vxlan_unset_port(netdev, 0, 0, NULL);
1289
1290 hw_if->disable_tx(pdata);
1291 hw_if->disable_rx(pdata);
1292
1293 phy_if->phy_stop(pdata);
1294
1295 xgbe_free_irqs(pdata);
1296
1297 xgbe_napi_disable(pdata, 1);
1298
1299 hw_if->exit(pdata);
1300
1301 for (i = 0; i < pdata->channel_count; i++) {
1302 channel = pdata->channel[i];
1303 if (!channel->tx_ring)
1304 continue;
1305
1306 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1307 netdev_tx_reset_queue(txq);
1308 }
1309
1310 set_bit(XGBE_STOPPED, &pdata->dev_state);
1311
1312 DBGPR("<--xgbe_stop\n");
1313 }
1314
xgbe_stopdev(struct work_struct * work)1315 static void xgbe_stopdev(struct work_struct *work)
1316 {
1317 struct xgbe_prv_data *pdata = container_of(work,
1318 struct xgbe_prv_data,
1319 stopdev_work);
1320
1321 rtnl_lock();
1322
1323 xgbe_stop(pdata);
1324
1325 xgbe_free_tx_data(pdata);
1326 xgbe_free_rx_data(pdata);
1327
1328 rtnl_unlock();
1329
1330 netdev_alert(pdata->netdev, "device stopped\n");
1331 }
1332
xgbe_full_restart_dev(struct xgbe_prv_data * pdata)1333 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1334 {
1335 /* If not running, "restart" will happen on open */
1336 if (!netif_running(pdata->netdev))
1337 return;
1338
1339 xgbe_stop(pdata);
1340
1341 xgbe_free_memory(pdata);
1342 xgbe_alloc_memory(pdata);
1343
1344 xgbe_start(pdata);
1345 }
1346
xgbe_restart_dev(struct xgbe_prv_data * pdata)1347 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1348 {
1349 /* If not running, "restart" will happen on open */
1350 if (!netif_running(pdata->netdev))
1351 return;
1352
1353 xgbe_stop(pdata);
1354
1355 xgbe_free_tx_data(pdata);
1356 xgbe_free_rx_data(pdata);
1357
1358 xgbe_start(pdata);
1359 }
1360
xgbe_restart(struct work_struct * work)1361 static void xgbe_restart(struct work_struct *work)
1362 {
1363 struct xgbe_prv_data *pdata = container_of(work,
1364 struct xgbe_prv_data,
1365 restart_work);
1366
1367 rtnl_lock();
1368
1369 xgbe_restart_dev(pdata);
1370
1371 rtnl_unlock();
1372 }
1373
xgbe_prep_vlan(struct sk_buff * skb,struct xgbe_packet_data * packet)1374 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1375 {
1376 if (skb_vlan_tag_present(skb))
1377 packet->vlan_ctag = skb_vlan_tag_get(skb);
1378 }
1379
xgbe_prep_tso(struct sk_buff * skb,struct xgbe_packet_data * packet)1380 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1381 {
1382 int ret;
1383
1384 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1385 TSO_ENABLE))
1386 return 0;
1387
1388 ret = skb_cow_head(skb, 0);
1389 if (ret)
1390 return ret;
1391
1392 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1393 packet->header_len = skb_inner_tcp_all_headers(skb);
1394 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1395 } else {
1396 packet->header_len = skb_tcp_all_headers(skb);
1397 packet->tcp_header_len = tcp_hdrlen(skb);
1398 }
1399 packet->tcp_payload_len = skb->len - packet->header_len;
1400 packet->mss = skb_shinfo(skb)->gso_size;
1401
1402 DBGPR(" packet->header_len=%u\n", packet->header_len);
1403 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1404 packet->tcp_header_len, packet->tcp_payload_len);
1405 DBGPR(" packet->mss=%u\n", packet->mss);
1406
1407 /* Update the number of packets that will ultimately be transmitted
1408 * along with the extra bytes for each extra packet
1409 */
1410 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1411 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1412
1413 return 0;
1414 }
1415
xgbe_is_vxlan(struct sk_buff * skb)1416 static bool xgbe_is_vxlan(struct sk_buff *skb)
1417 {
1418 if (!skb->encapsulation)
1419 return false;
1420
1421 if (skb->ip_summed != CHECKSUM_PARTIAL)
1422 return false;
1423
1424 switch (skb->protocol) {
1425 case htons(ETH_P_IP):
1426 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1427 return false;
1428 break;
1429
1430 case htons(ETH_P_IPV6):
1431 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1432 return false;
1433 break;
1434
1435 default:
1436 return false;
1437 }
1438
1439 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1440 skb->inner_protocol != htons(ETH_P_TEB) ||
1441 (skb_inner_mac_header(skb) - skb_transport_header(skb) !=
1442 sizeof(struct udphdr) + sizeof(struct vxlanhdr)))
1443 return false;
1444
1445 return true;
1446 }
1447
xgbe_is_tso(struct sk_buff * skb)1448 static int xgbe_is_tso(struct sk_buff *skb)
1449 {
1450 if (skb->ip_summed != CHECKSUM_PARTIAL)
1451 return 0;
1452
1453 if (!skb_is_gso(skb))
1454 return 0;
1455
1456 DBGPR(" TSO packet to be processed\n");
1457
1458 return 1;
1459 }
1460
xgbe_packet_info(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,struct sk_buff * skb,struct xgbe_packet_data * packet)1461 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1462 struct xgbe_ring *ring, struct sk_buff *skb,
1463 struct xgbe_packet_data *packet)
1464 {
1465 skb_frag_t *frag;
1466 unsigned int context_desc;
1467 unsigned int len;
1468 unsigned int i;
1469
1470 packet->skb = skb;
1471
1472 context_desc = 0;
1473 packet->rdesc_count = 0;
1474
1475 packet->tx_packets = 1;
1476 packet->tx_bytes = skb->len;
1477
1478 if (xgbe_is_tso(skb)) {
1479 /* TSO requires an extra descriptor if mss is different */
1480 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1481 context_desc = 1;
1482 packet->rdesc_count++;
1483 }
1484
1485 /* TSO requires an extra descriptor for TSO header */
1486 packet->rdesc_count++;
1487
1488 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1489 TSO_ENABLE, 1);
1490 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1491 CSUM_ENABLE, 1);
1492 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1493 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1494 CSUM_ENABLE, 1);
1495
1496 if (xgbe_is_vxlan(skb))
1497 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1498 VXLAN, 1);
1499
1500 if (skb_vlan_tag_present(skb)) {
1501 /* VLAN requires an extra descriptor if tag is different */
1502 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1503 /* We can share with the TSO context descriptor */
1504 if (!context_desc) {
1505 context_desc = 1;
1506 packet->rdesc_count++;
1507 }
1508
1509 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1510 VLAN_CTAG, 1);
1511 }
1512
1513 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1514 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1515 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1516 PTP, 1);
1517
1518 for (len = skb_headlen(skb); len;) {
1519 packet->rdesc_count++;
1520 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1521 }
1522
1523 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1524 frag = &skb_shinfo(skb)->frags[i];
1525 for (len = skb_frag_size(frag); len; ) {
1526 packet->rdesc_count++;
1527 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1528 }
1529 }
1530 }
1531
xgbe_open(struct net_device * netdev)1532 static int xgbe_open(struct net_device *netdev)
1533 {
1534 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1535 int ret;
1536
1537 /* Create the various names based on netdev name */
1538 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1539 netdev_name(netdev));
1540
1541 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1542 netdev_name(netdev));
1543
1544 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1545 netdev_name(netdev));
1546
1547 /* Create workqueues */
1548 pdata->dev_workqueue =
1549 create_singlethread_workqueue(netdev_name(netdev));
1550 if (!pdata->dev_workqueue) {
1551 netdev_err(netdev, "device workqueue creation failed\n");
1552 return -ENOMEM;
1553 }
1554
1555 pdata->an_workqueue =
1556 create_singlethread_workqueue(pdata->an_name);
1557 if (!pdata->an_workqueue) {
1558 netdev_err(netdev, "phy workqueue creation failed\n");
1559 ret = -ENOMEM;
1560 goto err_dev_wq;
1561 }
1562
1563 /* Reset the phy settings */
1564 ret = xgbe_phy_reset(pdata);
1565 if (ret)
1566 goto err_an_wq;
1567
1568 /* Enable the clocks */
1569 ret = clk_prepare_enable(pdata->sysclk);
1570 if (ret) {
1571 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1572 goto err_an_wq;
1573 }
1574
1575 ret = clk_prepare_enable(pdata->ptpclk);
1576 if (ret) {
1577 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1578 goto err_sysclk;
1579 }
1580
1581 INIT_WORK(&pdata->service_work, xgbe_service);
1582 INIT_WORK(&pdata->restart_work, xgbe_restart);
1583 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1584 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1585
1586 /* Initialize PTP timestamping and clock. */
1587 xgbe_init_ptp(pdata);
1588
1589 ret = xgbe_alloc_memory(pdata);
1590 if (ret)
1591 goto err_ptpclk;
1592
1593 ret = xgbe_start(pdata);
1594 if (ret)
1595 goto err_mem;
1596
1597 clear_bit(XGBE_DOWN, &pdata->dev_state);
1598
1599 return 0;
1600
1601 err_mem:
1602 xgbe_free_memory(pdata);
1603
1604 err_ptpclk:
1605 clk_disable_unprepare(pdata->ptpclk);
1606
1607 err_sysclk:
1608 clk_disable_unprepare(pdata->sysclk);
1609
1610 err_an_wq:
1611 destroy_workqueue(pdata->an_workqueue);
1612
1613 err_dev_wq:
1614 destroy_workqueue(pdata->dev_workqueue);
1615
1616 return ret;
1617 }
1618
xgbe_close(struct net_device * netdev)1619 static int xgbe_close(struct net_device *netdev)
1620 {
1621 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1622
1623 /* Stop the device */
1624 xgbe_stop(pdata);
1625
1626 xgbe_free_memory(pdata);
1627
1628 /* Disable the clocks */
1629 clk_disable_unprepare(pdata->ptpclk);
1630 clk_disable_unprepare(pdata->sysclk);
1631
1632 destroy_workqueue(pdata->an_workqueue);
1633
1634 destroy_workqueue(pdata->dev_workqueue);
1635
1636 set_bit(XGBE_DOWN, &pdata->dev_state);
1637
1638 return 0;
1639 }
1640
xgbe_xmit(struct sk_buff * skb,struct net_device * netdev)1641 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1642 {
1643 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1644 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1645 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1646 struct xgbe_channel *channel;
1647 struct xgbe_ring *ring;
1648 struct xgbe_packet_data *packet;
1649 struct netdev_queue *txq;
1650 netdev_tx_t ret;
1651
1652 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1653
1654 channel = pdata->channel[skb->queue_mapping];
1655 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1656 ring = channel->tx_ring;
1657 packet = &ring->packet_data;
1658
1659 ret = NETDEV_TX_OK;
1660
1661 if (skb->len == 0) {
1662 netif_err(pdata, tx_err, netdev,
1663 "empty skb received from stack\n");
1664 dev_kfree_skb_any(skb);
1665 goto tx_netdev_return;
1666 }
1667
1668 /* Calculate preliminary packet info */
1669 memset(packet, 0, sizeof(*packet));
1670 xgbe_packet_info(pdata, ring, skb, packet);
1671
1672 /* Check that there are enough descriptors available */
1673 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1674 if (ret)
1675 goto tx_netdev_return;
1676
1677 ret = xgbe_prep_tso(skb, packet);
1678 if (ret) {
1679 netif_err(pdata, tx_err, netdev,
1680 "error processing TSO packet\n");
1681 dev_kfree_skb_any(skb);
1682 goto tx_netdev_return;
1683 }
1684 xgbe_prep_vlan(skb, packet);
1685
1686 if (!desc_if->map_tx_skb(channel, skb)) {
1687 dev_kfree_skb_any(skb);
1688 goto tx_netdev_return;
1689 }
1690
1691 xgbe_prep_tx_tstamp(pdata, skb, packet);
1692
1693 /* Report on the actual number of bytes (to be) sent */
1694 netdev_tx_sent_queue(txq, packet->tx_bytes);
1695
1696 /* Configure required descriptor fields for transmission */
1697 hw_if->dev_xmit(channel);
1698
1699 if (netif_msg_pktdata(pdata))
1700 xgbe_print_pkt(netdev, skb, true);
1701
1702 /* Stop the queue in advance if there may not be enough descriptors */
1703 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1704
1705 ret = NETDEV_TX_OK;
1706
1707 tx_netdev_return:
1708 return ret;
1709 }
1710
xgbe_set_rx_mode(struct net_device * netdev)1711 static void xgbe_set_rx_mode(struct net_device *netdev)
1712 {
1713 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1714 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1715
1716 DBGPR("-->xgbe_set_rx_mode\n");
1717
1718 hw_if->config_rx_mode(pdata);
1719
1720 DBGPR("<--xgbe_set_rx_mode\n");
1721 }
1722
xgbe_set_mac_address(struct net_device * netdev,void * addr)1723 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1724 {
1725 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1726 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1727 struct sockaddr *saddr = addr;
1728
1729 DBGPR("-->xgbe_set_mac_address\n");
1730
1731 if (!is_valid_ether_addr(saddr->sa_data))
1732 return -EADDRNOTAVAIL;
1733
1734 eth_hw_addr_set(netdev, saddr->sa_data);
1735
1736 hw_if->set_mac_address(pdata, netdev->dev_addr);
1737
1738 DBGPR("<--xgbe_set_mac_address\n");
1739
1740 return 0;
1741 }
1742
xgbe_ioctl(struct net_device * netdev,struct ifreq * ifreq,int cmd)1743 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1744 {
1745 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1746 int ret;
1747
1748 switch (cmd) {
1749 case SIOCGHWTSTAMP:
1750 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1751 break;
1752
1753 case SIOCSHWTSTAMP:
1754 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1755 break;
1756
1757 default:
1758 ret = -EOPNOTSUPP;
1759 }
1760
1761 return ret;
1762 }
1763
xgbe_change_mtu(struct net_device * netdev,int mtu)1764 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1765 {
1766 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1767 int ret;
1768
1769 DBGPR("-->xgbe_change_mtu\n");
1770
1771 ret = xgbe_calc_rx_buf_size(netdev, mtu);
1772 if (ret < 0)
1773 return ret;
1774
1775 pdata->rx_buf_size = ret;
1776 WRITE_ONCE(netdev->mtu, mtu);
1777
1778 xgbe_restart_dev(pdata);
1779
1780 DBGPR("<--xgbe_change_mtu\n");
1781
1782 return 0;
1783 }
1784
xgbe_tx_timeout(struct net_device * netdev,unsigned int txqueue)1785 static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1786 {
1787 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1788
1789 netdev_warn(netdev, "tx timeout, device restarting\n");
1790 schedule_work(&pdata->restart_work);
1791 }
1792
xgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * s)1793 static void xgbe_get_stats64(struct net_device *netdev,
1794 struct rtnl_link_stats64 *s)
1795 {
1796 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1797 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1798
1799 DBGPR("-->%s\n", __func__);
1800
1801 pdata->hw_if.read_mmc_stats(pdata);
1802
1803 s->rx_packets = pstats->rxframecount_gb;
1804 s->rx_bytes = pstats->rxoctetcount_gb;
1805 s->rx_errors = pstats->rxframecount_gb -
1806 pstats->rxbroadcastframes_g -
1807 pstats->rxmulticastframes_g -
1808 pstats->rxunicastframes_g;
1809 s->multicast = pstats->rxmulticastframes_g;
1810 s->rx_length_errors = pstats->rxlengtherror;
1811 s->rx_crc_errors = pstats->rxcrcerror;
1812 s->rx_fifo_errors = pstats->rxfifooverflow;
1813
1814 s->tx_packets = pstats->txframecount_gb;
1815 s->tx_bytes = pstats->txoctetcount_gb;
1816 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1817 s->tx_dropped = netdev->stats.tx_dropped;
1818
1819 DBGPR("<--%s\n", __func__);
1820 }
1821
xgbe_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)1822 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1823 u16 vid)
1824 {
1825 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1826 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1827
1828 DBGPR("-->%s\n", __func__);
1829
1830 set_bit(vid, pdata->active_vlans);
1831 hw_if->update_vlan_hash_table(pdata);
1832
1833 DBGPR("<--%s\n", __func__);
1834
1835 return 0;
1836 }
1837
xgbe_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)1838 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1839 u16 vid)
1840 {
1841 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1842 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1843
1844 DBGPR("-->%s\n", __func__);
1845
1846 clear_bit(vid, pdata->active_vlans);
1847 hw_if->update_vlan_hash_table(pdata);
1848
1849 DBGPR("<--%s\n", __func__);
1850
1851 return 0;
1852 }
1853
1854 #ifdef CONFIG_NET_POLL_CONTROLLER
xgbe_poll_controller(struct net_device * netdev)1855 static void xgbe_poll_controller(struct net_device *netdev)
1856 {
1857 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1858 struct xgbe_channel *channel;
1859 unsigned int i;
1860
1861 DBGPR("-->xgbe_poll_controller\n");
1862
1863 if (pdata->per_channel_irq) {
1864 for (i = 0; i < pdata->channel_count; i++) {
1865 channel = pdata->channel[i];
1866 xgbe_dma_isr(channel->dma_irq, channel);
1867 }
1868 } else {
1869 disable_irq(pdata->dev_irq);
1870 xgbe_isr(pdata->dev_irq, pdata);
1871 enable_irq(pdata->dev_irq);
1872 }
1873
1874 DBGPR("<--xgbe_poll_controller\n");
1875 }
1876 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1877
xgbe_setup_tc(struct net_device * netdev,enum tc_setup_type type,void * type_data)1878 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
1879 void *type_data)
1880 {
1881 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1882 struct tc_mqprio_qopt *mqprio = type_data;
1883 u8 tc;
1884
1885 if (type != TC_SETUP_QDISC_MQPRIO)
1886 return -EOPNOTSUPP;
1887
1888 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
1889 tc = mqprio->num_tc;
1890
1891 if (tc > pdata->hw_feat.tc_cnt)
1892 return -EINVAL;
1893
1894 pdata->num_tcs = tc;
1895 pdata->hw_if.config_tc(pdata);
1896
1897 return 0;
1898 }
1899
xgbe_fix_features(struct net_device * netdev,netdev_features_t features)1900 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
1901 netdev_features_t features)
1902 {
1903 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1904 netdev_features_t vxlan_base;
1905
1906 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
1907
1908 if (!pdata->hw_feat.vxn)
1909 return features;
1910
1911 /* VXLAN CSUM requires VXLAN base */
1912 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
1913 !(features & NETIF_F_GSO_UDP_TUNNEL)) {
1914 netdev_notice(netdev,
1915 "forcing tx udp tunnel support\n");
1916 features |= NETIF_F_GSO_UDP_TUNNEL;
1917 }
1918
1919 /* Can't do one without doing the other */
1920 if ((features & vxlan_base) != vxlan_base) {
1921 netdev_notice(netdev,
1922 "forcing both tx and rx udp tunnel support\n");
1923 features |= vxlan_base;
1924 }
1925
1926 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
1927 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
1928 netdev_notice(netdev,
1929 "forcing tx udp tunnel checksumming on\n");
1930 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1931 }
1932 } else {
1933 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
1934 netdev_notice(netdev,
1935 "forcing tx udp tunnel checksumming off\n");
1936 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
1937 }
1938 }
1939
1940 return features;
1941 }
1942
xgbe_set_features(struct net_device * netdev,netdev_features_t features)1943 static int xgbe_set_features(struct net_device *netdev,
1944 netdev_features_t features)
1945 {
1946 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1947 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1948 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1949 int ret = 0;
1950
1951 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1952 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1953 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1954 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1955
1956 if ((features & NETIF_F_RXHASH) && !rxhash)
1957 ret = hw_if->enable_rss(pdata);
1958 else if (!(features & NETIF_F_RXHASH) && rxhash)
1959 ret = hw_if->disable_rss(pdata);
1960 if (ret)
1961 return ret;
1962
1963 if ((features & NETIF_F_RXCSUM) && !rxcsum) {
1964 hw_if->enable_sph(pdata);
1965 hw_if->enable_vxlan(pdata);
1966 hw_if->enable_rx_csum(pdata);
1967 schedule_work(&pdata->restart_work);
1968 } else if (!(features & NETIF_F_RXCSUM) && rxcsum) {
1969 hw_if->disable_sph(pdata);
1970 hw_if->disable_vxlan(pdata);
1971 hw_if->disable_rx_csum(pdata);
1972 schedule_work(&pdata->restart_work);
1973 }
1974
1975 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1976 hw_if->enable_rx_vlan_stripping(pdata);
1977 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1978 hw_if->disable_rx_vlan_stripping(pdata);
1979
1980 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1981 hw_if->enable_rx_vlan_filtering(pdata);
1982 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1983 hw_if->disable_rx_vlan_filtering(pdata);
1984
1985 pdata->netdev_features = features;
1986
1987 DBGPR("<--xgbe_set_features\n");
1988
1989 return 0;
1990 }
1991
xgbe_features_check(struct sk_buff * skb,struct net_device * netdev,netdev_features_t features)1992 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
1993 struct net_device *netdev,
1994 netdev_features_t features)
1995 {
1996 features = vlan_features_check(skb, features);
1997 features = vxlan_features_check(skb, features);
1998
1999 return features;
2000 }
2001
2002 static const struct net_device_ops xgbe_netdev_ops = {
2003 .ndo_open = xgbe_open,
2004 .ndo_stop = xgbe_close,
2005 .ndo_start_xmit = xgbe_xmit,
2006 .ndo_set_rx_mode = xgbe_set_rx_mode,
2007 .ndo_set_mac_address = xgbe_set_mac_address,
2008 .ndo_validate_addr = eth_validate_addr,
2009 .ndo_eth_ioctl = xgbe_ioctl,
2010 .ndo_change_mtu = xgbe_change_mtu,
2011 .ndo_tx_timeout = xgbe_tx_timeout,
2012 .ndo_get_stats64 = xgbe_get_stats64,
2013 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
2014 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
2015 #ifdef CONFIG_NET_POLL_CONTROLLER
2016 .ndo_poll_controller = xgbe_poll_controller,
2017 #endif
2018 .ndo_setup_tc = xgbe_setup_tc,
2019 .ndo_fix_features = xgbe_fix_features,
2020 .ndo_set_features = xgbe_set_features,
2021 .ndo_features_check = xgbe_features_check,
2022 };
2023
xgbe_get_netdev_ops(void)2024 const struct net_device_ops *xgbe_get_netdev_ops(void)
2025 {
2026 return &xgbe_netdev_ops;
2027 }
2028
xgbe_rx_refresh(struct xgbe_channel * channel)2029 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2030 {
2031 struct xgbe_prv_data *pdata = channel->pdata;
2032 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2033 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2034 struct xgbe_ring *ring = channel->rx_ring;
2035 struct xgbe_ring_data *rdata;
2036
2037 while (ring->dirty != ring->cur) {
2038 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2039
2040 /* Reset rdata values */
2041 desc_if->unmap_rdata(pdata, rdata);
2042
2043 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2044 break;
2045
2046 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2047
2048 ring->dirty++;
2049 }
2050
2051 /* Make sure everything is written before the register write */
2052 wmb();
2053
2054 /* Update the Rx Tail Pointer Register with address of
2055 * the last cleaned entry */
2056 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2057 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2058 lower_32_bits(rdata->rdesc_dma));
2059 }
2060
xgbe_create_skb(struct xgbe_prv_data * pdata,struct napi_struct * napi,struct xgbe_ring_data * rdata,unsigned int len)2061 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2062 struct napi_struct *napi,
2063 struct xgbe_ring_data *rdata,
2064 unsigned int len)
2065 {
2066 struct sk_buff *skb;
2067 u8 *packet;
2068
2069 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2070 if (!skb)
2071 return NULL;
2072
2073 /* Pull in the header buffer which may contain just the header
2074 * or the header plus data
2075 */
2076 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2077 rdata->rx.hdr.dma_off,
2078 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2079
2080 packet = page_address(rdata->rx.hdr.pa.pages) +
2081 rdata->rx.hdr.pa.pages_offset;
2082 skb_copy_to_linear_data(skb, packet, len);
2083 skb_put(skb, len);
2084
2085 return skb;
2086 }
2087
xgbe_rx_buf1_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet)2088 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2089 struct xgbe_packet_data *packet)
2090 {
2091 /* Always zero if not the first descriptor */
2092 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2093 return 0;
2094
2095 /* First descriptor with split header, return header length */
2096 if (rdata->rx.hdr_len)
2097 return rdata->rx.hdr_len;
2098
2099 /* First descriptor but not the last descriptor and no split header,
2100 * so the full buffer was used
2101 */
2102 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2103 return rdata->rx.hdr.dma_len;
2104
2105 /* First descriptor and last descriptor and no split header, so
2106 * calculate how much of the buffer was used
2107 */
2108 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2109 }
2110
xgbe_rx_buf2_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet,unsigned int len)2111 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2112 struct xgbe_packet_data *packet,
2113 unsigned int len)
2114 {
2115 /* Always the full buffer if not the last descriptor */
2116 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2117 return rdata->rx.buf.dma_len;
2118
2119 /* Last descriptor so calculate how much of the buffer was used
2120 * for the last bit of data
2121 */
2122 return rdata->rx.len - len;
2123 }
2124
xgbe_tx_poll(struct xgbe_channel * channel)2125 static int xgbe_tx_poll(struct xgbe_channel *channel)
2126 {
2127 struct xgbe_prv_data *pdata = channel->pdata;
2128 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2129 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2130 struct xgbe_ring *ring = channel->tx_ring;
2131 struct xgbe_ring_data *rdata;
2132 struct xgbe_ring_desc *rdesc;
2133 struct net_device *netdev = pdata->netdev;
2134 struct netdev_queue *txq;
2135 int processed = 0;
2136 unsigned int tx_packets = 0, tx_bytes = 0;
2137 unsigned int cur;
2138
2139 DBGPR("-->xgbe_tx_poll\n");
2140
2141 /* Nothing to do if there isn't a Tx ring for this channel */
2142 if (!ring)
2143 return 0;
2144
2145 cur = ring->cur;
2146
2147 /* Be sure we get ring->cur before accessing descriptor data */
2148 smp_rmb();
2149
2150 txq = netdev_get_tx_queue(netdev, channel->queue_index);
2151
2152 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2153 (ring->dirty != cur)) {
2154 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2155 rdesc = rdata->rdesc;
2156
2157 if (!hw_if->tx_complete(rdesc))
2158 break;
2159
2160 /* Make sure descriptor fields are read after reading the OWN
2161 * bit */
2162 dma_rmb();
2163
2164 if (netif_msg_tx_done(pdata))
2165 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2166
2167 if (hw_if->is_last_desc(rdesc)) {
2168 tx_packets += rdata->tx.packets;
2169 tx_bytes += rdata->tx.bytes;
2170 }
2171
2172 /* Free the SKB and reset the descriptor for re-use */
2173 desc_if->unmap_rdata(pdata, rdata);
2174 hw_if->tx_desc_reset(rdata);
2175
2176 processed++;
2177 ring->dirty++;
2178 }
2179
2180 if (!processed)
2181 return 0;
2182
2183 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2184
2185 if ((ring->tx.queue_stopped == 1) &&
2186 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2187 ring->tx.queue_stopped = 0;
2188 netif_tx_wake_queue(txq);
2189 }
2190
2191 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2192
2193 return processed;
2194 }
2195
xgbe_rx_poll(struct xgbe_channel * channel,int budget)2196 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2197 {
2198 struct xgbe_prv_data *pdata = channel->pdata;
2199 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2200 struct xgbe_ring *ring = channel->rx_ring;
2201 struct xgbe_ring_data *rdata;
2202 struct xgbe_packet_data *packet;
2203 struct net_device *netdev = pdata->netdev;
2204 struct napi_struct *napi;
2205 struct sk_buff *skb;
2206 struct skb_shared_hwtstamps *hwtstamps;
2207 unsigned int last, error, context_next, context;
2208 unsigned int len, buf1_len, buf2_len, max_len;
2209 unsigned int received = 0;
2210 int packet_count = 0;
2211
2212 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2213
2214 /* Nothing to do if there isn't a Rx ring for this channel */
2215 if (!ring)
2216 return 0;
2217
2218 last = 0;
2219 context_next = 0;
2220
2221 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2222
2223 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2224 packet = &ring->packet_data;
2225 while (packet_count < budget) {
2226 DBGPR(" cur = %d\n", ring->cur);
2227
2228 /* First time in loop see if we need to restore state */
2229 if (!received && rdata->state_saved) {
2230 skb = rdata->state.skb;
2231 error = rdata->state.error;
2232 len = rdata->state.len;
2233 } else {
2234 memset(packet, 0, sizeof(*packet));
2235 skb = NULL;
2236 error = 0;
2237 len = 0;
2238 }
2239
2240 read_again:
2241 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2242
2243 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2244 xgbe_rx_refresh(channel);
2245
2246 if (hw_if->dev_read(channel))
2247 break;
2248
2249 received++;
2250 ring->cur++;
2251
2252 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2253 LAST);
2254 context_next = XGMAC_GET_BITS(packet->attributes,
2255 RX_PACKET_ATTRIBUTES,
2256 CONTEXT_NEXT);
2257 context = XGMAC_GET_BITS(packet->attributes,
2258 RX_PACKET_ATTRIBUTES,
2259 CONTEXT);
2260
2261 /* Earlier error, just drain the remaining data */
2262 if ((!last || context_next) && error)
2263 goto read_again;
2264
2265 if (error || packet->errors) {
2266 if (packet->errors)
2267 netif_err(pdata, rx_err, netdev,
2268 "error in received packet\n");
2269 dev_kfree_skb(skb);
2270 goto next_packet;
2271 }
2272
2273 if (!context) {
2274 /* Get the data length in the descriptor buffers */
2275 buf1_len = xgbe_rx_buf1_len(rdata, packet);
2276 len += buf1_len;
2277 buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2278 len += buf2_len;
2279
2280 if (buf2_len > rdata->rx.buf.dma_len) {
2281 /* Hardware inconsistency within the descriptors
2282 * that has resulted in a length underflow.
2283 */
2284 error = 1;
2285 goto skip_data;
2286 }
2287
2288 if (!skb) {
2289 skb = xgbe_create_skb(pdata, napi, rdata,
2290 buf1_len);
2291 if (!skb) {
2292 error = 1;
2293 goto skip_data;
2294 }
2295 }
2296
2297 if (buf2_len) {
2298 dma_sync_single_range_for_cpu(pdata->dev,
2299 rdata->rx.buf.dma_base,
2300 rdata->rx.buf.dma_off,
2301 rdata->rx.buf.dma_len,
2302 DMA_FROM_DEVICE);
2303
2304 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2305 rdata->rx.buf.pa.pages,
2306 rdata->rx.buf.pa.pages_offset,
2307 buf2_len,
2308 rdata->rx.buf.dma_len);
2309 rdata->rx.buf.pa.pages = NULL;
2310 }
2311 }
2312
2313 skip_data:
2314 if (!last || context_next)
2315 goto read_again;
2316
2317 if (!skb || error) {
2318 dev_kfree_skb(skb);
2319 goto next_packet;
2320 }
2321
2322 /* Be sure we don't exceed the configured MTU */
2323 max_len = netdev->mtu + ETH_HLEN;
2324 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2325 (skb->protocol == htons(ETH_P_8021Q)))
2326 max_len += VLAN_HLEN;
2327
2328 if (skb->len > max_len) {
2329 netif_err(pdata, rx_err, netdev,
2330 "packet length exceeds configured MTU\n");
2331 dev_kfree_skb(skb);
2332 goto next_packet;
2333 }
2334
2335 if (netif_msg_pktdata(pdata))
2336 xgbe_print_pkt(netdev, skb, false);
2337
2338 skb_checksum_none_assert(skb);
2339 if (XGMAC_GET_BITS(packet->attributes,
2340 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2341 skb->ip_summed = CHECKSUM_UNNECESSARY;
2342
2343 if (XGMAC_GET_BITS(packet->attributes,
2344 RX_PACKET_ATTRIBUTES, TNP)) {
2345 skb->encapsulation = 1;
2346
2347 if (XGMAC_GET_BITS(packet->attributes,
2348 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2349 skb->csum_level = 1;
2350 }
2351
2352 if (XGMAC_GET_BITS(packet->attributes,
2353 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2354 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2355 packet->vlan_ctag);
2356
2357 if (XGMAC_GET_BITS(packet->attributes,
2358 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2359 hwtstamps = skb_hwtstamps(skb);
2360 hwtstamps->hwtstamp = ns_to_ktime(packet->rx_tstamp);
2361 }
2362
2363 if (XGMAC_GET_BITS(packet->attributes,
2364 RX_PACKET_ATTRIBUTES, RSS_HASH))
2365 skb_set_hash(skb, packet->rss_hash,
2366 packet->rss_hash_type);
2367
2368 skb->dev = netdev;
2369 skb->protocol = eth_type_trans(skb, netdev);
2370 skb_record_rx_queue(skb, channel->queue_index);
2371
2372 napi_gro_receive(napi, skb);
2373
2374 next_packet:
2375 packet_count++;
2376 }
2377
2378 /* Check if we need to save state before leaving */
2379 if (received && (!last || context_next)) {
2380 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2381 rdata->state_saved = 1;
2382 rdata->state.skb = skb;
2383 rdata->state.len = len;
2384 rdata->state.error = error;
2385 }
2386
2387 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2388
2389 return packet_count;
2390 }
2391
xgbe_one_poll(struct napi_struct * napi,int budget)2392 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2393 {
2394 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2395 napi);
2396 struct xgbe_prv_data *pdata = channel->pdata;
2397 int processed = 0;
2398
2399 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2400
2401 /* Cleanup Tx ring first */
2402 xgbe_tx_poll(channel);
2403
2404 /* Process Rx ring next */
2405 processed = xgbe_rx_poll(channel, budget);
2406
2407 /* If we processed everything, we are done */
2408 if ((processed < budget) && napi_complete_done(napi, processed)) {
2409 /* Enable Tx and Rx interrupts */
2410 if (pdata->channel_irq_mode)
2411 xgbe_enable_rx_tx_int(pdata, channel);
2412 else
2413 enable_irq(channel->dma_irq);
2414 }
2415
2416 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2417
2418 return processed;
2419 }
2420
xgbe_all_poll(struct napi_struct * napi,int budget)2421 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2422 {
2423 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2424 napi);
2425 struct xgbe_channel *channel;
2426 int ring_budget;
2427 int processed, last_processed;
2428 unsigned int i;
2429
2430 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2431
2432 processed = 0;
2433 ring_budget = budget / pdata->rx_ring_count;
2434 do {
2435 last_processed = processed;
2436
2437 for (i = 0; i < pdata->channel_count; i++) {
2438 channel = pdata->channel[i];
2439
2440 /* Cleanup Tx ring first */
2441 xgbe_tx_poll(channel);
2442
2443 /* Process Rx ring next */
2444 if (ring_budget > (budget - processed))
2445 ring_budget = budget - processed;
2446 processed += xgbe_rx_poll(channel, ring_budget);
2447 }
2448 } while ((processed < budget) && (processed != last_processed));
2449
2450 /* If we processed everything, we are done */
2451 if ((processed < budget) && napi_complete_done(napi, processed)) {
2452 /* Enable Tx and Rx interrupts */
2453 xgbe_enable_rx_tx_ints(pdata);
2454 }
2455
2456 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2457
2458 return processed;
2459 }
2460
xgbe_dump_tx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx,unsigned int count,unsigned int flag)2461 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2462 unsigned int idx, unsigned int count, unsigned int flag)
2463 {
2464 struct xgbe_ring_data *rdata;
2465 struct xgbe_ring_desc *rdesc;
2466
2467 while (count--) {
2468 rdata = XGBE_GET_DESC_DATA(ring, idx);
2469 rdesc = rdata->rdesc;
2470 netdev_dbg(pdata->netdev,
2471 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2472 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2473 le32_to_cpu(rdesc->desc0),
2474 le32_to_cpu(rdesc->desc1),
2475 le32_to_cpu(rdesc->desc2),
2476 le32_to_cpu(rdesc->desc3));
2477 idx++;
2478 }
2479 }
2480
xgbe_dump_rx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx)2481 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2482 unsigned int idx)
2483 {
2484 struct xgbe_ring_data *rdata;
2485 struct xgbe_ring_desc *rdesc;
2486
2487 rdata = XGBE_GET_DESC_DATA(ring, idx);
2488 rdesc = rdata->rdesc;
2489 netdev_dbg(pdata->netdev,
2490 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2491 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2492 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2493 }
2494
xgbe_print_pkt(struct net_device * netdev,struct sk_buff * skb,bool tx_rx)2495 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2496 {
2497 struct ethhdr *eth = (struct ethhdr *)skb->data;
2498 unsigned char buffer[128];
2499 unsigned int i;
2500
2501 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2502
2503 netdev_dbg(netdev, "%s packet of %d bytes\n",
2504 (tx_rx ? "TX" : "RX"), skb->len);
2505
2506 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2507 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2508 netdev_dbg(netdev, "Protocol: %#06x\n", ntohs(eth->h_proto));
2509
2510 for (i = 0; i < skb->len; i += 32) {
2511 unsigned int len = min(skb->len - i, 32U);
2512
2513 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2514 buffer, sizeof(buffer), false);
2515 netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
2516 }
2517
2518 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2519 }
2520