1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_wa.h"
7
8 #include <drm/drm_managed.h>
9 #include <kunit/visibility.h>
10 #include <linux/compiler_types.h>
11 #include <linux/fault-inject.h>
12
13 #include <generated/xe_wa_oob.h>
14
15 #include "regs/xe_engine_regs.h"
16 #include "regs/xe_gt_regs.h"
17 #include "regs/xe_regs.h"
18 #include "xe_device_types.h"
19 #include "xe_force_wake.h"
20 #include "xe_gt.h"
21 #include "xe_hw_engine_types.h"
22 #include "xe_mmio.h"
23 #include "xe_platform_types.h"
24 #include "xe_rtp.h"
25 #include "xe_sriov.h"
26 #include "xe_step.h"
27
28 /**
29 * DOC: Hardware workarounds
30 *
31 * Hardware workarounds are register programming documented to be executed in
32 * the driver that fall outside of the normal programming sequences for a
33 * platform. There are some basic categories of workarounds, depending on
34 * how/when they are applied:
35 *
36 * - LRC workarounds: workarounds that touch registers that are
37 * saved/restored to/from the HW context image. The list is emitted (via Load
38 * Register Immediate commands) once when initializing the device and saved in
39 * the default context. That default context is then used on every context
40 * creation to have a "primed golden context", i.e. a context image that
41 * already contains the changes needed to all the registers.
42 *
43 * - Engine workarounds: the list of these WAs is applied whenever the specific
44 * engine is reset. It's also possible that a set of engine classes share a
45 * common power domain and they are reset together. This happens on some
46 * platforms with render and compute engines. In this case (at least) one of
47 * them need to keeep the workaround programming: the approach taken in the
48 * driver is to tie those workarounds to the first compute/render engine that
49 * is registered. When executing with GuC submission, engine resets are
50 * outside of kernel driver control, hence the list of registers involved in
51 * written once, on engine initialization, and then passed to GuC, that
52 * saves/restores their values before/after the reset takes place. See
53 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
54 *
55 * - GT workarounds: the list of these WAs is applied whenever these registers
56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
57 *
58 * - Register whitelist: some workarounds need to be implemented in userspace,
59 * but need to touch privileged registers. The whitelist in the kernel
60 * instructs the hardware to allow the access to happen. From the kernel side,
61 * this is just a special case of a MMIO workaround (as we write the list of
62 * these to/be-whitelisted registers to some special HW registers).
63 *
64 * - Workaround batchbuffers: buffers that get executed automatically by the
65 * hardware on every HW context restore. These buffers are created and
66 * programmed in the default context so the hardware always go through those
67 * programming sequences when switching contexts. The support for workaround
68 * batchbuffers is enabled these hardware mechanisms:
69 *
70 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
71 * context, pointing the hardware to jump to that location when that offset
72 * is reached in the context restore. Workaround batchbuffer in the driver
73 * currently uses this mechanism for all platforms.
74 *
75 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
76 * pointing the hardware to a buffer to continue executing after the
77 * engine registers are restored in a context restore sequence. This is
78 * currently not used in the driver.
79 *
80 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
81 * a central place. Those are peppered around the rest of the code, as needed.
82 * Workarounds related to the display IP are the main example.
83 *
84 * .. [1] Technically, some registers are powercontext saved & restored, so they
85 * survive a suspend/resume. In practice, writing them again is not too
86 * costly and simplifies things, so it's the approach taken in the driver.
87 *
88 * .. note::
89 * Hardware workarounds in xe work the same way as in i915, with the
90 * difference of how they are maintained in the code. In xe it uses the
91 * xe_rtp infrastructure so the workarounds can be kept in tables, following
92 * a more declarative approach rather than procedural.
93 */
94
95 #undef XE_REG_MCR
96 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
97
98 __diag_push();
99 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
100
101 static const struct xe_rtp_entry_sr gt_was[] = {
102 { XE_RTP_NAME("14011060649"),
103 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
104 ENGINE_CLASS(VIDEO_DECODE),
105 FUNC(xe_rtp_match_even_instance)),
106 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
107 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
108 },
109 { XE_RTP_NAME("14011059788"),
110 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
111 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
112 },
113 { XE_RTP_NAME("14015795083"),
114 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
115 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
116 },
117
118 /* DG1 */
119
120 { XE_RTP_NAME("1409420604"),
121 XE_RTP_RULES(PLATFORM(DG1)),
122 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
123 },
124 { XE_RTP_NAME("1408615072"),
125 XE_RTP_RULES(PLATFORM(DG1)),
126 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
127 },
128
129 /* DG2 */
130
131 { XE_RTP_NAME("22010523718"),
132 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
133 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
134 },
135 { XE_RTP_NAME("14011006942"),
136 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
137 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
138 },
139 { XE_RTP_NAME("14014830051"),
140 XE_RTP_RULES(PLATFORM(DG2)),
141 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
142 },
143 { XE_RTP_NAME("18018781329"),
144 XE_RTP_RULES(PLATFORM(DG2)),
145 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
146 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
147 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
148 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
149 },
150 { XE_RTP_NAME("1509235366"),
151 XE_RTP_RULES(PLATFORM(DG2)),
152 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
153 INVALIDATION_BROADCAST_MODE_DIS |
154 GLOBAL_INVALIDATION_MODE))
155 },
156
157 /* PVC */
158
159 { XE_RTP_NAME("18018781329"),
160 XE_RTP_RULES(PLATFORM(PVC)),
161 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
162 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
163 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
164 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
165 },
166 { XE_RTP_NAME("16016694945"),
167 XE_RTP_RULES(PLATFORM(PVC)),
168 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
169 },
170
171 /* Xe_LPG */
172
173 { XE_RTP_NAME("14015795083"),
174 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
175 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
176 },
177 { XE_RTP_NAME("14018575942"),
178 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
179 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
180 },
181 { XE_RTP_NAME("22016670082"),
182 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
183 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
184 },
185
186 /* Xe_LPM+ */
187
188 { XE_RTP_NAME("16021867713"),
189 XE_RTP_RULES(MEDIA_VERSION(1300),
190 ENGINE_CLASS(VIDEO_DECODE)),
191 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
192 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
193 },
194 { XE_RTP_NAME("22016670082"),
195 XE_RTP_RULES(MEDIA_VERSION(1300)),
196 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
197 },
198
199 /* Xe2_LPG */
200
201 { XE_RTP_NAME("16020975621"),
202 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
203 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
204 },
205 { XE_RTP_NAME("14018157293"),
206 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
207 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
208 SET(XEHPC_L3CLOS_MASK(1), ~0),
209 SET(XEHPC_L3CLOS_MASK(2), ~0),
210 SET(XEHPC_L3CLOS_MASK(3), ~0))
211 },
212
213 /* Xe2_LPM */
214
215 { XE_RTP_NAME("14017421178"),
216 XE_RTP_RULES(MEDIA_VERSION(2000),
217 ENGINE_CLASS(VIDEO_DECODE)),
218 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
219 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
220 },
221 { XE_RTP_NAME("16021867713"),
222 XE_RTP_RULES(MEDIA_VERSION(2000),
223 ENGINE_CLASS(VIDEO_DECODE)),
224 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
225 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
226 },
227 { XE_RTP_NAME("14019449301"),
228 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
229 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
230 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
231 },
232
233 /* Xe2_HPM */
234
235 { XE_RTP_NAME("16021867713"),
236 XE_RTP_RULES(MEDIA_VERSION(1301),
237 ENGINE_CLASS(VIDEO_DECODE)),
238 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
239 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
240 },
241 { XE_RTP_NAME("14020316580"),
242 XE_RTP_RULES(MEDIA_VERSION(1301)),
243 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
244 VDN_HCP_POWERGATE_ENABLE(0) |
245 VDN_MFXVDENC_POWERGATE_ENABLE(0) |
246 VDN_HCP_POWERGATE_ENABLE(2) |
247 VDN_MFXVDENC_POWERGATE_ENABLE(2))),
248 },
249 { XE_RTP_NAME("14019449301"),
250 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
251 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
252 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
253 },
254
255 /* Xe3_LPG */
256
257 { XE_RTP_NAME("14021871409"),
258 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
259 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
260 },
261
262 /* Xe3_LPM */
263
264 { XE_RTP_NAME("16021867713"),
265 XE_RTP_RULES(MEDIA_VERSION(3000),
266 ENGINE_CLASS(VIDEO_DECODE)),
267 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
268 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
269 },
270 { XE_RTP_NAME("16021865536"),
271 XE_RTP_RULES(MEDIA_VERSION(3000),
272 ENGINE_CLASS(VIDEO_DECODE)),
273 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
274 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
275 },
276 { XE_RTP_NAME("14021486841"),
277 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
278 ENGINE_CLASS(VIDEO_DECODE)),
279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
281 },
282 };
283
284 static const struct xe_rtp_entry_sr engine_was[] = {
285 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
286 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
287 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
288 FF_TESSELATION_DOP_GATE_DISABLE))
289 },
290 { XE_RTP_NAME("1409804808"),
291 XE_RTP_RULES(GRAPHICS_VERSION(1200),
292 ENGINE_CLASS(RENDER),
293 IS_INTEGRATED),
294 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
295 },
296 { XE_RTP_NAME("14010229206, 1409085225"),
297 XE_RTP_RULES(GRAPHICS_VERSION(1200),
298 ENGINE_CLASS(RENDER),
299 IS_INTEGRATED),
300 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
301 },
302 { XE_RTP_NAME("1606931601"),
303 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
304 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
305 },
306 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
307 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
308 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
309 FF_DOP_CLOCK_GATE_DISABLE))
310 },
311 { XE_RTP_NAME("1406941453"),
312 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
313 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
314 },
315 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
316 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
317 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
318 FFSC_PERCTX_PREEMPT_CTRL))
319 },
320
321 /* TGL */
322
323 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
324 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
325 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
326 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
327 RC_SEMA_IDLE_MSG_DISABLE))
328 },
329
330 /* RKL */
331
332 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
333 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
334 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
335 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
336 RC_SEMA_IDLE_MSG_DISABLE))
337 },
338
339 /* ADL-P */
340
341 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
342 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
343 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
344 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
345 RC_SEMA_IDLE_MSG_DISABLE))
346 },
347
348 /* DG2 */
349
350 { XE_RTP_NAME("22013037850"),
351 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
352 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
353 DISABLE_128B_EVICTION_COMMAND_UDW))
354 },
355 { XE_RTP_NAME("22014226127"),
356 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
357 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
358 },
359 { XE_RTP_NAME("18017747507"),
360 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
361 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
362 POLYGON_TRIFAN_LINELOOP_DISABLE))
363 },
364 { XE_RTP_NAME("22012826095, 22013059131"),
365 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
366 FUNC(xe_rtp_match_first_render_or_compute)),
367 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
368 MAXREQS_PER_BANK,
369 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
370 },
371 { XE_RTP_NAME("22013059131"),
372 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
373 FUNC(xe_rtp_match_first_render_or_compute)),
374 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
375 },
376 { XE_RTP_NAME("14015227452"),
377 XE_RTP_RULES(PLATFORM(DG2),
378 FUNC(xe_rtp_match_first_render_or_compute)),
379 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
380 },
381 { XE_RTP_NAME("18028616096"),
382 XE_RTP_RULES(PLATFORM(DG2),
383 FUNC(xe_rtp_match_first_render_or_compute)),
384 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
385 },
386 { XE_RTP_NAME("22015475538"),
387 XE_RTP_RULES(PLATFORM(DG2),
388 FUNC(xe_rtp_match_first_render_or_compute)),
389 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
390 },
391 { XE_RTP_NAME("22012654132"),
392 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
393 FUNC(xe_rtp_match_first_render_or_compute)),
394 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
395 /*
396 * Register can't be read back for verification on
397 * DG2 due to Wa_14012342262
398 */
399 .read_mask = 0))
400 },
401 { XE_RTP_NAME("1509727124"),
402 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
403 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
404 },
405 { XE_RTP_NAME("22012856258"),
406 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
407 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
408 },
409 { XE_RTP_NAME("22010960976, 14013347512"),
410 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
411 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
412 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
413 },
414 { XE_RTP_NAME("14015150844"),
415 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
416 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
417 XE_RTP_NOCHECK))
418 },
419
420 /* PVC */
421
422 { XE_RTP_NAME("22014226127"),
423 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
424 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
425 },
426 { XE_RTP_NAME("14015227452"),
427 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
428 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
429 },
430 { XE_RTP_NAME("18020744125"),
431 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
432 ENGINE_CLASS(COMPUTE)),
433 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
434 },
435 { XE_RTP_NAME("14014999345"),
436 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
437 GRAPHICS_STEP(B0, C0)),
438 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
439 },
440
441 /* Xe_LPG */
442
443 { XE_RTP_NAME("14017856879"),
444 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
445 FUNC(xe_rtp_match_first_render_or_compute)),
446 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
447 },
448 { XE_RTP_NAME("14015150844"),
449 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
450 FUNC(xe_rtp_match_first_render_or_compute)),
451 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
452 XE_RTP_NOCHECK))
453 },
454 { XE_RTP_NAME("14020495402"),
455 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
456 FUNC(xe_rtp_match_first_render_or_compute)),
457 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
458 },
459
460 /* Xe2_LPG */
461
462 { XE_RTP_NAME("18032247524"),
463 XE_RTP_RULES(GRAPHICS_VERSION(2004),
464 FUNC(xe_rtp_match_first_render_or_compute)),
465 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
466 },
467 { XE_RTP_NAME("16018712365"),
468 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
469 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
470 },
471 { XE_RTP_NAME("14018957109"),
472 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
473 FUNC(xe_rtp_match_first_render_or_compute)),
474 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
475 },
476 { XE_RTP_NAME("14020338487"),
477 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
478 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
479 },
480 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
481 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
482 FUNC(xe_rtp_match_first_render_or_compute)),
483 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
484 },
485 { XE_RTP_NAME("14019322943"),
486 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
487 FUNC(xe_rtp_match_first_render_or_compute)),
488 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
489 },
490 { XE_RTP_NAME("14018471104"),
491 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
492 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
493 },
494 { XE_RTP_NAME("16018737384"),
495 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
496 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
497 },
498 /*
499 * These two workarounds are the same, just applying to different
500 * engines. Although Wa_18032095049 (for the RCS) isn't required on
501 * all steppings, disabling these reports has no impact for our
502 * driver or the GuC, so we go ahead and treat it the same as
503 * Wa_16021639441 which does apply to all steppings.
504 */
505 { XE_RTP_NAME("18032095049, 16021639441"),
506 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
507 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
508 GHWSP_CSB_REPORT_DIS |
509 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
510 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
511 },
512 { XE_RTP_NAME("16018610683"),
513 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
514 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
515 },
516 { XE_RTP_NAME("14021402888"),
517 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
518 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
519 },
520
521 /* Xe2_HPG */
522
523 { XE_RTP_NAME("16018712365"),
524 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
525 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
526 },
527 { XE_RTP_NAME("16018737384"),
528 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
529 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
530 },
531 { XE_RTP_NAME("14019988906"),
532 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
533 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
534 },
535 { XE_RTP_NAME("14019877138"),
536 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
537 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
538 },
539 { XE_RTP_NAME("14020338487"),
540 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
541 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
542 },
543 { XE_RTP_NAME("18032247524"),
544 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
545 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
546 },
547 { XE_RTP_NAME("14018471104"),
548 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
549 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
550 },
551 /*
552 * Although this workaround isn't required for the RCS, disabling these
553 * reports has no impact for our driver or the GuC, so we go ahead and
554 * apply this to all engines for simplicity.
555 */
556 { XE_RTP_NAME("16021639441"),
557 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
558 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
559 GHWSP_CSB_REPORT_DIS |
560 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
561 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
562 },
563 { XE_RTP_NAME("14019811474"),
564 XE_RTP_RULES(GRAPHICS_VERSION(2001),
565 FUNC(xe_rtp_match_first_render_or_compute)),
566 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
567 },
568 { XE_RTP_NAME("14021402888"),
569 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
570 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
571 },
572 { XE_RTP_NAME("14021821874"),
573 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
574 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
575 },
576
577 /* Xe2_LPM */
578
579 { XE_RTP_NAME("16021639441"),
580 XE_RTP_RULES(MEDIA_VERSION(2000)),
581 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
582 GHWSP_CSB_REPORT_DIS |
583 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
584 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
585 },
586
587 /* Xe2_HPM */
588
589 { XE_RTP_NAME("16021639441"),
590 XE_RTP_RULES(MEDIA_VERSION(1301)),
591 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
592 GHWSP_CSB_REPORT_DIS |
593 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
594 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
595 },
596
597 /* Xe3_LPG */
598
599 { XE_RTP_NAME("14021402888"),
600 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
601 FUNC(xe_rtp_match_first_render_or_compute)),
602 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
603 },
604 { XE_RTP_NAME("18034896535"),
605 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
606 FUNC(xe_rtp_match_first_render_or_compute)),
607 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
608 },
609 { XE_RTP_NAME("16024792527"),
610 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
611 FUNC(xe_rtp_match_first_render_or_compute)),
612 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
613 SMP_FORCE_128B_OVERFETCH))
614 },
615 { XE_RTP_NAME("14023061436"),
616 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
617 FUNC(xe_rtp_match_first_render_or_compute)),
618 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
619 },
620 { XE_RTP_NAME("13012615864"),
621 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
622 FUNC(xe_rtp_match_first_render_or_compute)),
623 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
624 },
625 { XE_RTP_NAME("16023105232"),
626 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
627 GRAPHICS_VERSION_RANGE(2001, 3001)),
628 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
629 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
630 },
631 };
632
633 static const struct xe_rtp_entry_sr lrc_was[] = {
634 { XE_RTP_NAME("16011163337"),
635 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
636 /* read verification is ignored due to 1608008084. */
637 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
638 FF_MODE2_GS_TIMER_MASK,
639 FF_MODE2_GS_TIMER_224))
640 },
641 { XE_RTP_NAME("1604555607"),
642 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
643 /* read verification is ignored due to 1608008084. */
644 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
645 FF_MODE2_TDS_TIMER_MASK,
646 FF_MODE2_TDS_TIMER_128))
647 },
648 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
649 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
650 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
651 DISABLE_CPS_AWARE_COLOR_PIPE))
652 },
653 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
654 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
655 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
656 PREEMPT_GPGPU_LEVEL_MASK,
657 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
658 },
659 { XE_RTP_NAME("1806527549"),
660 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
661 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
662 },
663 { XE_RTP_NAME("1606376872"),
664 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
665 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
666 },
667
668 /* DG1 */
669
670 { XE_RTP_NAME("1409044764"),
671 XE_RTP_RULES(PLATFORM(DG1)),
672 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
673 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
674 },
675 { XE_RTP_NAME("22010493298"),
676 XE_RTP_RULES(PLATFORM(DG1)),
677 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
678 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
679 },
680
681 /* DG2 */
682
683 { XE_RTP_NAME("16013271637"),
684 XE_RTP_RULES(PLATFORM(DG2)),
685 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
686 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
687 },
688 { XE_RTP_NAME("14014947963"),
689 XE_RTP_RULES(PLATFORM(DG2)),
690 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
691 PREEMPTION_VERTEX_COUNT,
692 0x4000))
693 },
694 { XE_RTP_NAME("18018764978"),
695 XE_RTP_RULES(PLATFORM(DG2)),
696 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
697 SCOREBOARD_STALL_FLUSH_CONTROL))
698 },
699 { XE_RTP_NAME("18019271663"),
700 XE_RTP_RULES(PLATFORM(DG2)),
701 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
702 },
703 { XE_RTP_NAME("14019877138"),
704 XE_RTP_RULES(PLATFORM(DG2)),
705 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
706 },
707
708 /* PVC */
709
710 { XE_RTP_NAME("16017236439"),
711 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
712 FUNC(xe_rtp_match_even_instance)),
713 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
714 BCS_SWCTRL_DISABLE_256B,
715 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
716 },
717
718 /* Xe_LPG */
719
720 { XE_RTP_NAME("18019271663"),
721 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
722 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
723 },
724 { XE_RTP_NAME("14019877138"),
725 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
726 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
727 },
728
729 /* Xe2_LPG */
730
731 { XE_RTP_NAME("16020518922"),
732 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
733 ENGINE_CLASS(RENDER)),
734 XE_RTP_ACTIONS(SET(FF_MODE,
735 DIS_TE_AUTOSTRIP |
736 DIS_MESH_PARTIAL_AUTOSTRIP |
737 DIS_MESH_AUTOSTRIP),
738 SET(VFLSKPD,
739 DIS_PARTIAL_AUTOSTRIP |
740 DIS_AUTOSTRIP))
741 },
742 { XE_RTP_NAME("14019386621"),
743 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
744 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
745 },
746 { XE_RTP_NAME("14019877138"),
747 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
748 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
749 },
750 { XE_RTP_NAME("14020013138"),
751 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
752 ENGINE_CLASS(RENDER)),
753 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
754 },
755 { XE_RTP_NAME("14019988906"),
756 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
757 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
758 },
759 { XE_RTP_NAME("16020183090"),
760 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
761 ENGINE_CLASS(RENDER)),
762 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
763 },
764 { XE_RTP_NAME("18033852989"),
765 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
766 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
767 },
768 { XE_RTP_NAME("14021567978"),
769 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
770 ENGINE_CLASS(RENDER)),
771 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
772 },
773 { XE_RTP_NAME("14020756599"),
774 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
775 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
776 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
777 },
778 { XE_RTP_NAME("14021490052"),
779 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
780 XE_RTP_ACTIONS(SET(FF_MODE,
781 DIS_MESH_PARTIAL_AUTOSTRIP |
782 DIS_MESH_AUTOSTRIP),
783 SET(VFLSKPD,
784 DIS_PARTIAL_AUTOSTRIP |
785 DIS_AUTOSTRIP))
786 },
787 { XE_RTP_NAME("15016589081"),
788 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
789 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
790 },
791
792 /* Xe2_HPG */
793 { XE_RTP_NAME("15010599737"),
794 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
795 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
796 },
797 { XE_RTP_NAME("14019386621"),
798 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
799 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
800 },
801 { XE_RTP_NAME("14020756599"),
802 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
803 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
804 },
805 { XE_RTP_NAME("14021490052"),
806 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
807 XE_RTP_ACTIONS(SET(FF_MODE,
808 DIS_MESH_PARTIAL_AUTOSTRIP |
809 DIS_MESH_AUTOSTRIP),
810 SET(VFLSKPD,
811 DIS_PARTIAL_AUTOSTRIP |
812 DIS_AUTOSTRIP))
813 },
814 { XE_RTP_NAME("15016589081"),
815 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
816 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
817 },
818 { XE_RTP_NAME("22021007897"),
819 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
820 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
821 },
822
823 /* Xe3_LPG */
824 { XE_RTP_NAME("14021490052"),
825 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
826 ENGINE_CLASS(RENDER)),
827 XE_RTP_ACTIONS(SET(FF_MODE,
828 DIS_MESH_PARTIAL_AUTOSTRIP |
829 DIS_MESH_AUTOSTRIP),
830 SET(VFLSKPD,
831 DIS_PARTIAL_AUTOSTRIP |
832 DIS_AUTOSTRIP))
833 },
834 };
835
836 static __maybe_unused const struct xe_rtp_entry oob_was[] = {
837 #include <generated/xe_wa_oob.c>
838 {}
839 };
840
841 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
842
843 __diag_pop();
844
845 /**
846 * xe_wa_process_oob - process OOB workaround table
847 * @gt: GT instance to process workarounds for
848 *
849 * Process OOB workaround table for this platform, marking in @gt the
850 * workarounds that are active.
851 */
xe_wa_process_oob(struct xe_gt * gt)852 void xe_wa_process_oob(struct xe_gt *gt)
853 {
854 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
855
856 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
857 ARRAY_SIZE(oob_was));
858 gt->wa_active.oob_initialized = true;
859 xe_rtp_process(&ctx, oob_was);
860 }
861
862 /**
863 * xe_wa_process_gt - process GT workaround table
864 * @gt: GT instance to process workarounds for
865 *
866 * Process GT workaround table for this platform, saving in @gt all the
867 * workarounds that need to be applied at the GT level.
868 */
xe_wa_process_gt(struct xe_gt * gt)869 void xe_wa_process_gt(struct xe_gt *gt)
870 {
871 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
872
873 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
874 ARRAY_SIZE(gt_was));
875 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr);
876 }
877 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
878
879 /**
880 * xe_wa_process_engine - process engine workaround table
881 * @hwe: engine instance to process workarounds for
882 *
883 * Process engine workaround table for this platform, saving in @hwe all the
884 * workarounds that need to be applied at the engine level that match this
885 * engine.
886 */
xe_wa_process_engine(struct xe_hw_engine * hwe)887 void xe_wa_process_engine(struct xe_hw_engine *hwe)
888 {
889 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
890
891 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
892 ARRAY_SIZE(engine_was));
893 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr);
894 }
895
896 /**
897 * xe_wa_process_lrc - process context workaround table
898 * @hwe: engine instance to process workarounds for
899 *
900 * Process context workaround table for this platform, saving in @hwe all the
901 * workarounds that need to be applied on context restore. These are workarounds
902 * touching registers that are part of the HW context image.
903 */
xe_wa_process_lrc(struct xe_hw_engine * hwe)904 void xe_wa_process_lrc(struct xe_hw_engine *hwe)
905 {
906 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
907
908 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
909 ARRAY_SIZE(lrc_was));
910 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc);
911 }
912
913 /**
914 * xe_wa_init - initialize gt with workaround bookkeeping
915 * @gt: GT instance to initialize
916 *
917 * Returns 0 for success, negative error code otherwise.
918 */
xe_wa_init(struct xe_gt * gt)919 int xe_wa_init(struct xe_gt *gt)
920 {
921 struct xe_device *xe = gt_to_xe(gt);
922 size_t n_oob, n_lrc, n_engine, n_gt, total;
923 unsigned long *p;
924
925 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
926 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
927 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
928 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
929 total = n_gt + n_engine + n_lrc + n_oob;
930
931 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
932 if (!p)
933 return -ENOMEM;
934
935 gt->wa_active.gt = p;
936 p += n_gt;
937 gt->wa_active.engine = p;
938 p += n_engine;
939 gt->wa_active.lrc = p;
940 p += n_lrc;
941 gt->wa_active.oob = p;
942
943 return 0;
944 }
945 ALLOW_ERROR_INJECTION(xe_wa_init, ERRNO); /* See xe_pci_probe() */
946
xe_wa_dump(struct xe_gt * gt,struct drm_printer * p)947 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
948 {
949 size_t idx;
950
951 drm_printf(p, "GT Workarounds\n");
952 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
953 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
954
955 drm_printf(p, "\nEngine Workarounds\n");
956 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
957 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
958
959 drm_printf(p, "\nLRC Workarounds\n");
960 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
961 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
962
963 drm_printf(p, "\nOOB Workarounds\n");
964 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
965 if (oob_was[idx].name)
966 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
967 }
968
969 /*
970 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
971 * adding anything to this function; most workarounds should be implemented
972 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
973 * which are relatively rare. Since the registers these workarounds target are
974 * outside the GT, they should only need to be applied once at device
975 * probe/resume; they will not lose their values on any kind of GT or engine
976 * reset.
977 *
978 * TODO: We may want to move this over to xe_rtp in the future once we have
979 * enough workarounds to justify the work.
980 */
xe_wa_apply_tile_workarounds(struct xe_tile * tile)981 void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
982 {
983 struct xe_mmio *mmio = &tile->mmio;
984
985 if (IS_SRIOV_VF(tile->xe))
986 return;
987
988 if (XE_WA(tile->primary_gt, 22010954014))
989 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
990 }
991