1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #include "xe_guc.h"
7 
8 #include <drm/drm_managed.h>
9 
10 #include <generated/xe_wa_oob.h>
11 
12 #include "abi/guc_actions_abi.h"
13 #include "abi/guc_errors_abi.h"
14 #include "regs/xe_gt_regs.h"
15 #include "regs/xe_gtt_defs.h"
16 #include "regs/xe_guc_regs.h"
17 #include "regs/xe_irq_regs.h"
18 #include "xe_bo.h"
19 #include "xe_device.h"
20 #include "xe_force_wake.h"
21 #include "xe_gt.h"
22 #include "xe_gt_printk.h"
23 #include "xe_gt_sriov_vf.h"
24 #include "xe_gt_throttle.h"
25 #include "xe_guc_ads.h"
26 #include "xe_guc_buf.h"
27 #include "xe_guc_capture.h"
28 #include "xe_guc_ct.h"
29 #include "xe_guc_db_mgr.h"
30 #include "xe_guc_engine_activity.h"
31 #include "xe_guc_hwconfig.h"
32 #include "xe_guc_log.h"
33 #include "xe_guc_pc.h"
34 #include "xe_guc_relay.h"
35 #include "xe_guc_submit.h"
36 #include "xe_memirq.h"
37 #include "xe_mmio.h"
38 #include "xe_platform_types.h"
39 #include "xe_sriov.h"
40 #include "xe_uc.h"
41 #include "xe_uc_fw.h"
42 #include "xe_wa.h"
43 #include "xe_wopcm.h"
44 
guc_bo_ggtt_addr(struct xe_guc * guc,struct xe_bo * bo)45 static u32 guc_bo_ggtt_addr(struct xe_guc *guc,
46 			    struct xe_bo *bo)
47 {
48 	struct xe_device *xe = guc_to_xe(guc);
49 	u32 addr;
50 
51 	/*
52 	 * For most BOs, the address on the allocating tile is fine. However for
53 	 * some, e.g. G2G CTB, the address on a specific tile is required as it
54 	 * might be different for each tile. So, just always ask for the address
55 	 * on the target GuC.
56 	 */
57 	addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id);
58 
59 	/* GuC addresses above GUC_GGTT_TOP don't map through the GTT */
60 	xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc)));
61 	xe_assert(xe, addr < GUC_GGTT_TOP);
62 	xe_assert(xe, bo->size <= GUC_GGTT_TOP - addr);
63 
64 	return addr;
65 }
66 
guc_ctl_debug_flags(struct xe_guc * guc)67 static u32 guc_ctl_debug_flags(struct xe_guc *guc)
68 {
69 	u32 level = xe_guc_log_get_level(&guc->log);
70 	u32 flags = 0;
71 
72 	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
73 		flags |= GUC_LOG_DISABLED;
74 	else
75 		flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
76 			 GUC_LOG_VERBOSITY_SHIFT;
77 
78 	return flags;
79 }
80 
guc_ctl_feature_flags(struct xe_guc * guc)81 static u32 guc_ctl_feature_flags(struct xe_guc *guc)
82 {
83 	u32 flags = GUC_CTL_ENABLE_LITE_RESTORE;
84 
85 	if (!guc_to_xe(guc)->info.skip_guc_pc)
86 		flags |= GUC_CTL_ENABLE_SLPC;
87 
88 	return flags;
89 }
90 
guc_ctl_log_params_flags(struct xe_guc * guc)91 static u32 guc_ctl_log_params_flags(struct xe_guc *guc)
92 {
93 	u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT;
94 	u32 flags;
95 
96 	#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
97 	#define LOG_UNIT SZ_1M
98 	#define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS
99 	#else
100 	#define LOG_UNIT SZ_4K
101 	#define LOG_FLAG 0
102 	#endif
103 
104 	#if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0)
105 	#define CAPTURE_UNIT SZ_1M
106 	#define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS
107 	#else
108 	#define CAPTURE_UNIT SZ_4K
109 	#define CAPTURE_FLAG 0
110 	#endif
111 
112 	BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
113 	BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT));
114 	BUILD_BUG_ON(!DEBUG_BUFFER_SIZE);
115 	BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT));
116 	BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE);
117 	BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT));
118 
119 	BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) >
120 			(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
121 	BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) >
122 			(GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT));
123 	BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) >
124 			(GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT));
125 
126 	flags = GUC_LOG_VALID |
127 		GUC_LOG_NOTIFY_ON_HALF_FULL |
128 		CAPTURE_FLAG |
129 		LOG_FLAG |
130 		((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
131 		((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |
132 		((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) <<
133 		 GUC_LOG_CAPTURE_SHIFT) |
134 		(offset << GUC_LOG_BUF_ADDR_SHIFT);
135 
136 	#undef LOG_UNIT
137 	#undef LOG_FLAG
138 	#undef CAPTURE_UNIT
139 	#undef CAPTURE_FLAG
140 
141 	return flags;
142 }
143 
guc_ctl_ads_flags(struct xe_guc * guc)144 static u32 guc_ctl_ads_flags(struct xe_guc *guc)
145 {
146 	u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT;
147 	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
148 
149 	return flags;
150 }
151 
needs_wa_dual_queue(struct xe_gt * gt)152 static bool needs_wa_dual_queue(struct xe_gt *gt)
153 {
154 	/*
155 	 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions
156 	 * on RCS and CCSes with different address spaces, which on DG2 is
157 	 * required as a WA for an HW bug.
158 	 */
159 	if (XE_WA(gt, 22011391025))
160 		return true;
161 
162 	/*
163 	 * On newer platforms, the HW has been updated to not allow parallel
164 	 * execution of different address spaces, so the RCS/CCS will stall the
165 	 * context switch if one of the other RCS/CCSes is busy with a different
166 	 * address space. While functionally correct, having a submission
167 	 * stalled on the HW limits the GuC ability to shuffle things around and
168 	 * can cause complications if the non-stalled submission runs for a long
169 	 * time, because the GuC doesn't know that the stalled submission isn't
170 	 * actually running and might declare it as hung. Therefore, we enable
171 	 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines
172 	 * to move management back to the GuC.
173 	 */
174 	if (CCS_MASK(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270)
175 		return true;
176 
177 	return false;
178 }
179 
guc_ctl_wa_flags(struct xe_guc * guc)180 static u32 guc_ctl_wa_flags(struct xe_guc *guc)
181 {
182 	struct xe_device *xe = guc_to_xe(guc);
183 	struct xe_gt *gt = guc_to_gt(guc);
184 	u32 flags = 0;
185 
186 	if (XE_WA(gt, 22012773006))
187 		flags |= GUC_WA_POLLCS;
188 
189 	if (XE_WA(gt, 14014475959))
190 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
191 
192 	if (needs_wa_dual_queue(gt))
193 		flags |= GUC_WA_DUAL_QUEUE;
194 
195 	/*
196 	 * Wa_22011802037: FIXME - there's more to be done than simply setting
197 	 * this flag: make sure each CS is stopped when preparing for GT reset
198 	 * and wait for pending MI_FW.
199 	 */
200 	if (GRAPHICS_VERx100(xe) < 1270)
201 		flags |= GUC_WA_PRE_PARSER;
202 
203 	if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685))
204 		flags |= GUC_WA_CONTEXT_ISOLATION;
205 
206 	if (XE_WA(gt, 18020744125) &&
207 	    !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER))
208 		flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
209 
210 	if (XE_WA(gt, 1509372804))
211 		flags |= GUC_WA_RENDER_RST_RC6_EXIT;
212 
213 	if (XE_WA(gt, 14018913170))
214 		flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
215 
216 	return flags;
217 }
218 
guc_ctl_devid(struct xe_guc * guc)219 static u32 guc_ctl_devid(struct xe_guc *guc)
220 {
221 	struct xe_device *xe = guc_to_xe(guc);
222 
223 	return (((u32)xe->info.devid) << 16) | xe->info.revid;
224 }
225 
guc_print_params(struct xe_guc * guc)226 static void guc_print_params(struct xe_guc *guc)
227 {
228 	struct xe_gt *gt = guc_to_gt(guc);
229 	u32 *params = guc->params;
230 	int i;
231 
232 	BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));
233 	BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT);
234 
235 	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
236 		xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]);
237 }
238 
guc_init_params(struct xe_guc * guc)239 static void guc_init_params(struct xe_guc *guc)
240 {
241 	u32 *params = guc->params;
242 
243 	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
244 	params[GUC_CTL_FEATURE] = 0;
245 	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
246 	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
247 	params[GUC_CTL_WA] = 0;
248 	params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
249 
250 	guc_print_params(guc);
251 }
252 
guc_init_params_post_hwconfig(struct xe_guc * guc)253 static void guc_init_params_post_hwconfig(struct xe_guc *guc)
254 {
255 	u32 *params = guc->params;
256 
257 	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
258 	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
259 	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
260 	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
261 	params[GUC_CTL_WA] = guc_ctl_wa_flags(guc);
262 	params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
263 
264 	guc_print_params(guc);
265 }
266 
267 /*
268  * Initialize the GuC parameter block before starting the firmware
269  * transfer. These parameters are read by the firmware on startup
270  * and cannot be changed thereafter.
271  */
guc_write_params(struct xe_guc * guc)272 static void guc_write_params(struct xe_guc *guc)
273 {
274 	struct xe_gt *gt = guc_to_gt(guc);
275 	int i;
276 
277 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
278 
279 	xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(0), 0);
280 
281 	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
282 		xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(1 + i), guc->params[i]);
283 }
284 
guc_action_register_g2g_buffer(struct xe_guc * guc,u32 type,u32 dst_tile,u32 dst_dev,u32 desc_addr,u32 buff_addr,u32 size)285 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev,
286 					  u32 desc_addr, u32 buff_addr, u32 size)
287 {
288 	struct xe_gt *gt = guc_to_gt(guc);
289 	struct xe_device *xe = gt_to_xe(gt);
290 	u32 action[] = {
291 		XE_GUC_ACTION_REGISTER_G2G,
292 		FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) |
293 		FIELD_PREP(XE_G2G_REGISTER_TYPE, type) |
294 		FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) |
295 		FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev),
296 		desc_addr,
297 		buff_addr,
298 	};
299 
300 	xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT));
301 	xe_assert(xe, !(size % SZ_4K));
302 
303 	return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
304 }
305 
guc_action_deregister_g2g_buffer(struct xe_guc * guc,u32 type,u32 dst_tile,u32 dst_dev)306 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev)
307 {
308 	struct xe_gt *gt = guc_to_gt(guc);
309 	struct xe_device *xe = gt_to_xe(gt);
310 	u32 action[] = {
311 		XE_GUC_ACTION_DEREGISTER_G2G,
312 		FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) |
313 		FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) |
314 		FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev),
315 	};
316 
317 	xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT));
318 
319 	return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
320 }
321 
322 #define G2G_DEV(gt)	(((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1)
323 
324 #define G2G_BUFFER_SIZE (SZ_4K)
325 #define G2G_DESC_SIZE (64)
326 #define G2G_DESC_AREA_SIZE (SZ_4K)
327 
328 /*
329  * Generate a unique id for each bi-directional CTB for each pair of
330  * near and far tiles/devices. The id can then be used as an index into
331  * a single allocation that is sub-divided into multiple CTBs.
332  *
333  * For example, with two devices per tile and two tiles, the table should
334  * look like:
335  *           Far <tile>.<dev>
336  *         0.0   0.1   1.0   1.1
337  * N 0.0  --/-- 00/01 02/03 04/05
338  * e 0.1  01/00 --/-- 06/07 08/09
339  * a 1.0  03/02 07/06 --/-- 10/11
340  * r 1.1  05/04 09/08 11/10 --/--
341  *
342  * Where each entry is Rx/Tx channel id.
343  *
344  * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would
345  * be reading from channel #11 and writing to channel #10. Whereas,
346  * GuC #2 talking to GuC #3 would be read on #10 and write to #11.
347  */
g2g_slot(u32 near_tile,u32 near_dev,u32 far_tile,u32 far_dev,u32 type,u32 max_inst,bool have_dev)348 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev,
349 			     u32 type, u32 max_inst, bool have_dev)
350 {
351 	u32 near = near_tile, far = far_tile;
352 	u32 idx = 0, x, y, direction;
353 	int i;
354 
355 	if (have_dev) {
356 		near = (near << 1) | near_dev;
357 		far = (far << 1) | far_dev;
358 	}
359 
360 	/* No need to send to one's self */
361 	if (far == near)
362 		return -1;
363 
364 	if (far > near) {
365 		/* Top right table half */
366 		x = far;
367 		y = near;
368 
369 		/* T/R is 'forwards' direction */
370 		direction = type;
371 	} else {
372 		/* Bottom left table half */
373 		x = near;
374 		y = far;
375 
376 		/* B/L is 'backwards' direction */
377 		direction = (1 - type);
378 	}
379 
380 	/* Count the rows prior to the target */
381 	for (i = y; i > 0; i--)
382 		idx += max_inst - i;
383 
384 	/* Count this row up to the target */
385 	idx += (x - 1 - y);
386 
387 	/* Slots are in Rx/Tx pairs */
388 	idx *= 2;
389 
390 	/* Pick Rx/Tx direction */
391 	idx += direction;
392 
393 	return idx;
394 }
395 
guc_g2g_register(struct xe_guc * near_guc,struct xe_gt * far_gt,u32 type,bool have_dev)396 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev)
397 {
398 	struct xe_gt *near_gt = guc_to_gt(near_guc);
399 	struct xe_device *xe = gt_to_xe(near_gt);
400 	struct xe_bo *g2g_bo;
401 	u32 near_tile = gt_to_tile(near_gt)->id;
402 	u32 near_dev = G2G_DEV(near_gt);
403 	u32 far_tile = gt_to_tile(far_gt)->id;
404 	u32 far_dev = G2G_DEV(far_gt);
405 	u32 max = xe->info.gt_count;
406 	u32 base, desc, buf;
407 	int slot;
408 
409 	/* G2G is not allowed between different cards */
410 	xe_assert(xe, xe == gt_to_xe(far_gt));
411 
412 	g2g_bo = near_guc->g2g.bo;
413 	xe_assert(xe, g2g_bo);
414 
415 	slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev);
416 	xe_assert(xe, slot >= 0);
417 
418 	base = guc_bo_ggtt_addr(near_guc, g2g_bo);
419 	desc = base + slot * G2G_DESC_SIZE;
420 	buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE;
421 
422 	xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE);
423 	xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= g2g_bo->size);
424 
425 	return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev,
426 					      desc, buf, G2G_BUFFER_SIZE);
427 }
428 
guc_g2g_deregister(struct xe_guc * guc,u32 far_tile,u32 far_dev,u32 type)429 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type)
430 {
431 	guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev);
432 }
433 
guc_g2g_size(struct xe_guc * guc)434 static u32 guc_g2g_size(struct xe_guc *guc)
435 {
436 	struct xe_gt *gt = guc_to_gt(guc);
437 	struct xe_device *xe = gt_to_xe(gt);
438 	unsigned int count = xe->info.gt_count;
439 	u32 num_channels = (count * (count - 1)) / 2;
440 
441 	xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE);
442 
443 	return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE;
444 }
445 
xe_guc_g2g_wanted(struct xe_device * xe)446 static bool xe_guc_g2g_wanted(struct xe_device *xe)
447 {
448 	/* Can't do GuC to GuC communication if there is only one GuC */
449 	if (xe->info.gt_count <= 1)
450 		return false;
451 
452 	/* No current user */
453 	return false;
454 }
455 
guc_g2g_alloc(struct xe_guc * guc)456 static int guc_g2g_alloc(struct xe_guc *guc)
457 {
458 	struct xe_gt *gt = guc_to_gt(guc);
459 	struct xe_device *xe = gt_to_xe(gt);
460 	struct xe_tile *tile = gt_to_tile(gt);
461 	struct xe_bo *bo;
462 	u32 g2g_size;
463 
464 	if (guc->g2g.bo)
465 		return 0;
466 
467 	if (gt->info.id != 0) {
468 		struct xe_gt *root_gt = xe_device_get_gt(xe, 0);
469 		struct xe_guc *root_guc = &root_gt->uc.guc;
470 		struct xe_bo *bo;
471 
472 		bo = xe_bo_get(root_guc->g2g.bo);
473 		if (!bo)
474 			return -ENODEV;
475 
476 		guc->g2g.bo = bo;
477 		guc->g2g.owned = false;
478 		return 0;
479 	}
480 
481 	g2g_size = guc_g2g_size(guc);
482 	bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size,
483 					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
484 					  XE_BO_FLAG_GGTT |
485 					  XE_BO_FLAG_GGTT_ALL |
486 					  XE_BO_FLAG_GGTT_INVALIDATE);
487 	if (IS_ERR(bo))
488 		return PTR_ERR(bo);
489 
490 	xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size);
491 	guc->g2g.bo = bo;
492 	guc->g2g.owned = true;
493 
494 	return 0;
495 }
496 
guc_g2g_fini(struct xe_guc * guc)497 static void guc_g2g_fini(struct xe_guc *guc)
498 {
499 	if (!guc->g2g.bo)
500 		return;
501 
502 	/* Unpinning the owned object is handled by generic shutdown */
503 	if (!guc->g2g.owned)
504 		xe_bo_put(guc->g2g.bo);
505 
506 	guc->g2g.bo = NULL;
507 }
508 
guc_g2g_start(struct xe_guc * guc)509 static int guc_g2g_start(struct xe_guc *guc)
510 {
511 	struct xe_gt *far_gt, *gt = guc_to_gt(guc);
512 	struct xe_device *xe = gt_to_xe(gt);
513 	unsigned int i, j;
514 	int t, err;
515 	bool have_dev;
516 
517 	if (!guc->g2g.bo) {
518 		int ret;
519 
520 		ret = guc_g2g_alloc(guc);
521 		if (ret)
522 			return ret;
523 	}
524 
525 	/* GuC interface will need extending if more GT device types are ever created. */
526 	xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA));
527 
528 	/* Channel numbering depends on whether there are multiple GTs per tile */
529 	have_dev = xe->info.gt_count > xe->info.tile_count;
530 
531 	for_each_gt(far_gt, xe, i) {
532 		u32 far_tile, far_dev;
533 
534 		if (far_gt->info.id == gt->info.id)
535 			continue;
536 
537 		far_tile = gt_to_tile(far_gt)->id;
538 		far_dev = G2G_DEV(far_gt);
539 
540 		for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) {
541 			err = guc_g2g_register(guc, far_gt, t, have_dev);
542 			if (err) {
543 				while (--t >= 0)
544 					guc_g2g_deregister(guc, far_tile, far_dev, t);
545 				goto err_deregister;
546 			}
547 		}
548 	}
549 
550 	return 0;
551 
552 err_deregister:
553 	for_each_gt(far_gt, xe, j) {
554 		u32 tile, dev;
555 
556 		if (far_gt->info.id == gt->info.id)
557 			continue;
558 
559 		if (j >= i)
560 			break;
561 
562 		tile = gt_to_tile(far_gt)->id;
563 		dev = G2G_DEV(far_gt);
564 
565 		for (t = 0; t < XE_G2G_TYPE_LIMIT; t++)
566 			guc_g2g_deregister(guc, tile, dev, t);
567 	}
568 
569 	return err;
570 }
571 
guc_fini_hw(void * arg)572 static void guc_fini_hw(void *arg)
573 {
574 	struct xe_guc *guc = arg;
575 	struct xe_gt *gt = guc_to_gt(guc);
576 	unsigned int fw_ref;
577 
578 	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
579 	xe_uc_fini_hw(&guc_to_gt(guc)->uc);
580 	xe_force_wake_put(gt_to_fw(gt), fw_ref);
581 
582 	guc_g2g_fini(guc);
583 }
584 
585 /**
586  * xe_guc_comm_init_early - early initialization of GuC communication
587  * @guc: the &xe_guc to initialize
588  *
589  * Must be called prior to first MMIO communication with GuC firmware.
590  */
xe_guc_comm_init_early(struct xe_guc * guc)591 void xe_guc_comm_init_early(struct xe_guc *guc)
592 {
593 	struct xe_gt *gt = guc_to_gt(guc);
594 
595 	if (xe_gt_is_media_type(gt))
596 		guc->notify_reg = MED_GUC_HOST_INTERRUPT;
597 	else
598 		guc->notify_reg = GUC_HOST_INTERRUPT;
599 }
600 
xe_guc_realloc_post_hwconfig(struct xe_guc * guc)601 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
602 {
603 	struct xe_tile *tile = gt_to_tile(guc_to_gt(guc));
604 	struct xe_device *xe = guc_to_xe(guc);
605 	int ret;
606 
607 	if (!IS_DGFX(guc_to_xe(guc)))
608 		return 0;
609 
610 	ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo);
611 	if (ret)
612 		return ret;
613 
614 	ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo);
615 	if (ret)
616 		return ret;
617 
618 	ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo);
619 	if (ret)
620 		return ret;
621 
622 	ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ct.bo);
623 	if (ret)
624 		return ret;
625 
626 	return 0;
627 }
628 
vf_guc_init(struct xe_guc * guc)629 static int vf_guc_init(struct xe_guc *guc)
630 {
631 	int err;
632 
633 	xe_guc_comm_init_early(guc);
634 
635 	err = xe_guc_ct_init(&guc->ct);
636 	if (err)
637 		return err;
638 
639 	err = xe_guc_relay_init(&guc->relay);
640 	if (err)
641 		return err;
642 
643 	return 0;
644 }
645 
xe_guc_init(struct xe_guc * guc)646 int xe_guc_init(struct xe_guc *guc)
647 {
648 	struct xe_device *xe = guc_to_xe(guc);
649 	struct xe_gt *gt = guc_to_gt(guc);
650 	int ret;
651 
652 	guc->fw.type = XE_UC_FW_TYPE_GUC;
653 	ret = xe_uc_fw_init(&guc->fw);
654 	if (ret)
655 		goto out;
656 
657 	if (!xe_uc_fw_is_enabled(&guc->fw))
658 		return 0;
659 
660 	if (IS_SRIOV_VF(xe)) {
661 		ret = vf_guc_init(guc);
662 		if (ret)
663 			goto out;
664 		return 0;
665 	}
666 
667 	ret = xe_guc_log_init(&guc->log);
668 	if (ret)
669 		goto out;
670 
671 	ret = xe_guc_capture_init(guc);
672 	if (ret)
673 		goto out;
674 
675 	ret = xe_guc_ads_init(&guc->ads);
676 	if (ret)
677 		goto out;
678 
679 	ret = xe_guc_ct_init(&guc->ct);
680 	if (ret)
681 		goto out;
682 
683 	ret = xe_guc_relay_init(&guc->relay);
684 	if (ret)
685 		goto out;
686 
687 	xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE);
688 
689 	ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc);
690 	if (ret)
691 		goto out;
692 
693 	guc_init_params(guc);
694 
695 	xe_guc_comm_init_early(guc);
696 
697 	return 0;
698 
699 out:
700 	xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret));
701 	return ret;
702 }
703 
vf_guc_init_post_hwconfig(struct xe_guc * guc)704 static int vf_guc_init_post_hwconfig(struct xe_guc *guc)
705 {
706 	int err;
707 
708 	err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc)));
709 	if (err)
710 		return err;
711 
712 	/* XXX xe_guc_db_mgr_init not needed for now */
713 
714 	return 0;
715 }
716 
717 /**
718  * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load
719  * @guc: The GuC object
720  *
721  * Return: 0 on success, negative error code on error.
722  */
xe_guc_init_post_hwconfig(struct xe_guc * guc)723 int xe_guc_init_post_hwconfig(struct xe_guc *guc)
724 {
725 	int ret;
726 
727 	if (IS_SRIOV_VF(guc_to_xe(guc)))
728 		return vf_guc_init_post_hwconfig(guc);
729 
730 	ret = xe_guc_realloc_post_hwconfig(guc);
731 	if (ret)
732 		return ret;
733 
734 	guc_init_params_post_hwconfig(guc);
735 
736 	ret = xe_guc_submit_init(guc, ~0);
737 	if (ret)
738 		return ret;
739 
740 	ret = xe_guc_db_mgr_init(&guc->dbm, ~0);
741 	if (ret)
742 		return ret;
743 
744 	ret = xe_guc_pc_init(&guc->pc);
745 	if (ret)
746 		return ret;
747 
748 	ret = xe_guc_engine_activity_init(guc);
749 	if (ret)
750 		return ret;
751 
752 	ret = xe_guc_buf_cache_init(&guc->buf);
753 	if (ret)
754 		return ret;
755 
756 	return xe_guc_ads_init_post_hwconfig(&guc->ads);
757 }
758 
xe_guc_post_load_init(struct xe_guc * guc)759 int xe_guc_post_load_init(struct xe_guc *guc)
760 {
761 	int ret;
762 
763 	xe_guc_ads_populate_post_load(&guc->ads);
764 
765 	if (xe_guc_g2g_wanted(guc_to_xe(guc))) {
766 		ret = guc_g2g_start(guc);
767 		if (ret)
768 			return ret;
769 	}
770 
771 	guc->submission_state.enabled = true;
772 
773 	return 0;
774 }
775 
xe_guc_reset(struct xe_guc * guc)776 int xe_guc_reset(struct xe_guc *guc)
777 {
778 	struct xe_gt *gt = guc_to_gt(guc);
779 	struct xe_mmio *mmio = &gt->mmio;
780 	u32 guc_status, gdrst;
781 	int ret;
782 
783 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
784 
785 	if (IS_SRIOV_VF(gt_to_xe(gt)))
786 		return xe_gt_sriov_vf_bootstrap(gt);
787 
788 	xe_mmio_write32(mmio, GDRST, GRDOM_GUC);
789 
790 	ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false);
791 	if (ret) {
792 		xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst);
793 		goto err_out;
794 	}
795 
796 	guc_status = xe_mmio_read32(mmio, GUC_STATUS);
797 	if (!(guc_status & GS_MIA_IN_RESET)) {
798 		xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n",
799 			  guc_status);
800 		ret = -EIO;
801 		goto err_out;
802 	}
803 
804 	return 0;
805 
806 err_out:
807 
808 	return ret;
809 }
810 
guc_prepare_xfer(struct xe_guc * guc)811 static void guc_prepare_xfer(struct xe_guc *guc)
812 {
813 	struct xe_gt *gt = guc_to_gt(guc);
814 	struct xe_mmio *mmio = &gt->mmio;
815 	struct xe_device *xe =  guc_to_xe(guc);
816 	u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
817 		GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
818 		GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
819 		GUC_ENABLE_MIA_CLOCK_GATING;
820 
821 	if (GRAPHICS_VERx100(xe) < 1250)
822 		shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
823 				GUC_ENABLE_MIA_CACHING;
824 
825 	if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
826 		shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index);
827 
828 	/* Must program this register before loading the ucode with DMA */
829 	xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags);
830 
831 	xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
832 
833 	/* Make sure GuC receives ARAT interrupts */
834 	xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0);
835 }
836 
837 /*
838  * Supporting MMIO & in memory RSA
839  */
guc_xfer_rsa(struct xe_guc * guc)840 static int guc_xfer_rsa(struct xe_guc *guc)
841 {
842 	struct xe_gt *gt = guc_to_gt(guc);
843 	u32 rsa[UOS_RSA_SCRATCH_COUNT];
844 	size_t copied;
845 	int i;
846 
847 	if (guc->fw.rsa_size > 256) {
848 		u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) +
849 				    xe_uc_fw_rsa_offset(&guc->fw);
850 		xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
851 		return 0;
852 	}
853 
854 	copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa));
855 	if (copied < sizeof(rsa))
856 		return -ENOMEM;
857 
858 	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
859 		xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(i), rsa[i]);
860 
861 	return 0;
862 }
863 
864 /*
865  * Check a previously read GuC status register (GUC_STATUS) looking for
866  * known terminal states (either completion or failure) of either the
867  * microkernel status field or the boot ROM status field. Returns +1 for
868  * successful completion, -1 for failure and 0 for any intermediate state.
869  */
guc_load_done(u32 status)870 static int guc_load_done(u32 status)
871 {
872 	u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status);
873 	u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status);
874 
875 	switch (uk_val) {
876 	case XE_GUC_LOAD_STATUS_READY:
877 		return 1;
878 
879 	case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH:
880 	case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH:
881 	case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE:
882 	case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR:
883 	case XE_GUC_LOAD_STATUS_DPC_ERROR:
884 	case XE_GUC_LOAD_STATUS_EXCEPTION:
885 	case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID:
886 	case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID:
887 	case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
888 		return -1;
889 	}
890 
891 	switch (br_val) {
892 	case XE_BOOTROM_STATUS_NO_KEY_FOUND:
893 	case XE_BOOTROM_STATUS_RSA_FAILED:
894 	case XE_BOOTROM_STATUS_PAVPC_FAILED:
895 	case XE_BOOTROM_STATUS_WOPCM_FAILED:
896 	case XE_BOOTROM_STATUS_LOADLOC_FAILED:
897 	case XE_BOOTROM_STATUS_JUMP_FAILED:
898 	case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED:
899 	case XE_BOOTROM_STATUS_MPUMAP_INCORRECT:
900 	case XE_BOOTROM_STATUS_EXCEPTION:
901 	case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
902 		return -1;
903 	}
904 
905 	return 0;
906 }
907 
guc_pc_get_cur_freq(struct xe_guc_pc * guc_pc)908 static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc)
909 {
910 	u32 freq;
911 	int ret = xe_guc_pc_get_cur_freq(guc_pc, &freq);
912 
913 	return ret ? ret : freq;
914 }
915 
916 /*
917  * Wait for the GuC to start up.
918  *
919  * Measurements indicate this should take no more than 20ms (assuming the GT
920  * clock is at maximum frequency). However, thermal throttling and other issues
921  * can prevent the clock hitting max and thus making the load take significantly
922  * longer. Allow up to 200ms as a safety margin for real world worst case situations.
923  *
924  * However, bugs anywhere from KMD to GuC to PCODE to fan failure in a CI farm can
925  * lead to even longer times. E.g. if the GT is clamped to minimum frequency then
926  * the load times can be in the seconds range. So the timeout is increased for debug
927  * builds to ensure that problems can be correctly analysed. For release builds, the
928  * timeout is kept short so that users don't wait forever to find out that there is a
929  * problem. In either case, if the load took longer than is reasonable even with some
930  * 'sensible' throttling, then flag a warning because something is not right.
931  *
932  * Note that there is a limit on how long an individual usleep_range() can wait for,
933  * hence longer waits require wrapping a shorter wait in a loop.
934  *
935  * Note that the only reason an end user should hit the shorter timeout is in case of
936  * extreme thermal throttling. And a system that is that hot during boot is probably
937  * dead anyway!
938  */
939 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
940 #define GUC_LOAD_RETRY_LIMIT	20
941 #else
942 #define GUC_LOAD_RETRY_LIMIT	3
943 #endif
944 #define GUC_LOAD_TIME_WARN_MS      200
945 
guc_wait_ucode(struct xe_guc * guc)946 static void guc_wait_ucode(struct xe_guc *guc)
947 {
948 	struct xe_gt *gt = guc_to_gt(guc);
949 	struct xe_mmio *mmio = &gt->mmio;
950 	struct xe_guc_pc *guc_pc = &gt->uc.guc.pc;
951 	ktime_t before, after, delta;
952 	int load_done;
953 	u32 status = 0;
954 	int count = 0;
955 	u64 delta_ms;
956 	u32 before_freq;
957 
958 	before_freq = xe_guc_pc_get_act_freq(guc_pc);
959 	before = ktime_get();
960 	/*
961 	 * Note, can't use any kind of timing information from the call to xe_mmio_wait.
962 	 * It could return a thousand intermediate stages at random times. Instead, must
963 	 * manually track the total time taken and locally implement the timeout.
964 	 */
965 	do {
966 		u32 last_status = status & (GS_UKERNEL_MASK | GS_BOOTROM_MASK);
967 		int ret;
968 
969 		/*
970 		 * Wait for any change (intermediate or terminal) in the status register.
971 		 * Note, the return value is a don't care. The only failure code is timeout
972 		 * but the timeouts need to be accumulated over all the intermediate partial
973 		 * timeouts rather than allowing a huge timeout each time. So basically, need
974 		 * to treat a timeout no different to a value change.
975 		 */
976 		ret = xe_mmio_wait32_not(mmio, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK,
977 					 last_status, 1000 * 1000, &status, false);
978 		if (ret < 0)
979 			count++;
980 		after = ktime_get();
981 		delta = ktime_sub(after, before);
982 		delta_ms = ktime_to_ms(delta);
983 
984 		load_done = guc_load_done(status);
985 		if (load_done != 0)
986 			break;
987 
988 		if (delta_ms >= (GUC_LOAD_RETRY_LIMIT * 1000))
989 			break;
990 
991 		xe_gt_dbg(gt, "load still in progress, timeouts = %d, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n",
992 			  count, xe_guc_pc_get_act_freq(guc_pc),
993 			  guc_pc_get_cur_freq(guc_pc), status,
994 			  REG_FIELD_GET(GS_BOOTROM_MASK, status),
995 			  REG_FIELD_GET(GS_UKERNEL_MASK, status));
996 	} while (1);
997 
998 	if (load_done != 1) {
999 		u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status);
1000 		u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);
1001 
1002 		xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz), done = %d\n",
1003 			  status, delta_ms, xe_guc_pc_get_act_freq(guc_pc),
1004 			  guc_pc_get_cur_freq(guc_pc), load_done);
1005 		xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
1006 			  REG_FIELD_GET(GS_MIA_IN_RESET, status),
1007 			  bootrom, ukernel,
1008 			  REG_FIELD_GET(GS_MIA_MASK, status),
1009 			  REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
1010 
1011 		switch (bootrom) {
1012 		case XE_BOOTROM_STATUS_NO_KEY_FOUND:
1013 			xe_gt_err(gt, "invalid key requested, header = 0x%08X\n",
1014 				  xe_mmio_read32(mmio, GUC_HEADER_INFO));
1015 			break;
1016 
1017 		case XE_BOOTROM_STATUS_RSA_FAILED:
1018 			xe_gt_err(gt, "firmware signature verification failed\n");
1019 			break;
1020 
1021 		case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
1022 			xe_gt_err(gt, "firmware production part check failure\n");
1023 			break;
1024 		}
1025 
1026 		switch (ukernel) {
1027 		case XE_GUC_LOAD_STATUS_EXCEPTION:
1028 			xe_gt_err(gt, "firmware exception. EIP: %#x\n",
1029 				  xe_mmio_read32(mmio, SOFT_SCRATCH(13)));
1030 			break;
1031 
1032 		case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
1033 			xe_gt_err(gt, "illegal register in save/restore workaround list\n");
1034 			break;
1035 
1036 		case XE_GUC_LOAD_STATUS_HWCONFIG_START:
1037 			xe_gt_err(gt, "still extracting hwconfig table.\n");
1038 			break;
1039 		}
1040 
1041 		xe_device_declare_wedged(gt_to_xe(gt));
1042 	} else if (delta_ms > GUC_LOAD_TIME_WARN_MS) {
1043 		xe_gt_warn(gt, "excessive init time: %lldms! [status = 0x%08X, timeouts = %d]\n",
1044 			   delta_ms, status, count);
1045 		xe_gt_warn(gt, "excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n",
1046 			   xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc),
1047 			   before_freq, xe_gt_throttle_get_limit_reasons(gt));
1048 	} else {
1049 		xe_gt_dbg(gt, "init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X, timeouts = %d\n",
1050 			  delta_ms, xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc),
1051 			  before_freq, status, count);
1052 	}
1053 }
1054 
__xe_guc_upload(struct xe_guc * guc)1055 static int __xe_guc_upload(struct xe_guc *guc)
1056 {
1057 	int ret;
1058 
1059 	/* Raise GT freq to speed up HuC/GuC load */
1060 	xe_guc_pc_raise_unslice(&guc->pc);
1061 
1062 	guc_write_params(guc);
1063 	guc_prepare_xfer(guc);
1064 
1065 	/*
1066 	 * Note that GuC needs the CSS header plus uKernel code to be copied
1067 	 * by the DMA engine in one operation, whereas the RSA signature is
1068 	 * loaded separately, either by copying it to the UOS_RSA_SCRATCH
1069 	 * register (if key size <= 256) or through a ggtt-pinned vma (if key
1070 	 * size > 256). The RSA size and therefore the way we provide it to the
1071 	 * HW is fixed for each platform and hard-coded in the bootrom.
1072 	 */
1073 	ret = guc_xfer_rsa(guc);
1074 	if (ret)
1075 		goto out;
1076 	/*
1077 	 * Current uCode expects the code to be loaded at 8k; locations below
1078 	 * this are used for the stack.
1079 	 */
1080 	ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
1081 	if (ret)
1082 		goto out;
1083 
1084 	/* Wait for authentication */
1085 	guc_wait_ucode(guc);
1086 
1087 	xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING);
1088 	return 0;
1089 
1090 out:
1091 	xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL);
1092 	return 0	/* FIXME: ret, don't want to stop load currently */;
1093 }
1094 
vf_guc_min_load_for_hwconfig(struct xe_guc * guc)1095 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc)
1096 {
1097 	struct xe_gt *gt = guc_to_gt(guc);
1098 	int ret;
1099 
1100 	ret = xe_gt_sriov_vf_bootstrap(gt);
1101 	if (ret)
1102 		return ret;
1103 
1104 	ret = xe_gt_sriov_vf_query_config(gt);
1105 	if (ret)
1106 		return ret;
1107 
1108 	ret = xe_guc_hwconfig_init(guc);
1109 	if (ret)
1110 		return ret;
1111 
1112 	ret = xe_guc_enable_communication(guc);
1113 	if (ret)
1114 		return ret;
1115 
1116 	ret = xe_gt_sriov_vf_connect(gt);
1117 	if (ret)
1118 		return ret;
1119 
1120 	ret = xe_gt_sriov_vf_query_runtime(gt);
1121 	if (ret)
1122 		return ret;
1123 
1124 	return 0;
1125 }
1126 
1127 /**
1128  * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table
1129  * @guc: The GuC object
1130  *
1131  * This function uploads a minimal GuC that does not support submissions but
1132  * in a state where the hwconfig table can be read. Next, it reads and parses
1133  * the hwconfig table so it can be used for subsequent steps in the driver load.
1134  * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only).
1135  *
1136  * Return: 0 on success, negative error code on error.
1137  */
xe_guc_min_load_for_hwconfig(struct xe_guc * guc)1138 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
1139 {
1140 	int ret;
1141 
1142 	if (IS_SRIOV_VF(guc_to_xe(guc)))
1143 		return vf_guc_min_load_for_hwconfig(guc);
1144 
1145 	xe_guc_ads_populate_minimal(&guc->ads);
1146 
1147 	xe_guc_pc_init_early(&guc->pc);
1148 
1149 	ret = __xe_guc_upload(guc);
1150 	if (ret)
1151 		return ret;
1152 
1153 	ret = xe_guc_hwconfig_init(guc);
1154 	if (ret)
1155 		return ret;
1156 
1157 	ret = xe_guc_enable_communication(guc);
1158 	if (ret)
1159 		return ret;
1160 
1161 	return 0;
1162 }
1163 
xe_guc_upload(struct xe_guc * guc)1164 int xe_guc_upload(struct xe_guc *guc)
1165 {
1166 	xe_guc_ads_populate(&guc->ads);
1167 
1168 	return __xe_guc_upload(guc);
1169 }
1170 
guc_handle_mmio_msg(struct xe_guc * guc)1171 static void guc_handle_mmio_msg(struct xe_guc *guc)
1172 {
1173 	struct xe_gt *gt = guc_to_gt(guc);
1174 	u32 msg;
1175 
1176 	if (IS_SRIOV_VF(guc_to_xe(guc)))
1177 		return;
1178 
1179 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
1180 
1181 	msg = xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(15));
1182 	msg &= XE_GUC_RECV_MSG_EXCEPTION |
1183 		XE_GUC_RECV_MSG_CRASH_DUMP_POSTED;
1184 	xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(15), 0);
1185 
1186 	if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED)
1187 		xe_gt_err(gt, "Received early GuC crash dump notification!\n");
1188 
1189 	if (msg & XE_GUC_RECV_MSG_EXCEPTION)
1190 		xe_gt_err(gt, "Received early GuC exception notification!\n");
1191 }
1192 
guc_enable_irq(struct xe_guc * guc)1193 static void guc_enable_irq(struct xe_guc *guc)
1194 {
1195 	struct xe_gt *gt = guc_to_gt(guc);
1196 	u32 events = xe_gt_is_media_type(gt) ?
1197 		REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST)  :
1198 		REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
1199 
1200 	/* Primary GuC and media GuC share a single enable bit */
1201 	xe_mmio_write32(&gt->mmio, GUC_SG_INTR_ENABLE,
1202 			REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));
1203 
1204 	/*
1205 	 * There are separate mask bits for primary and media GuCs, so use
1206 	 * a RMW operation to avoid clobbering the other GuC's setting.
1207 	 */
1208 	xe_mmio_rmw32(&gt->mmio, GUC_SG_INTR_MASK, events, 0);
1209 }
1210 
xe_guc_enable_communication(struct xe_guc * guc)1211 int xe_guc_enable_communication(struct xe_guc *guc)
1212 {
1213 	struct xe_device *xe = guc_to_xe(guc);
1214 	int err;
1215 
1216 	if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) {
1217 		struct xe_gt *gt = guc_to_gt(guc);
1218 		struct xe_tile *tile = gt_to_tile(gt);
1219 
1220 		err = xe_memirq_init_guc(&tile->memirq, guc);
1221 		if (err)
1222 			return err;
1223 	} else {
1224 		guc_enable_irq(guc);
1225 	}
1226 
1227 	err = xe_guc_ct_enable(&guc->ct);
1228 	if (err)
1229 		return err;
1230 
1231 	guc_handle_mmio_msg(guc);
1232 
1233 	return 0;
1234 }
1235 
xe_guc_suspend(struct xe_guc * guc)1236 int xe_guc_suspend(struct xe_guc *guc)
1237 {
1238 	struct xe_gt *gt = guc_to_gt(guc);
1239 	u32 action[] = {
1240 		XE_GUC_ACTION_CLIENT_SOFT_RESET,
1241 	};
1242 	int ret;
1243 
1244 	ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
1245 	if (ret) {
1246 		xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret));
1247 		return ret;
1248 	}
1249 
1250 	xe_guc_sanitize(guc);
1251 	return 0;
1252 }
1253 
xe_guc_notify(struct xe_guc * guc)1254 void xe_guc_notify(struct xe_guc *guc)
1255 {
1256 	struct xe_gt *gt = guc_to_gt(guc);
1257 	const u32 default_notify_data = 0;
1258 
1259 	/*
1260 	 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass
1261 	 * additional payload data to the GuC but this capability is not
1262 	 * used by the firmware yet. Use default value in the meantime.
1263 	 */
1264 	xe_mmio_write32(&gt->mmio, guc->notify_reg, default_notify_data);
1265 }
1266 
xe_guc_auth_huc(struct xe_guc * guc,u32 rsa_addr)1267 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
1268 {
1269 	u32 action[] = {
1270 		XE_GUC_ACTION_AUTHENTICATE_HUC,
1271 		rsa_addr
1272 	};
1273 
1274 	return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
1275 }
1276 
xe_guc_mmio_send_recv(struct xe_guc * guc,const u32 * request,u32 len,u32 * response_buf)1277 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
1278 			  u32 len, u32 *response_buf)
1279 {
1280 	struct xe_device *xe = guc_to_xe(guc);
1281 	struct xe_gt *gt = guc_to_gt(guc);
1282 	struct xe_mmio *mmio = &gt->mmio;
1283 	u32 header, reply;
1284 	struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
1285 		MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
1286 	const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1;
1287 	int ret;
1288 	int i;
1289 
1290 	BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT);
1291 
1292 	xe_assert(xe, len);
1293 	xe_assert(xe, len <= VF_SW_FLAG_COUNT);
1294 	xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT);
1295 	xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) ==
1296 		  GUC_HXG_ORIGIN_HOST);
1297 	xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) ==
1298 		  GUC_HXG_TYPE_REQUEST);
1299 
1300 retry:
1301 	/* Not in critical data-path, just do if else for GT type */
1302 	if (xe_gt_is_media_type(gt)) {
1303 		for (i = 0; i < len; ++i)
1304 			xe_mmio_write32(mmio, MED_VF_SW_FLAG(i),
1305 					request[i]);
1306 		xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX));
1307 	} else {
1308 		for (i = 0; i < len; ++i)
1309 			xe_mmio_write32(mmio, VF_SW_FLAG(i),
1310 					request[i]);
1311 		xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX));
1312 	}
1313 
1314 	xe_guc_notify(guc);
1315 
1316 	ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN,
1317 			     FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC),
1318 			     50000, &reply, false);
1319 	if (ret) {
1320 timeout:
1321 		xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n",
1322 			  request[0], reply);
1323 		return ret;
1324 	}
1325 
1326 	header = xe_mmio_read32(mmio, reply_reg);
1327 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
1328 	    GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
1329 		/*
1330 		 * Once we got a BUSY reply we must wait again for the final
1331 		 * response but this time we can't use ORIGIN mask anymore.
1332 		 * To spot a right change in the reply, we take advantage that
1333 		 * response SUCCESS and FAILURE differ only by the single bit
1334 		 * and all other bits are set and can be used as a new mask.
1335 		 */
1336 		u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE;
1337 		u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits);
1338 
1339 		BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS);
1340 		BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1);
1341 
1342 		ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask,
1343 				     1000000, &header, false);
1344 
1345 		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
1346 			     GUC_HXG_ORIGIN_GUC))
1347 			goto proto;
1348 		if (unlikely(ret)) {
1349 			if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=
1350 			    GUC_HXG_TYPE_NO_RESPONSE_BUSY)
1351 				goto proto;
1352 			goto timeout;
1353 		}
1354 	}
1355 
1356 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
1357 	    GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
1358 		u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
1359 
1360 		xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n",
1361 			  request[0], reason);
1362 		goto retry;
1363 	}
1364 
1365 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
1366 	    GUC_HXG_TYPE_RESPONSE_FAILURE) {
1367 		u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
1368 		u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
1369 
1370 		xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n",
1371 			  request[0], error, hint);
1372 		return -ENXIO;
1373 	}
1374 
1375 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=
1376 	    GUC_HXG_TYPE_RESPONSE_SUCCESS) {
1377 proto:
1378 		xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n",
1379 			  request[0], header);
1380 		return -EPROTO;
1381 	}
1382 
1383 	/* Just copy entire possible message response */
1384 	if (response_buf) {
1385 		response_buf[0] = header;
1386 
1387 		for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
1388 			reply_reg.addr += sizeof(u32);
1389 			response_buf[i] = xe_mmio_read32(mmio, reply_reg);
1390 		}
1391 	}
1392 
1393 	/* Use data from the GuC response as our return value */
1394 	return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);
1395 }
1396 
xe_guc_mmio_send(struct xe_guc * guc,const u32 * request,u32 len)1397 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)
1398 {
1399 	return xe_guc_mmio_send_recv(guc, request, len, NULL);
1400 }
1401 
guc_self_cfg(struct xe_guc * guc,u16 key,u16 len,u64 val)1402 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val)
1403 {
1404 	struct xe_device *xe = guc_to_xe(guc);
1405 	u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {
1406 		FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
1407 		FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |
1408 		FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION,
1409 			   GUC_ACTION_HOST2GUC_SELF_CFG),
1410 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) |
1411 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len),
1412 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32,
1413 			   lower_32_bits(val)),
1414 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64,
1415 			   upper_32_bits(val)),
1416 	};
1417 	int ret;
1418 
1419 	xe_assert(xe, len <= 2);
1420 	xe_assert(xe, len != 1 || !upper_32_bits(val));
1421 
1422 	/* Self config must go over MMIO */
1423 	ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request));
1424 
1425 	if (unlikely(ret < 0))
1426 		return ret;
1427 	if (unlikely(ret > 1))
1428 		return -EPROTO;
1429 	if (unlikely(!ret))
1430 		return -ENOKEY;
1431 
1432 	return 0;
1433 }
1434 
xe_guc_self_cfg32(struct xe_guc * guc,u16 key,u32 val)1435 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val)
1436 {
1437 	return guc_self_cfg(guc, key, 1, val);
1438 }
1439 
xe_guc_self_cfg64(struct xe_guc * guc,u16 key,u64 val)1440 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val)
1441 {
1442 	return guc_self_cfg(guc, key, 2, val);
1443 }
1444 
xe_guc_sw_0_irq_handler(struct xe_guc * guc)1445 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc)
1446 {
1447 	struct xe_gt *gt = guc_to_gt(guc);
1448 
1449 	if (IS_SRIOV_VF(gt_to_xe(gt)))
1450 		xe_gt_sriov_vf_migrated_event_handler(gt);
1451 }
1452 
xe_guc_irq_handler(struct xe_guc * guc,const u16 iir)1453 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir)
1454 {
1455 	if (iir & GUC_INTR_GUC2HOST)
1456 		xe_guc_ct_irq_handler(&guc->ct);
1457 
1458 	if (iir & GUC_INTR_SW_INT_0)
1459 		xe_guc_sw_0_irq_handler(guc);
1460 }
1461 
xe_guc_sanitize(struct xe_guc * guc)1462 void xe_guc_sanitize(struct xe_guc *guc)
1463 {
1464 	xe_uc_fw_sanitize(&guc->fw);
1465 	xe_guc_ct_disable(&guc->ct);
1466 	guc->submission_state.enabled = false;
1467 }
1468 
xe_guc_reset_prepare(struct xe_guc * guc)1469 int xe_guc_reset_prepare(struct xe_guc *guc)
1470 {
1471 	return xe_guc_submit_reset_prepare(guc);
1472 }
1473 
xe_guc_reset_wait(struct xe_guc * guc)1474 void xe_guc_reset_wait(struct xe_guc *guc)
1475 {
1476 	xe_guc_submit_reset_wait(guc);
1477 }
1478 
xe_guc_stop_prepare(struct xe_guc * guc)1479 void xe_guc_stop_prepare(struct xe_guc *guc)
1480 {
1481 	if (!IS_SRIOV_VF(guc_to_xe(guc))) {
1482 		int err;
1483 
1484 		err = xe_guc_pc_stop(&guc->pc);
1485 		xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n",
1486 			   ERR_PTR(err));
1487 	}
1488 }
1489 
xe_guc_stop(struct xe_guc * guc)1490 void xe_guc_stop(struct xe_guc *guc)
1491 {
1492 	xe_guc_ct_stop(&guc->ct);
1493 
1494 	xe_guc_submit_stop(guc);
1495 }
1496 
xe_guc_start(struct xe_guc * guc)1497 int xe_guc_start(struct xe_guc *guc)
1498 {
1499 	return xe_guc_submit_start(guc);
1500 }
1501 
xe_guc_print_info(struct xe_guc * guc,struct drm_printer * p)1502 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
1503 {
1504 	struct xe_gt *gt = guc_to_gt(guc);
1505 	unsigned int fw_ref;
1506 	u32 status;
1507 	int i;
1508 
1509 	xe_uc_fw_print(&guc->fw, p);
1510 
1511 	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
1512 	if (!fw_ref)
1513 		return;
1514 
1515 	status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
1516 
1517 	drm_printf(p, "\nGuC status 0x%08x:\n", status);
1518 	drm_printf(p, "\tBootrom status = 0x%x\n",
1519 		   REG_FIELD_GET(GS_BOOTROM_MASK, status));
1520 	drm_printf(p, "\tuKernel status = 0x%x\n",
1521 		   REG_FIELD_GET(GS_UKERNEL_MASK, status));
1522 	drm_printf(p, "\tMIA Core status = 0x%x\n",
1523 		   REG_FIELD_GET(GS_MIA_MASK, status));
1524 	drm_printf(p, "\tLog level = %d\n",
1525 		   xe_guc_log_get_level(&guc->log));
1526 
1527 	drm_puts(p, "\nScratch registers:\n");
1528 	for (i = 0; i < SOFT_SCRATCH_COUNT; i++) {
1529 		drm_printf(p, "\t%2d: \t0x%x\n",
1530 			   i, xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(i)));
1531 	}
1532 
1533 	xe_force_wake_put(gt_to_fw(gt), fw_ref);
1534 
1535 	drm_puts(p, "\n");
1536 	xe_guc_ct_print(&guc->ct, p, false);
1537 
1538 	drm_puts(p, "\n");
1539 	xe_guc_submit_print(guc, p);
1540 }
1541 
1542 /**
1543  * xe_guc_declare_wedged() - Declare GuC wedged
1544  * @guc: the GuC object
1545  *
1546  * Wedge the GuC which stops all submission, saves desired debug state, and
1547  * cleans up anything which could timeout.
1548  */
xe_guc_declare_wedged(struct xe_guc * guc)1549 void xe_guc_declare_wedged(struct xe_guc *guc)
1550 {
1551 	xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode);
1552 
1553 	xe_guc_reset_prepare(guc);
1554 	xe_guc_ct_stop(&guc->ct);
1555 	xe_guc_submit_wedge(guc);
1556 }
1557