1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
5 */
6
7 #ifndef WIL6210_TXRX_H
8 #define WIL6210_TXRX_H
9
10 #include <net/sock.h>
11 #include "wil6210.h"
12 #include "txrx_edma.h"
13
14 #define BUF_SW_OWNED (1)
15 #define BUF_HW_OWNED (0)
16
17 /* default size of MAC Tx/Rx buffers */
18 #define TXRX_BUF_LEN_DEFAULT (2048)
19
20 /* how many bytes to reserve for rtap header? */
21 #define WIL6210_RTAP_SIZE (128)
22
23 /* Tx/Rx path */
24
wil_desc_addr(struct wil_ring_dma_addr * addr)25 static inline dma_addr_t wil_desc_addr(struct wil_ring_dma_addr *addr)
26 {
27 return le32_to_cpu(addr->addr_low) |
28 ((u64)le16_to_cpu(addr->addr_high) << 32);
29 }
30
wil_desc_addr_set(struct wil_ring_dma_addr * addr,dma_addr_t pa)31 static inline void wil_desc_addr_set(struct wil_ring_dma_addr *addr,
32 dma_addr_t pa)
33 {
34 addr->addr_low = cpu_to_le32(lower_32_bits(pa));
35 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa));
36 }
37
38 /* Tx descriptor - MAC part
39 * [dword 0]
40 * bit 0.. 9 : lifetime_expiry_value:10
41 * bit 10 : interrupt_en:1
42 * bit 11 : status_en:1
43 * bit 12..13 : txss_override:2
44 * bit 14 : timestamp_insertion:1
45 * bit 15 : duration_preserve:1
46 * bit 16..21 : reserved0:6
47 * bit 22..26 : mcs_index:5
48 * bit 27 : mcs_en:1
49 * bit 28..30 : reserved1:3
50 * bit 31 : sn_preserved:1
51 * [dword 1]
52 * bit 0.. 3 : pkt_mode:4
53 * bit 4 : pkt_mode_en:1
54 * bit 5 : mac_id_en:1
55 * bit 6..7 : mac_id:2
56 * bit 8..14 : reserved0:7
57 * bit 15 : ack_policy_en:1
58 * bit 16..19 : dst_index:4
59 * bit 20 : dst_index_en:1
60 * bit 21..22 : ack_policy:2
61 * bit 23 : lifetime_en:1
62 * bit 24..30 : max_retry:7
63 * bit 31 : max_retry_en:1
64 * [dword 2]
65 * bit 0.. 7 : num_of_descriptors:8
66 * bit 8..17 : reserved:10
67 * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11
68 * bit 20 : snap_hdr_insertion_en:1
69 * bit 21 : vlan_removal_en:1
70 * bit 22..31 : reserved0:10
71 * [dword 3]
72 * bit 0.. 31: ucode_cmd:32
73 */
74 struct vring_tx_mac {
75 u32 d[3];
76 u32 ucode_cmd;
77 } __packed;
78
79 /* TX MAC Dword 0 */
80 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0
81 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10
82 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF
83
84 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10
85 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
86 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400
87
88 #define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11
89 #define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
90 #define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800
91
92 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12
93 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2
94 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000
95
96 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14
97 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
98 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000
99
100 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15
101 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
102 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000
103
104 #define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22
105 #define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5
106 #define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000
107
108 #define MAC_CFG_DESC_TX_0_MCS_EN_POS 27
109 #define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
110 #define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000
111
112 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31
113 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
114 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000
115
116 /* TX MAC Dword 1 */
117 #define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0
118 #define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4
119 #define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF
120
121 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4
122 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
123 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10
124
125 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_POS 5
126 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_LEN 1
127 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_MSK 0x20
128
129 #define MAC_CFG_DESC_TX_1_MAC_ID_POS 6
130 #define MAC_CFG_DESC_TX_1_MAC_ID_LEN 2
131 #define MAC_CFG_DESC_TX_1_MAC_ID_MSK 0xc0
132
133 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15
134 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
135 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000
136
137 #define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16
138 #define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4
139 #define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000
140
141 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20
142 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
143 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000
144
145 #define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21
146 #define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2
147 #define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000
148
149 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23
150 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
151 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000
152
153 #define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24
154 #define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7
155 #define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000
156
157 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31
158 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
159 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000
160
161 /* TX MAC Dword 2 */
162 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0
163 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8
164 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF
165
166 #define MAC_CFG_DESC_TX_2_RESERVED_POS 8
167 #define MAC_CFG_DESC_TX_2_RESERVED_LEN 10
168 #define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00
169
170 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18
171 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2
172 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000
173
174 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20
175 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
176 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000
177
178 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21
179 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
180 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000
181
182 /* TX MAC Dword 3 */
183 #define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0
184 #define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32
185 #define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF
186
187 /* TX DMA Dword 0 */
188 #define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0
189 #define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8
190 #define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF
191
192 #define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8
193 #define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
194 #define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100
195
196 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS 9
197 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1
198 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK 0x200
199
200 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10
201 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
202 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400
203
204 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11
205 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2
206 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800
207
208 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13
209 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
210 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000
211
212 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14
213 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
214 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000
215
216 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15
217 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
218 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000
219
220 #define DMA_CFG_DESC_TX_0_QID_POS 16
221 #define DMA_CFG_DESC_TX_0_QID_LEN 5
222 #define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000
223
224 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21
225 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
226 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000
227
228 #define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30
229 #define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2
230 #define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000 /* L4 type: 0-UDP, 2-TCP */
231
232 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS 0
233 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN 7
234 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK 0x7F /* MAC hdr len */
235
236 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS 7
237 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1
238 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80 /* 1-IPv4, 0-IPv6 */
239
240 #define TX_DMA_STATUS_DU BIT(0)
241
242 /* Tx descriptor - DMA part
243 * [dword 0]
244 * bit 0.. 7 : l4_length:8 layer 4 length
245 * bit 8 : cmd_eop:1 This descriptor is the last one in the packet
246 * bit 9 : reserved
247 * bit 10 : cmd_dma_it:1 immediate interrupt
248 * bit 11..12 : SBD - Segment Buffer Details
249 * 00 - Header Segment
250 * 01 - First Data Segment
251 * 10 - Medium Data Segment
252 * 11 - Last Data Segment
253 * bit 13 : TSE - TCP Segmentation Enable
254 * bit 14 : IIC - Directs the HW to Insert IPv4 Checksum
255 * bit 15 : ITC - Directs the HW to Insert TCP/UDP Checksum
256 * bit 16..20 : QID - The target QID that the packet should be stored
257 * in the MAC.
258 * bit 21 : PO - Pseudo header Offload:
259 * 0 - Use the pseudo header value from the TCP checksum field
260 * 1- Calculate Pseudo header Checksum
261 * bit 22 : NC - No UDP Checksum
262 * bit 23..29 : reserved
263 * bit 30..31 : L4T - Layer 4 Type: 00 - UDP , 10 - TCP , 10, 11 - Reserved
264 * If L4Len equal 0, no L4 at all
265 * [dword 1]
266 * bit 0..31 : addr_low:32 The payload buffer low address
267 * [dword 2]
268 * bit 0..15 : addr_high:16 The payload buffer high address
269 * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum
270 * offload feature
271 * bit 24..30 : mac_length:7
272 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6
273 * [dword 3]
274 * [byte 12] error
275 * bit 0 2 : mac_status:3
276 * bit 3 7 : reserved:5
277 * [byte 13] status
278 * bit 0 : DU:1 Descriptor Used
279 * bit 1 7 : reserved:7
280 * [word 7] length
281 */
282 struct vring_tx_dma {
283 u32 d0;
284 struct wil_ring_dma_addr addr;
285 u8 ip_length;
286 u8 b11; /* 0..6: mac_length; 7:ip_version */
287 u8 error; /* 0..2: err; 3..7: reserved; */
288 u8 status; /* 0: used; 1..7; reserved */
289 __le16 length;
290 } __packed;
291
292 /* TSO type used in dma descriptor d0 bits 11-12 */
293 enum {
294 wil_tso_type_hdr = 0,
295 wil_tso_type_first = 1,
296 wil_tso_type_mid = 2,
297 wil_tso_type_lst = 3,
298 };
299
300 /* Rx descriptor - MAC part
301 * [dword 0]
302 * bit 0.. 3 : tid:4 The QoS (b3-0) TID Field
303 * bit 4.. 6 : cid:3 The Source index that was found during parsing the TA.
304 * This field is used to define the source of the packet
305 * bit 7 : MAC_id_valid:1, 1 if MAC virtual number is valid.
306 * bit 8.. 9 : mid:2 The MAC virtual number
307 * bit 10..11 : frame_type:2 : The FC (b3-2) - MPDU Type
308 * (management, data, control and extension)
309 * bit 12..15 : frame_subtype:4 : The FC (b7-4) - Frame Subtype
310 * bit 16..27 : seq_number:12 The received Sequence number field
311 * bit 28..31 : extended:4 extended subtype
312 * [dword 1]
313 * bit 0.. 3 : reserved
314 * bit 4.. 5 : key_id:2
315 * bit 6 : decrypt_bypass:1
316 * bit 7 : security:1 FC (b14)
317 * bit 8.. 9 : ds_bits:2 FC (b9-8)
318 * bit 10 : a_msdu_present:1 QoS (b7)
319 * bit 11 : a_msdu_type:1 QoS (b8)
320 * bit 12 : a_mpdu:1 part of AMPDU aggregation
321 * bit 13 : broadcast:1
322 * bit 14 : mutlicast:1
323 * bit 15 : reserved:1
324 * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet
325 * is received from
326 * bit 21..24 : mcs:4
327 * bit 25..28 : mic_icr:4 this signal tells the DMA to assert an interrupt
328 * after it writes the packet
329 * bit 29..31 : reserved:3
330 * [dword 2]
331 * bit 0.. 2 : time_slot:3 The timeslot that the MPDU is received
332 * bit 3.. 4 : fc_protocol_ver:1 The FC (b1-0) - Protocol Version
333 * bit 5 : fc_order:1 The FC Control (b15) -Order
334 * bit 6.. 7 : qos_ack_policy:2 The QoS (b6-5) ack policy Field
335 * bit 8 : esop:1 The QoS (b4) ESOP field
336 * bit 9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field
337 * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field
338 * bit 15 : qos_ac_constraint:1 QoS (b15)
339 * bit 16..31 : pn_15_0:16 low 2 bytes of PN
340 * [dword 3]
341 * bit 0..31 : pn_47_16:32 high 4 bytes of PN
342 */
343 struct vring_rx_mac {
344 u32 d0;
345 u32 d1;
346 u16 w4;
347 struct_group_attr(pn, __packed,
348 u16 pn_15_0;
349 u32 pn_47_16;
350 );
351 } __packed;
352
353 /* Rx descriptor - DMA part
354 * [dword 0]
355 * bit 0.. 7 : l4_length:8 layer 4 length. The field is only valid if
356 * L4I bit is set
357 * bit 8 : cmd_eop:1 set to 1
358 * bit 9 : cmd_rt:1 set to 1
359 * bit 10 : cmd_dma_it:1 immediate interrupt
360 * bit 11..15 : reserved:5
361 * bit 16..29 : phy_info_length:14 It is valid when the PII is set.
362 * When the FFM bit is set bits 29-27 are used for
363 * Flex Filter Match. Matching Index to one of the L2
364 * EtherType Flex Filter
365 * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
366 * 00 - UDP, 01 - TCP, 10, 11 - reserved
367 * [dword 1]
368 * bit 0..31 : addr_low:32 The payload buffer low address
369 * [dword 2]
370 * bit 0..15 : addr_high:16 The payload buffer high address
371 * bit 16..23 : ip_length:8 The filed is valid only if the L3I bit is set
372 * bit 24..30 : mac_length:7
373 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6
374 * [dword 3]
375 * [byte 12] error
376 * bit 0 : FCS:1
377 * bit 1 : MIC:1
378 * bit 2 : Key miss:1
379 * bit 3 : Replay:1
380 * bit 4 : L3:1 IPv4 checksum
381 * bit 5 : L4:1 TCP/UDP checksum
382 * bit 6 7 : reserved:2
383 * [byte 13] status
384 * bit 0 : DU:1 Descriptor Used
385 * bit 1 : EOP:1 The descriptor indicates the End of Packet
386 * bit 2 : error:1
387 * bit 3 : MI:1 MAC Interrupt is asserted (according to parser decision)
388 * bit 4 : L3I:1 L3 identified and checksum calculated
389 * bit 5 : L4I:1 L4 identified and checksum calculated
390 * bit 6 : PII:1 PHY Info Included in the packet
391 * bit 7 : FFM:1 EtherType Flex Filter Match
392 * [word 7] length
393 */
394
395 #define RX_DMA_D0_CMD_DMA_EOP BIT(8)
396 #define RX_DMA_D0_CMD_DMA_RT BIT(9) /* always 1 */
397 #define RX_DMA_D0_CMD_DMA_IT BIT(10) /* interrupt */
398 #define RX_MAC_D0_MAC_ID_VALID BIT(7)
399
400 /* Error field */
401 #define RX_DMA_ERROR_FCS BIT(0)
402 #define RX_DMA_ERROR_MIC BIT(1)
403 #define RX_DMA_ERROR_KEY BIT(2) /* Key missing */
404 #define RX_DMA_ERROR_REPLAY BIT(3)
405 #define RX_DMA_ERROR_L3_ERR BIT(4)
406 #define RX_DMA_ERROR_L4_ERR BIT(5)
407
408 /* Status field */
409 #define RX_DMA_STATUS_DU BIT(0)
410 #define RX_DMA_STATUS_EOP BIT(1)
411 #define RX_DMA_STATUS_ERROR BIT(2)
412 #define RX_DMA_STATUS_MI BIT(3) /* MAC Interrupt is asserted */
413 #define RX_DMA_STATUS_L3I BIT(4)
414 #define RX_DMA_STATUS_L4I BIT(5)
415 #define RX_DMA_STATUS_PHY_INFO BIT(6)
416 #define RX_DMA_STATUS_FFM BIT(7) /* EtherType Flex Filter Match */
417
418 /* IEEE 802.11, 8.5.2 EAPOL-Key frames */
419 #define WIL_KEY_INFO_KEY_TYPE BIT(3) /* val of 1 = Pairwise, 0 = Group key */
420
421 #define WIL_KEY_INFO_MIC BIT(8)
422 #define WIL_KEY_INFO_ENCR_KEY_DATA BIT(12) /* for rsn only */
423
424 #define WIL_EAP_NONCE_LEN 32
425 #define WIL_EAP_KEY_RSC_LEN 8
426 #define WIL_EAP_REPLAY_COUNTER_LEN 8
427 #define WIL_EAP_KEY_IV_LEN 16
428 #define WIL_EAP_KEY_ID_LEN 8
429
430 enum {
431 WIL_1X_TYPE_EAP_PACKET = 0,
432 WIL_1X_TYPE_EAPOL_START = 1,
433 WIL_1X_TYPE_EAPOL_LOGOFF = 2,
434 WIL_1X_TYPE_EAPOL_KEY = 3,
435 };
436
437 #define WIL_EAPOL_KEY_TYPE_RSN 2
438 #define WIL_EAPOL_KEY_TYPE_WPA 254
439
440 struct wil_1x_hdr {
441 u8 version;
442 u8 type;
443 __be16 length;
444 /* followed by data */
445 } __packed;
446
447 struct wil_eapol_key {
448 u8 type;
449 __be16 key_info;
450 __be16 key_length;
451 u8 replay_counter[WIL_EAP_REPLAY_COUNTER_LEN];
452 u8 key_nonce[WIL_EAP_NONCE_LEN];
453 u8 key_iv[WIL_EAP_KEY_IV_LEN];
454 u8 key_rsc[WIL_EAP_KEY_RSC_LEN];
455 u8 key_id[WIL_EAP_KEY_ID_LEN];
456 } __packed;
457
458 struct vring_rx_dma {
459 u32 d0;
460 struct wil_ring_dma_addr addr;
461 u8 ip_length;
462 u8 b11;
463 u8 error;
464 u8 status;
465 __le16 length;
466 } __packed;
467
468 struct vring_tx_desc {
469 struct vring_tx_mac mac;
470 struct vring_tx_dma dma;
471 } __packed;
472
473 union wil_tx_desc {
474 struct vring_tx_desc legacy;
475 struct wil_tx_enhanced_desc enhanced;
476 } __packed;
477
478 struct vring_rx_desc {
479 struct vring_rx_mac mac;
480 struct vring_rx_dma dma;
481 } __packed;
482
483 union wil_rx_desc {
484 struct vring_rx_desc legacy;
485 struct wil_rx_enhanced_desc enhanced;
486 } __packed;
487
488 union wil_ring_desc {
489 union wil_tx_desc tx;
490 union wil_rx_desc rx;
491 } __packed;
492
493 struct packet_rx_info {
494 u8 cid;
495 };
496
497 /* this struct will be stored in the skb cb buffer
498 * max length of the struct is limited to 48 bytes
499 */
500 struct skb_rx_info {
501 struct vring_rx_desc rx_desc;
502 struct packet_rx_info rx_info;
503 };
504
wil_rxdesc_tid(struct vring_rx_desc * d)505 static inline int wil_rxdesc_tid(struct vring_rx_desc *d)
506 {
507 return WIL_GET_BITS(d->mac.d0, 0, 3);
508 }
509
wil_rxdesc_cid(struct vring_rx_desc * d)510 static inline int wil_rxdesc_cid(struct vring_rx_desc *d)
511 {
512 return WIL_GET_BITS(d->mac.d0, 4, 6);
513 }
514
wil_rxdesc_mid(struct vring_rx_desc * d)515 static inline int wil_rxdesc_mid(struct vring_rx_desc *d)
516 {
517 return (d->mac.d0 & RX_MAC_D0_MAC_ID_VALID) ?
518 WIL_GET_BITS(d->mac.d0, 8, 9) : 0;
519 }
520
wil_rxdesc_ftype(struct vring_rx_desc * d)521 static inline int wil_rxdesc_ftype(struct vring_rx_desc *d)
522 {
523 return WIL_GET_BITS(d->mac.d0, 10, 11);
524 }
525
wil_rxdesc_subtype(struct vring_rx_desc * d)526 static inline int wil_rxdesc_subtype(struct vring_rx_desc *d)
527 {
528 return WIL_GET_BITS(d->mac.d0, 12, 15);
529 }
530
531 /* 1-st byte (with frame type/subtype) of FC field */
wil_rxdesc_fc1(struct vring_rx_desc * d)532 static inline u8 wil_rxdesc_fc1(struct vring_rx_desc *d)
533 {
534 return (u8)(WIL_GET_BITS(d->mac.d0, 10, 15) << 2);
535 }
536
wil_rxdesc_seq(struct vring_rx_desc * d)537 static inline int wil_rxdesc_seq(struct vring_rx_desc *d)
538 {
539 return WIL_GET_BITS(d->mac.d0, 16, 27);
540 }
541
wil_rxdesc_ext_subtype(struct vring_rx_desc * d)542 static inline int wil_rxdesc_ext_subtype(struct vring_rx_desc *d)
543 {
544 return WIL_GET_BITS(d->mac.d0, 28, 31);
545 }
546
wil_rxdesc_retry(struct vring_rx_desc * d)547 static inline int wil_rxdesc_retry(struct vring_rx_desc *d)
548 {
549 return WIL_GET_BITS(d->mac.d0, 31, 31);
550 }
551
wil_rxdesc_key_id(struct vring_rx_desc * d)552 static inline int wil_rxdesc_key_id(struct vring_rx_desc *d)
553 {
554 return WIL_GET_BITS(d->mac.d1, 4, 5);
555 }
556
wil_rxdesc_security(struct vring_rx_desc * d)557 static inline int wil_rxdesc_security(struct vring_rx_desc *d)
558 {
559 return WIL_GET_BITS(d->mac.d1, 7, 7);
560 }
561
wil_rxdesc_ds_bits(struct vring_rx_desc * d)562 static inline int wil_rxdesc_ds_bits(struct vring_rx_desc *d)
563 {
564 return WIL_GET_BITS(d->mac.d1, 8, 9);
565 }
566
wil_rxdesc_mcs(struct vring_rx_desc * d)567 static inline int wil_rxdesc_mcs(struct vring_rx_desc *d)
568 {
569 return WIL_GET_BITS(d->mac.d1, 21, 24);
570 }
571
wil_rxdesc_mcast(struct vring_rx_desc * d)572 static inline int wil_rxdesc_mcast(struct vring_rx_desc *d)
573 {
574 return WIL_GET_BITS(d->mac.d1, 13, 14);
575 }
576
wil_skb_rxdesc(struct sk_buff * skb)577 static inline struct vring_rx_desc *wil_skb_rxdesc(struct sk_buff *skb)
578 {
579 return (void *)skb->cb;
580 }
581
wil_ring_is_empty(struct wil_ring * ring)582 static inline int wil_ring_is_empty(struct wil_ring *ring)
583 {
584 return ring->swhead == ring->swtail;
585 }
586
wil_ring_next_tail(struct wil_ring * ring)587 static inline u32 wil_ring_next_tail(struct wil_ring *ring)
588 {
589 return (ring->swtail + 1) % ring->size;
590 }
591
wil_ring_advance_head(struct wil_ring * ring,int n)592 static inline void wil_ring_advance_head(struct wil_ring *ring, int n)
593 {
594 ring->swhead = (ring->swhead + n) % ring->size;
595 }
596
wil_ring_is_full(struct wil_ring * ring)597 static inline int wil_ring_is_full(struct wil_ring *ring)
598 {
599 return wil_ring_next_tail(ring) == ring->swhead;
600 }
601
wil_skb_get_da(struct sk_buff * skb)602 static inline u8 *wil_skb_get_da(struct sk_buff *skb)
603 {
604 struct ethhdr *eth = (void *)skb->data;
605
606 return eth->h_dest;
607 }
608
wil_skb_get_sa(struct sk_buff * skb)609 static inline u8 *wil_skb_get_sa(struct sk_buff *skb)
610 {
611 struct ethhdr *eth = (void *)skb->data;
612
613 return eth->h_source;
614 }
615
wil_need_txstat(struct sk_buff * skb)616 static inline bool wil_need_txstat(struct sk_buff *skb)
617 {
618 const u8 *da = wil_skb_get_da(skb);
619
620 return is_unicast_ether_addr(da) && sk_requests_wifi_status(skb->sk);
621 }
622
wil_consume_skb(struct sk_buff * skb,bool acked)623 static inline void wil_consume_skb(struct sk_buff *skb, bool acked)
624 {
625 if (unlikely(wil_need_txstat(skb)))
626 skb_complete_wifi_ack(skb, acked);
627 else
628 acked ? dev_consume_skb_any(skb) : dev_kfree_skb_any(skb);
629 }
630
631 /* Used space in Tx ring */
wil_ring_used_tx(struct wil_ring * ring)632 static inline int wil_ring_used_tx(struct wil_ring *ring)
633 {
634 u32 swhead = ring->swhead;
635 u32 swtail = ring->swtail;
636
637 return (ring->size + swhead - swtail) % ring->size;
638 }
639
640 /* Available space in Tx ring */
wil_ring_avail_tx(struct wil_ring * ring)641 static inline int wil_ring_avail_tx(struct wil_ring *ring)
642 {
643 return ring->size - wil_ring_used_tx(ring) - 1;
644 }
645
wil_get_min_tx_ring_id(struct wil6210_priv * wil)646 static inline int wil_get_min_tx_ring_id(struct wil6210_priv *wil)
647 {
648 /* In Enhanced DMA ring 0 is reserved for RX */
649 return wil->use_enhanced_dma_hw ? 1 : 0;
650 }
651
652 /* similar to ieee80211_ version, but FC contain only 1-st byte */
wil_is_back_req(u8 fc)653 static inline int wil_is_back_req(u8 fc)
654 {
655 return (fc & (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) ==
656 (IEEE80211_FTYPE_CTL | IEEE80211_STYPE_BACK_REQ);
657 }
658
659 /* wil_val_in_range - check if value in [min,max) */
wil_val_in_range(int val,int min,int max)660 static inline bool wil_val_in_range(int val, int min, int max)
661 {
662 return val >= min && val < max;
663 }
664
wil_skb_get_cid(struct sk_buff * skb)665 static inline u8 wil_skb_get_cid(struct sk_buff *skb)
666 {
667 struct skb_rx_info *skb_rx_info = (void *)skb->cb;
668
669 return skb_rx_info->rx_info.cid;
670 }
671
wil_skb_set_cid(struct sk_buff * skb,u8 cid)672 static inline void wil_skb_set_cid(struct sk_buff *skb, u8 cid)
673 {
674 struct skb_rx_info *skb_rx_info = (void *)skb->cb;
675
676 skb_rx_info->rx_info.cid = cid;
677 }
678
679 void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev);
680 void wil_netif_rx(struct sk_buff *skb, struct net_device *ndev, int cid,
681 struct wil_net_stats *stats, bool gro);
682 void wil_rx_reorder(struct wil6210_priv *wil, struct sk_buff *skb);
683 void wil_rx_bar(struct wil6210_priv *wil, struct wil6210_vif *vif,
684 u8 cid, u8 tid, u16 seq);
685 struct wil_tid_ampdu_rx *wil_tid_ampdu_rx_alloc(struct wil6210_priv *wil,
686 int size, u16 ssn);
687 void wil_tid_ampdu_rx_free(struct wil6210_priv *wil,
688 struct wil_tid_ampdu_rx *r);
689 void wil_tx_data_init(struct wil_ring_tx_data *txdata);
690 void wil_init_txrx_ops_legacy_dma(struct wil6210_priv *wil);
691 void wil_tx_latency_calc(struct wil6210_priv *wil, struct sk_buff *skb,
692 struct wil_sta_info *sta);
693
694 #endif /* WIL6210_TXRX_H */
695