1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "coredump.h" 7 #include "mt7915.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 13 14 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 15 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 16 .radar_pattern = { 17 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 18 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 19 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 20 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 21 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 22 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 23 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 24 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 25 }, 26 }; 27 28 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 29 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 30 .radar_pattern = { 31 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 32 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 33 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 34 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 35 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 36 }, 37 }; 38 39 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 40 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 41 .radar_pattern = { 42 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 43 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 44 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 45 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 46 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 47 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 48 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 49 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 50 }, 51 }; 52 53 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 54 u16 idx, bool unicast) 55 { 56 struct mt7915_sta *sta; 57 struct mt76_wcid *wcid; 58 59 wcid = mt76_wcid_ptr(dev, idx); 60 if (unicast || !wcid) 61 return wcid; 62 63 if (!wcid->sta) 64 return NULL; 65 66 sta = container_of(wcid, struct mt7915_sta, wcid); 67 if (!sta->vif) 68 return NULL; 69 70 return &sta->vif->sta.wcid; 71 } 72 73 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 74 { 75 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 76 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 77 78 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 79 0, 5000); 80 } 81 82 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 83 { 84 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 85 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 86 87 return MT_WTBL_LMAC_OFFS(wcid, dw); 88 } 89 90 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 91 { 92 static const u8 ac_to_tid[] = { 93 [IEEE80211_AC_BE] = 0, 94 [IEEE80211_AC_BK] = 1, 95 [IEEE80211_AC_VI] = 4, 96 [IEEE80211_AC_VO] = 6 97 }; 98 struct ieee80211_sta *sta; 99 struct mt7915_sta *msta; 100 struct rate_info *rate; 101 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 102 LIST_HEAD(sta_poll_list); 103 int i; 104 105 spin_lock_bh(&dev->mt76.sta_poll_lock); 106 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 107 spin_unlock_bh(&dev->mt76.sta_poll_lock); 108 109 rcu_read_lock(); 110 111 while (true) { 112 bool clear = false; 113 u32 addr, val; 114 u16 idx; 115 s8 rssi[4]; 116 u8 bw; 117 118 spin_lock_bh(&dev->mt76.sta_poll_lock); 119 if (list_empty(&sta_poll_list)) { 120 spin_unlock_bh(&dev->mt76.sta_poll_lock); 121 break; 122 } 123 msta = list_first_entry(&sta_poll_list, 124 struct mt7915_sta, wcid.poll_list); 125 list_del_init(&msta->wcid.poll_list); 126 spin_unlock_bh(&dev->mt76.sta_poll_lock); 127 128 idx = msta->wcid.idx; 129 130 /* refresh peer's airtime reporting */ 131 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 132 133 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 134 u32 tx_last = msta->airtime_ac[i]; 135 u32 rx_last = msta->airtime_ac[i + 4]; 136 137 msta->airtime_ac[i] = mt76_rr(dev, addr); 138 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 139 140 if (msta->airtime_ac[i] <= tx_last) 141 tx_time[i] = 0; 142 else 143 tx_time[i] = msta->airtime_ac[i] - tx_last; 144 145 if (msta->airtime_ac[i + 4] <= rx_last) 146 rx_time[i] = 0; 147 else 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 queue = mt76_connac_lmac_mapping(i); 169 u32 tx_cur = tx_time[queue]; 170 u32 rx_cur = rx_time[queue]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 217 /* get signal strength of resp frames (CTS/BA/ACK) */ 218 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 219 val = mt76_rr(dev, addr); 220 221 rssi[0] = to_rssi(GENMASK(7, 0), val); 222 rssi[1] = to_rssi(GENMASK(15, 8), val); 223 rssi[2] = to_rssi(GENMASK(23, 16), val); 224 rssi[3] = to_rssi(GENMASK(31, 14), val); 225 226 msta->ack_signal = 227 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 228 229 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 230 } 231 232 rcu_read_unlock(); 233 } 234 235 static void 236 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 237 struct mt7915_sta *msta, struct sk_buff *skb, 238 u32 info) 239 { 240 struct ieee80211_vif *vif; 241 struct wireless_dev *wdev; 242 243 if (!msta || !msta->vif) 244 return; 245 246 if (!mt76_queue_is_wed_rx(q)) 247 return; 248 249 if (!(info & MT_DMA_INFO_PPE_VLD)) 250 return; 251 252 vif = container_of((void *)msta->vif, struct ieee80211_vif, 253 drv_priv); 254 wdev = ieee80211_vif_to_wdev(vif); 255 skb->dev = wdev->netdev; 256 257 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 258 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 259 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 260 } 261 262 static int 263 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 264 enum mt76_rxq_id q, u32 *info) 265 { 266 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 267 struct mt76_phy *mphy = &dev->mt76.phy; 268 struct mt7915_phy *phy = &dev->phy; 269 struct ieee80211_supported_band *sband; 270 __le32 *rxd = (__le32 *)skb->data; 271 __le32 *rxv = NULL; 272 u32 rxd0 = le32_to_cpu(rxd[0]); 273 u32 rxd1 = le32_to_cpu(rxd[1]); 274 u32 rxd2 = le32_to_cpu(rxd[2]); 275 u32 rxd3 = le32_to_cpu(rxd[3]); 276 u32 rxd4 = le32_to_cpu(rxd[4]); 277 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 278 bool unicast, insert_ccmp_hdr = false; 279 u8 remove_pad, amsdu_info; 280 u8 mode = 0, qos_ctl = 0; 281 struct mt7915_sta *msta = NULL; 282 u32 csum_status = *(u32 *)skb->cb; 283 bool hdr_trans; 284 u16 hdr_gap; 285 u16 seq_ctrl = 0; 286 __le16 fc = 0; 287 int idx; 288 289 memset(status, 0, sizeof(*status)); 290 291 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 292 mphy = dev->mt76.phys[MT_BAND1]; 293 if (!mphy) 294 return -EINVAL; 295 296 phy = mphy->priv; 297 status->phy_idx = 1; 298 } 299 300 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 301 return -EINVAL; 302 303 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 304 return -EINVAL; 305 306 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 307 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 308 return -EINVAL; 309 310 /* ICV error or CCMP/BIP/WPI MIC error */ 311 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 312 status->flag |= RX_FLAG_ONLY_MONITOR; 313 314 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 315 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 316 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 317 318 if (status->wcid) { 319 msta = container_of(status->wcid, struct mt7915_sta, wcid); 320 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 321 } 322 323 status->freq = mphy->chandef.chan->center_freq; 324 status->band = mphy->chandef.chan->band; 325 if (status->band == NL80211_BAND_5GHZ) 326 sband = &mphy->sband_5g.sband; 327 else if (status->band == NL80211_BAND_6GHZ) 328 sband = &mphy->sband_6g.sband; 329 else 330 sband = &mphy->sband_2g.sband; 331 332 if (!sband->channels) 333 return -EINVAL; 334 335 if ((rxd0 & csum_mask) == csum_mask && 336 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 337 skb->ip_summed = CHECKSUM_UNNECESSARY; 338 339 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 340 status->flag |= RX_FLAG_FAILED_FCS_CRC; 341 342 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 343 status->flag |= RX_FLAG_MMIC_ERROR; 344 345 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 346 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 347 status->flag |= RX_FLAG_DECRYPTED; 348 status->flag |= RX_FLAG_IV_STRIPPED; 349 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 350 } 351 352 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 353 354 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 355 return -EINVAL; 356 357 rxd += 6; 358 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 359 u32 v0 = le32_to_cpu(rxd[0]); 360 u32 v2 = le32_to_cpu(rxd[2]); 361 362 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 363 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 364 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 365 366 rxd += 4; 367 if ((u8 *)rxd - skb->data >= skb->len) 368 return -EINVAL; 369 } 370 371 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 372 u8 *data = (u8 *)rxd; 373 374 if (status->flag & RX_FLAG_DECRYPTED) { 375 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 376 case MT_CIPHER_AES_CCMP: 377 case MT_CIPHER_CCMP_CCX: 378 case MT_CIPHER_CCMP_256: 379 insert_ccmp_hdr = 380 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 381 fallthrough; 382 case MT_CIPHER_TKIP: 383 case MT_CIPHER_TKIP_NO_MIC: 384 case MT_CIPHER_GCMP: 385 case MT_CIPHER_GCMP_256: 386 status->iv[0] = data[5]; 387 status->iv[1] = data[4]; 388 status->iv[2] = data[3]; 389 status->iv[3] = data[2]; 390 status->iv[4] = data[1]; 391 status->iv[5] = data[0]; 392 break; 393 default: 394 break; 395 } 396 } 397 rxd += 4; 398 if ((u8 *)rxd - skb->data >= skb->len) 399 return -EINVAL; 400 } 401 402 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 403 status->timestamp = le32_to_cpu(rxd[0]); 404 status->flag |= RX_FLAG_MACTIME_START; 405 406 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 407 status->flag |= RX_FLAG_AMPDU_DETAILS; 408 409 /* all subframes of an A-MPDU have the same timestamp */ 410 if (phy->rx_ampdu_ts != status->timestamp) { 411 if (!++phy->ampdu_ref) 412 phy->ampdu_ref++; 413 } 414 phy->rx_ampdu_ts = status->timestamp; 415 416 status->ampdu_ref = phy->ampdu_ref; 417 } 418 419 rxd += 2; 420 if ((u8 *)rxd - skb->data >= skb->len) 421 return -EINVAL; 422 } 423 424 /* RXD Group 3 - P-RXV */ 425 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 426 u32 v0, v1; 427 int ret; 428 429 rxv = rxd; 430 rxd += 2; 431 if ((u8 *)rxd - skb->data >= skb->len) 432 return -EINVAL; 433 434 v0 = le32_to_cpu(rxv[0]); 435 v1 = le32_to_cpu(rxv[1]); 436 437 if (v0 & MT_PRXV_HT_AD_CODE) 438 status->enc_flags |= RX_ENC_FLAG_LDPC; 439 440 status->chains = mphy->antenna_mask; 441 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 442 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 443 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 444 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 445 446 /* RXD Group 5 - C-RXV */ 447 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 448 rxd += 18; 449 if ((u8 *)rxd - skb->data >= skb->len) 450 return -EINVAL; 451 } 452 453 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 454 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 455 sband, rxv, &mode); 456 if (ret < 0) 457 return ret; 458 } 459 } 460 461 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 462 status->amsdu = !!amsdu_info; 463 if (status->amsdu) { 464 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 465 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 466 } 467 468 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 469 if (hdr_trans && ieee80211_has_morefrags(fc)) { 470 struct ieee80211_vif *vif; 471 int err; 472 473 if (!msta || !msta->vif) 474 return -EINVAL; 475 476 vif = container_of((void *)msta->vif, struct ieee80211_vif, 477 drv_priv); 478 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 479 if (err) 480 return err; 481 482 hdr_trans = false; 483 } else { 484 int pad_start = 0; 485 486 skb_pull(skb, hdr_gap); 487 if (!hdr_trans && status->amsdu) { 488 pad_start = ieee80211_get_hdrlen_from_skb(skb); 489 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 490 /* 491 * When header translation failure is indicated, 492 * the hardware will insert an extra 2-byte field 493 * containing the data length after the protocol 494 * type field. This happens either when the LLC-SNAP 495 * pattern did not match, or if a VLAN header was 496 * detected. 497 */ 498 pad_start = 12; 499 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 500 pad_start += 4; 501 else 502 pad_start = 0; 503 } 504 505 if (pad_start) { 506 memmove(skb->data + 2, skb->data, pad_start); 507 skb_pull(skb, 2); 508 } 509 } 510 511 if (!hdr_trans) { 512 struct ieee80211_hdr *hdr; 513 514 if (insert_ccmp_hdr) { 515 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 516 517 mt76_insert_ccmp_hdr(skb, key_id); 518 } 519 520 hdr = mt76_skb_get_hdr(skb); 521 fc = hdr->frame_control; 522 if (ieee80211_is_data_qos(fc)) { 523 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 524 qos_ctl = *ieee80211_get_qos_ctl(hdr); 525 } 526 } else { 527 status->flag |= RX_FLAG_8023; 528 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 529 *info); 530 } 531 532 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 533 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 534 535 if (!status->wcid || !ieee80211_is_data_qos(fc)) 536 return 0; 537 538 status->aggr = unicast && 539 !ieee80211_is_qos_nullfunc(fc); 540 status->qos_ctl = qos_ctl; 541 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 542 543 return 0; 544 } 545 546 static void 547 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 548 { 549 #ifdef CONFIG_NL80211_TESTMODE 550 struct mt7915_phy *phy = &dev->phy; 551 __le32 *rxd = (__le32 *)skb->data; 552 __le32 *rxv_hdr = rxd + 2; 553 __le32 *rxv = rxd + 4; 554 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 555 u8 band_idx; 556 s32 foe; 557 u8 snr; 558 int i; 559 560 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 561 if (band_idx && !phy->mt76->band_idx) { 562 phy = mt7915_ext_phy(dev); 563 if (!phy) 564 goto out; 565 } 566 567 rcpi = le32_to_cpu(rxv[6]); 568 ib_rssi = le32_to_cpu(rxv[7]); 569 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 570 571 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 572 if (i == 3) 573 wb_rssi = le32_to_cpu(rxv[9]); 574 575 phy->test.last_rcpi[i] = rcpi & 0xff; 576 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 577 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 578 } 579 580 v20 = le32_to_cpu(rxv[20]); 581 v21 = le32_to_cpu(rxv[21]); 582 583 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 584 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 585 586 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 587 588 phy->test.last_freq_offset = foe; 589 phy->test.last_snr = snr; 590 out: 591 #endif 592 dev_kfree_skb(skb); 593 } 594 595 static void 596 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 597 struct sk_buff *skb) 598 { 599 #ifdef CONFIG_NL80211_TESTMODE 600 struct mt76_testmode_data *td = &phy->mt76->test; 601 const struct ieee80211_rate *r; 602 u8 bw, mode, nss = td->tx_rate_nss; 603 u8 rate_idx = td->tx_rate_idx; 604 u16 rateval = 0; 605 u32 val; 606 bool cck = false; 607 int band; 608 609 if (skb != phy->mt76->test.tx_skb) 610 return; 611 612 switch (td->tx_rate_mode) { 613 case MT76_TM_TX_MODE_HT: 614 nss = 1 + (rate_idx >> 3); 615 mode = MT_PHY_TYPE_HT; 616 break; 617 case MT76_TM_TX_MODE_VHT: 618 mode = MT_PHY_TYPE_VHT; 619 break; 620 case MT76_TM_TX_MODE_HE_SU: 621 mode = MT_PHY_TYPE_HE_SU; 622 break; 623 case MT76_TM_TX_MODE_HE_EXT_SU: 624 mode = MT_PHY_TYPE_HE_EXT_SU; 625 break; 626 case MT76_TM_TX_MODE_HE_TB: 627 mode = MT_PHY_TYPE_HE_TB; 628 break; 629 case MT76_TM_TX_MODE_HE_MU: 630 mode = MT_PHY_TYPE_HE_MU; 631 break; 632 case MT76_TM_TX_MODE_CCK: 633 cck = true; 634 fallthrough; 635 case MT76_TM_TX_MODE_OFDM: 636 band = phy->mt76->chandef.chan->band; 637 if (band == NL80211_BAND_2GHZ && !cck) 638 rate_idx += 4; 639 640 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 641 val = cck ? r->hw_value_short : r->hw_value; 642 643 mode = val >> 8; 644 rate_idx = val & 0xff; 645 break; 646 default: 647 mode = MT_PHY_TYPE_OFDM; 648 break; 649 } 650 651 switch (phy->mt76->chandef.width) { 652 case NL80211_CHAN_WIDTH_40: 653 bw = 1; 654 break; 655 case NL80211_CHAN_WIDTH_80: 656 bw = 2; 657 break; 658 case NL80211_CHAN_WIDTH_80P80: 659 case NL80211_CHAN_WIDTH_160: 660 bw = 3; 661 break; 662 default: 663 bw = 0; 664 break; 665 } 666 667 if (td->tx_rate_stbc && nss == 1) { 668 nss++; 669 rateval |= MT_TX_RATE_STBC; 670 } 671 672 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 673 FIELD_PREP(MT_TX_RATE_MODE, mode) | 674 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 675 676 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 677 678 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 679 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 680 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 681 682 val = MT_TXD6_FIXED_BW | 683 FIELD_PREP(MT_TXD6_BW, bw) | 684 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 685 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 686 687 /* for HE_SU/HE_EXT_SU PPDU 688 * - 1x, 2x, 4x LTF + 0.8us GI 689 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 690 * for HE_MU PPDU 691 * - 2x, 4x LTF + 0.8us GI 692 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 693 * for HE_TB PPDU 694 * - 1x, 2x LTF + 1.6us GI 695 * - 4x LTF + 3.2us GI 696 */ 697 if (mode >= MT_PHY_TYPE_HE_SU) 698 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 699 700 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 701 val |= MT_TXD6_LDPC; 702 703 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 704 txwi[6] |= cpu_to_le32(val); 705 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 706 phy->test.spe_idx)); 707 #endif 708 } 709 710 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 711 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 712 struct ieee80211_key_conf *key, 713 enum mt76_txq_id qid, u32 changed) 714 { 715 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 716 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 717 struct mt76_phy *mphy = &dev->phy; 718 719 if (phy_idx && dev->phys[MT_BAND1]) 720 mphy = dev->phys[MT_BAND1]; 721 722 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 723 724 if (mt76_testmode_enabled(mphy)) 725 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 726 } 727 728 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 729 enum mt76_txq_id qid, struct mt76_wcid *wcid, 730 struct ieee80211_sta *sta, 731 struct mt76_tx_info *tx_info) 732 { 733 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 734 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 735 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 736 struct ieee80211_key_conf *key = info->control.hw_key; 737 struct ieee80211_vif *vif = info->control.vif; 738 struct mt76_connac_fw_txp *txp; 739 struct mt76_txwi_cache *t; 740 int id, i, nbuf = tx_info->nbuf - 1; 741 u8 *txwi = (u8 *)txwi_ptr; 742 int pid; 743 744 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 745 return -EINVAL; 746 747 if (!wcid) 748 wcid = &dev->mt76.global_wcid; 749 750 if (sta) { 751 struct mt7915_sta *msta; 752 753 msta = (struct mt7915_sta *)sta->drv_priv; 754 755 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 756 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 757 msta->jiffies = jiffies; 758 } 759 } 760 761 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 762 t->skb = tx_info->skb; 763 764 id = mt76_token_consume(mdev, &t); 765 if (id < 0) 766 return id; 767 768 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 769 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 770 qid, 0); 771 772 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 773 for (i = 0; i < nbuf; i++) { 774 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 775 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 776 } 777 txp->nbuf = nbuf; 778 779 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 780 781 if (!key) 782 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 783 784 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 785 ieee80211_is_mgmt(hdr->frame_control)) 786 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 787 788 if (vif) { 789 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 790 791 txp->bss_idx = mvif->mt76.idx; 792 } 793 794 txp->token = cpu_to_le16(id); 795 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 796 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 797 else 798 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 799 tx_info->skb = NULL; 800 801 /* pass partial skb header to fw */ 802 tx_info->buf[1].len = MT_CT_PARSE_LEN; 803 tx_info->buf[1].skip_unmap = true; 804 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 805 806 return 0; 807 } 808 809 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 810 { 811 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 812 __le32 *txwi = ptr; 813 u32 val; 814 815 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 816 817 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 818 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 819 txwi[0] = cpu_to_le32(val); 820 821 val = MT_TXD1_LONG_FORMAT | 822 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 823 txwi[1] = cpu_to_le32(val); 824 825 txp->token = cpu_to_le16(token_id); 826 txp->nbuf = 1; 827 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 828 829 return MT_TXD_SIZE + sizeof(*txp); 830 } 831 832 static void 833 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 834 { 835 struct mt76_dev *mdev = &dev->mt76; 836 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 837 838 /* clean DMA queues and unmap buffers first */ 839 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 840 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 841 if (mphy_ext) { 842 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 843 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 844 } 845 } 846 847 static void 848 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 849 struct list_head *free_list, bool wake) 850 { 851 struct sk_buff *skb, *tmp; 852 853 mt7915_mac_sta_poll(dev); 854 855 if (wake) 856 mt76_set_tx_blocked(&dev->mt76, false); 857 858 mt76_worker_schedule(&dev->mt76.tx_worker); 859 860 list_for_each_entry_safe(skb, tmp, free_list, list) { 861 skb_list_del_init(skb); 862 napi_consume_skb(skb, 1); 863 } 864 } 865 866 static void 867 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 868 { 869 struct mt76_connac_tx_free *free = data; 870 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 871 struct mt76_dev *mdev = &dev->mt76; 872 struct mt76_txwi_cache *txwi; 873 struct ieee80211_sta *sta = NULL; 874 struct mt76_wcid *wcid = NULL; 875 LIST_HEAD(free_list); 876 void *end = data + len; 877 bool v3, wake = false; 878 u16 total, count = 0; 879 u32 txd = le32_to_cpu(free->txd); 880 __le32 *cur_info; 881 882 mt7915_mac_tx_free_prepare(dev); 883 884 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 885 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 886 887 for (cur_info = tx_info; count < total; cur_info++) { 888 u32 msdu, info; 889 u8 i; 890 891 if (WARN_ON_ONCE((void *)cur_info >= end)) 892 return; 893 894 /* 895 * 1'b1: new wcid pair. 896 * 1'b0: msdu_id with the same 'wcid pair' as above. 897 */ 898 info = le32_to_cpu(*cur_info); 899 if (info & MT_TX_FREE_PAIR) { 900 struct mt7915_sta *msta; 901 u16 idx; 902 903 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 904 wcid = mt76_wcid_ptr(dev, idx); 905 sta = wcid_to_sta(wcid); 906 if (!sta) 907 continue; 908 909 msta = container_of(wcid, struct mt7915_sta, wcid); 910 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 911 continue; 912 } 913 914 if (!mtk_wed_device_active(&mdev->mmio.wed) && wcid) { 915 u32 tx_retries = 0, tx_failed = 0; 916 917 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) { 918 tx_retries = 919 FIELD_GET(MT_TX_FREE_COUNT_V3, info) - 1; 920 tx_failed = tx_retries + 921 !!FIELD_GET(MT_TX_FREE_STAT_V3, info); 922 } else if (!v3 && (info & MT_TX_FREE_MPDU_HEADER)) { 923 tx_retries = 924 FIELD_GET(MT_TX_FREE_COUNT, info) - 1; 925 tx_failed = tx_retries + 926 !!FIELD_GET(MT_TX_FREE_STAT, info); 927 } 928 wcid->stats.tx_retries += tx_retries; 929 wcid->stats.tx_failed += tx_failed; 930 } 931 932 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) 933 continue; 934 935 for (i = 0; i < 1 + v3; i++) { 936 if (v3) { 937 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 938 if (msdu == MT_TX_FREE_MSDU_ID_V3) 939 continue; 940 } else { 941 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 942 } 943 count++; 944 txwi = mt76_token_release(mdev, msdu, &wake); 945 if (!txwi) 946 continue; 947 948 mt76_connac2_txwi_free(mdev, txwi, sta, &free_list); 949 } 950 } 951 952 mt7915_mac_tx_free_done(dev, &free_list, wake); 953 } 954 955 static void 956 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 957 { 958 struct mt76_connac_tx_free *free = data; 959 __le16 *info = (__le16 *)(data + sizeof(*free)); 960 struct mt76_dev *mdev = &dev->mt76; 961 void *end = data + len; 962 LIST_HEAD(free_list); 963 bool wake = false; 964 u8 i, count; 965 966 mt7915_mac_tx_free_prepare(dev); 967 968 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 969 if (WARN_ON_ONCE((void *)&info[count] > end)) 970 return; 971 972 for (i = 0; i < count; i++) { 973 struct mt76_txwi_cache *txwi; 974 u16 msdu = le16_to_cpu(info[i]); 975 976 txwi = mt76_token_release(mdev, msdu, &wake); 977 if (!txwi) 978 continue; 979 980 mt76_connac2_txwi_free(mdev, txwi, NULL, &free_list); 981 } 982 983 mt7915_mac_tx_free_done(dev, &free_list, wake); 984 } 985 986 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 987 { 988 struct mt7915_sta *msta = NULL; 989 struct mt76_wcid *wcid; 990 __le32 *txs_data = data; 991 u16 wcidx; 992 u8 pid; 993 994 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 995 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 996 997 if (pid < MT_PACKET_ID_WED) 998 return; 999 1000 rcu_read_lock(); 1001 1002 wcid = mt76_wcid_ptr(dev, wcidx); 1003 if (!wcid) 1004 goto out; 1005 1006 msta = container_of(wcid, struct mt7915_sta, wcid); 1007 1008 if (pid == MT_PACKET_ID_WED) 1009 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1010 else 1011 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1012 1013 if (!wcid->sta) 1014 goto out; 1015 1016 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1017 1018 out: 1019 rcu_read_unlock(); 1020 } 1021 1022 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1023 { 1024 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1025 __le32 *rxd = (__le32 *)data; 1026 __le32 *end = (__le32 *)&rxd[len / 4]; 1027 enum rx_pkt_type type; 1028 1029 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1030 1031 switch (type) { 1032 case PKT_TYPE_TXRX_NOTIFY: 1033 mt7915_mac_tx_free(dev, data, len); 1034 return false; 1035 case PKT_TYPE_TXRX_NOTIFY_V0: 1036 mt7915_mac_tx_free_v0(dev, data, len); 1037 return false; 1038 case PKT_TYPE_TXS: 1039 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1040 mt7915_mac_add_txs(dev, rxd); 1041 return false; 1042 case PKT_TYPE_RX_FW_MONITOR: 1043 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1044 return false; 1045 default: 1046 return true; 1047 } 1048 } 1049 1050 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1051 struct sk_buff *skb, u32 *info) 1052 { 1053 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1054 __le32 *rxd = (__le32 *)skb->data; 1055 __le32 *end = (__le32 *)&skb->data[skb->len]; 1056 enum rx_pkt_type type; 1057 1058 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1059 1060 switch (type) { 1061 case PKT_TYPE_TXRX_NOTIFY: 1062 mt7915_mac_tx_free(dev, skb->data, skb->len); 1063 napi_consume_skb(skb, 1); 1064 break; 1065 case PKT_TYPE_TXRX_NOTIFY_V0: 1066 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1067 napi_consume_skb(skb, 1); 1068 break; 1069 case PKT_TYPE_RX_EVENT: 1070 mt7915_mcu_rx_event(dev, skb); 1071 break; 1072 case PKT_TYPE_TXRXV: 1073 mt7915_mac_fill_rx_vector(dev, skb); 1074 break; 1075 case PKT_TYPE_TXS: 1076 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1077 mt7915_mac_add_txs(dev, rxd); 1078 dev_kfree_skb(skb); 1079 break; 1080 case PKT_TYPE_RX_FW_MONITOR: 1081 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1082 dev_kfree_skb(skb); 1083 break; 1084 case PKT_TYPE_NORMAL: 1085 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1086 mt76_rx(&dev->mt76, q, skb); 1087 return; 1088 } 1089 fallthrough; 1090 default: 1091 dev_kfree_skb(skb); 1092 break; 1093 } 1094 } 1095 1096 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1097 { 1098 struct mt7915_dev *dev = phy->dev; 1099 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1100 1101 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1102 mt76_set(dev, reg, BIT(11) | BIT(9)); 1103 } 1104 1105 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1106 { 1107 struct mt7915_dev *dev = phy->dev; 1108 int i; 1109 1110 for (i = 0; i < 4; i++) { 1111 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1112 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1113 } 1114 1115 phy->mt76->survey_time = ktime_get_boottime(); 1116 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1117 1118 /* reset airtime counters */ 1119 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1120 MT_WF_RMAC_MIB_RXTIME_CLR); 1121 1122 mt7915_mcu_get_chan_mib_info(phy, true); 1123 } 1124 1125 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1126 { 1127 s16 coverage_class = phy->coverage_class; 1128 struct mt7915_dev *dev = phy->dev; 1129 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1130 u32 val, reg_offset; 1131 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1132 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1133 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1134 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1135 u8 band = phy->mt76->band_idx; 1136 int eifs_ofdm = 84, sifs = 10, offset; 1137 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1138 1139 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1140 return; 1141 1142 if (ext_phy) 1143 coverage_class = max_t(s16, dev->phy.coverage_class, 1144 ext_phy->coverage_class); 1145 1146 mt76_set(dev, MT_ARB_SCR(band), 1147 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1148 udelay(1); 1149 1150 offset = 3 * coverage_class; 1151 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1152 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1153 1154 if (!is_mt7915(&dev->mt76)) { 1155 if (!a_band) { 1156 mt76_wr(dev, MT_TMAC_ICR1(band), 1157 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1158 eifs_ofdm = 78; 1159 } else { 1160 eifs_ofdm = 84; 1161 } 1162 } else if (a_band) { 1163 sifs = 16; 1164 } 1165 1166 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1167 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1168 mt76_wr(dev, MT_TMAC_ICR0(band), 1169 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1170 FIELD_PREP(MT_IFS_RIFS, 2) | 1171 FIELD_PREP(MT_IFS_SIFS, sifs) | 1172 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1173 1174 if (phy->slottime < 20 || a_band) 1175 val = MT7915_CFEND_RATE_DEFAULT; 1176 else 1177 val = MT7915_CFEND_RATE_11B; 1178 1179 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1180 mt76_clear(dev, MT_ARB_SCR(band), 1181 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1182 } 1183 1184 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1185 { 1186 u32 reg; 1187 1188 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1189 MT_WF_PHY_RXTD12_MT7916(band); 1190 mt76_set(dev, reg, 1191 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1192 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1193 1194 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1195 MT_WF_PHY_RX_CTRL1_MT7916(band); 1196 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1197 } 1198 1199 static u8 1200 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1201 { 1202 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1203 struct mt7915_dev *dev = phy->dev; 1204 u32 val, sum = 0, n = 0; 1205 int nss, i; 1206 1207 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1208 u32 reg = is_mt7915(&dev->mt76) ? 1209 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1210 MT_WF_IRPI_NSS_MT7916(idx, nss); 1211 1212 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1213 val = mt76_rr(dev, reg); 1214 sum += val * nf_power[i]; 1215 n += val; 1216 } 1217 } 1218 1219 if (!n) 1220 return 0; 1221 1222 return sum / n; 1223 } 1224 1225 void mt7915_update_channel(struct mt76_phy *mphy) 1226 { 1227 struct mt7915_phy *phy = mphy->priv; 1228 struct mt76_channel_state *state = mphy->chan_state; 1229 int nf; 1230 1231 mt7915_mcu_get_chan_mib_info(phy, false); 1232 1233 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1234 if (!phy->noise) 1235 phy->noise = nf << 4; 1236 else if (nf) 1237 phy->noise += nf - (phy->noise >> 4); 1238 1239 state->noise = -(phy->noise >> 4); 1240 } 1241 1242 static bool 1243 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1244 { 1245 bool ret; 1246 1247 ret = wait_event_timeout(dev->reset_wait, 1248 (READ_ONCE(dev->recovery.state) & state), 1249 MT7915_RESET_TIMEOUT); 1250 1251 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1252 return ret; 1253 } 1254 1255 static void 1256 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1257 { 1258 struct ieee80211_hw *hw = priv; 1259 1260 switch (vif->type) { 1261 case NL80211_IFTYPE_MESH_POINT: 1262 case NL80211_IFTYPE_ADHOC: 1263 case NL80211_IFTYPE_AP: 1264 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1265 BSS_CHANGED_BEACON_ENABLED); 1266 break; 1267 default: 1268 break; 1269 } 1270 } 1271 1272 static void 1273 mt7915_update_beacons(struct mt7915_dev *dev) 1274 { 1275 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1276 1277 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1278 IEEE80211_IFACE_ITER_RESUME_ALL, 1279 mt7915_update_vif_beacon, dev->mt76.hw); 1280 1281 if (!mphy_ext) 1282 return; 1283 1284 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1285 IEEE80211_IFACE_ITER_RESUME_ALL, 1286 mt7915_update_vif_beacon, mphy_ext->hw); 1287 } 1288 1289 static int 1290 mt7915_mac_restart(struct mt7915_dev *dev) 1291 { 1292 struct mt7915_phy *phy2; 1293 struct mt76_phy *ext_phy; 1294 struct mt76_dev *mdev = &dev->mt76; 1295 int i, ret; 1296 1297 ext_phy = dev->mt76.phys[MT_BAND1]; 1298 phy2 = ext_phy ? ext_phy->priv : NULL; 1299 1300 if (dev->hif2) { 1301 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1302 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1303 } 1304 1305 if (dev_is_pci(mdev->dev)) { 1306 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1307 if (dev->hif2) { 1308 if (is_mt7915(mdev)) 1309 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1310 else 1311 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0x0); 1312 } 1313 } 1314 1315 set_bit(MT76_RESET, &dev->mphy.state); 1316 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1317 wake_up(&dev->mt76.mcu.wait); 1318 if (ext_phy) 1319 set_bit(MT76_RESET, &ext_phy->state); 1320 1321 /* lock/unlock all queues to ensure that no tx is pending */ 1322 mt76_txq_schedule_all(&dev->mphy); 1323 if (ext_phy) 1324 mt76_txq_schedule_all(ext_phy); 1325 1326 /* disable all tx/rx napi */ 1327 mt76_worker_disable(&dev->mt76.tx_worker); 1328 mt76_for_each_q_rx(mdev, i) { 1329 if (mdev->q_rx[i].ndesc) 1330 napi_disable(&dev->mt76.napi[i]); 1331 } 1332 napi_disable(&dev->mt76.tx_napi); 1333 1334 /* token reinit */ 1335 mt76_connac2_tx_token_put(&dev->mt76); 1336 idr_init(&dev->mt76.token); 1337 1338 mt7915_dma_reset(dev, true); 1339 1340 mt76_for_each_q_rx(mdev, i) { 1341 if (mdev->q_rx[i].ndesc) { 1342 napi_enable(&dev->mt76.napi[i]); 1343 } 1344 } 1345 1346 local_bh_disable(); 1347 mt76_for_each_q_rx(mdev, i) { 1348 if (mdev->q_rx[i].ndesc) { 1349 napi_schedule(&dev->mt76.napi[i]); 1350 } 1351 } 1352 local_bh_enable(); 1353 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1354 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1355 1356 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1357 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1358 1359 if (dev->hif2) { 1360 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1361 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1362 } 1363 if (dev_is_pci(mdev->dev)) { 1364 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1365 if (dev->hif2) { 1366 mt76_wr(dev, MT_PCIE_RECOG_ID, 1367 dev->hif2->index | MT_PCIE_RECOG_ID_SEM); 1368 if (is_mt7915(mdev)) 1369 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1370 else 1371 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0xff); 1372 } 1373 } 1374 1375 /* load firmware */ 1376 ret = mt7915_mcu_init_firmware(dev); 1377 if (ret) 1378 goto out; 1379 1380 /* set the necessary init items */ 1381 ret = mt7915_mcu_set_eeprom(dev); 1382 if (ret) 1383 goto out; 1384 1385 mt7915_mac_init(dev); 1386 mt7915_init_txpower(&dev->phy); 1387 mt7915_init_txpower(phy2); 1388 ret = mt7915_txbf_init(dev); 1389 1390 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1391 ret = mt7915_run(dev->mphy.hw); 1392 if (ret) 1393 goto out; 1394 } 1395 1396 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) { 1397 ret = mt7915_run(ext_phy->hw); 1398 if (ret) 1399 goto out; 1400 } 1401 1402 out: 1403 /* reset done */ 1404 clear_bit(MT76_RESET, &dev->mphy.state); 1405 if (phy2) 1406 clear_bit(MT76_RESET, &phy2->mt76->state); 1407 1408 napi_enable(&dev->mt76.tx_napi); 1409 1410 local_bh_disable(); 1411 napi_schedule(&dev->mt76.tx_napi); 1412 local_bh_enable(); 1413 1414 mt76_worker_enable(&dev->mt76.tx_worker); 1415 1416 return ret; 1417 } 1418 1419 static void 1420 mt7915_mac_full_reset(struct mt7915_dev *dev) 1421 { 1422 struct mt76_phy *ext_phy; 1423 struct mt7915_phy *phy2; 1424 int i; 1425 1426 ext_phy = dev->mt76.phys[MT_BAND1]; 1427 phy2 = ext_phy ? ext_phy->priv : NULL; 1428 1429 dev->recovery.hw_full_reset = true; 1430 1431 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1432 wake_up(&dev->mt76.mcu.wait); 1433 ieee80211_stop_queues(mt76_hw(dev)); 1434 if (ext_phy) 1435 ieee80211_stop_queues(ext_phy->hw); 1436 1437 cancel_delayed_work_sync(&dev->mphy.mac_work); 1438 if (ext_phy) 1439 cancel_delayed_work_sync(&ext_phy->mac_work); 1440 1441 mt76_abort_scan(&dev->mt76); 1442 1443 mutex_lock(&dev->mt76.mutex); 1444 for (i = 0; i < 10; i++) { 1445 if (!mt7915_mac_restart(dev)) 1446 break; 1447 } 1448 1449 if (i == 10) 1450 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1451 1452 dev->phy.omac_mask = 0; 1453 if (phy2) 1454 phy2->omac_mask = 0; 1455 1456 mt76_reset_device(&dev->mt76); 1457 1458 INIT_LIST_HEAD(&dev->sta_rc_list); 1459 INIT_LIST_HEAD(&dev->twt_list); 1460 1461 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 1462 dev->mt76.global_wcid.idx = i; 1463 dev->recovery.hw_full_reset = false; 1464 1465 mutex_unlock(&dev->mt76.mutex); 1466 1467 ieee80211_restart_hw(mt76_hw(dev)); 1468 if (ext_phy) 1469 ieee80211_restart_hw(ext_phy->hw); 1470 } 1471 1472 /* system error recovery */ 1473 void mt7915_mac_reset_work(struct work_struct *work) 1474 { 1475 struct mt7915_phy *phy2; 1476 struct mt76_phy *ext_phy; 1477 struct mt7915_dev *dev; 1478 int i; 1479 1480 dev = container_of(work, struct mt7915_dev, reset_work); 1481 ext_phy = dev->mt76.phys[MT_BAND1]; 1482 phy2 = ext_phy ? ext_phy->priv : NULL; 1483 1484 /* chip full reset */ 1485 if (dev->recovery.restart) { 1486 /* disable WA/WM WDT */ 1487 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1488 MT_MCU_CMD_WDT_MASK); 1489 1490 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1491 dev->recovery.wa_reset_count++; 1492 else 1493 dev->recovery.wm_reset_count++; 1494 1495 mt7915_mac_full_reset(dev); 1496 1497 /* enable mcu irq */ 1498 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1499 mt7915_irq_disable(dev, 0); 1500 1501 /* enable WA/WM WDT */ 1502 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1503 1504 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1505 dev->recovery.restart = false; 1506 return; 1507 } 1508 1509 /* chip partial reset */ 1510 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1511 return; 1512 1513 ieee80211_stop_queues(mt76_hw(dev)); 1514 if (ext_phy) 1515 ieee80211_stop_queues(ext_phy->hw); 1516 1517 set_bit(MT76_RESET, &dev->mphy.state); 1518 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1519 wake_up(&dev->mt76.mcu.wait); 1520 cancel_delayed_work_sync(&dev->mphy.mac_work); 1521 if (phy2) { 1522 set_bit(MT76_RESET, &phy2->mt76->state); 1523 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1524 } 1525 1526 mutex_lock(&dev->mt76.mutex); 1527 1528 mt76_worker_disable(&dev->mt76.tx_worker); 1529 mt76_for_each_q_rx(&dev->mt76, i) 1530 napi_disable(&dev->mt76.napi[i]); 1531 napi_disable(&dev->mt76.tx_napi); 1532 1533 1534 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1535 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1536 1537 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1538 1539 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1540 mt7915_dma_reset(dev, false); 1541 1542 mt76_connac2_tx_token_put(&dev->mt76); 1543 idr_init(&dev->mt76.token); 1544 1545 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1546 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1547 } 1548 1549 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1550 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1551 1552 /* enable DMA Tx/Rx and interrupt */ 1553 mt7915_dma_start(dev, false, false); 1554 1555 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1556 clear_bit(MT76_RESET, &dev->mphy.state); 1557 if (phy2) 1558 clear_bit(MT76_RESET, &phy2->mt76->state); 1559 1560 mt76_for_each_q_rx(&dev->mt76, i) { 1561 napi_enable(&dev->mt76.napi[i]); 1562 } 1563 1564 local_bh_disable(); 1565 mt76_for_each_q_rx(&dev->mt76, i) { 1566 napi_schedule(&dev->mt76.napi[i]); 1567 } 1568 local_bh_enable(); 1569 1570 tasklet_schedule(&dev->mt76.irq_tasklet); 1571 1572 mt76_worker_enable(&dev->mt76.tx_worker); 1573 1574 napi_enable(&dev->mt76.tx_napi); 1575 local_bh_disable(); 1576 napi_schedule(&dev->mt76.tx_napi); 1577 local_bh_enable(); 1578 1579 ieee80211_wake_queues(mt76_hw(dev)); 1580 if (ext_phy) 1581 ieee80211_wake_queues(ext_phy->hw); 1582 1583 mutex_unlock(&dev->mt76.mutex); 1584 1585 mt7915_update_beacons(dev); 1586 1587 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1588 MT7915_WATCHDOG_TIME); 1589 if (phy2) 1590 ieee80211_queue_delayed_work(ext_phy->hw, 1591 &phy2->mt76->mac_work, 1592 MT7915_WATCHDOG_TIME); 1593 } 1594 1595 /* firmware coredump */ 1596 void mt7915_mac_dump_work(struct work_struct *work) 1597 { 1598 const struct mt7915_mem_region *mem_region; 1599 struct mt7915_crash_data *crash_data; 1600 struct mt7915_dev *dev; 1601 struct mt7915_mem_hdr *hdr; 1602 size_t buf_len; 1603 int i; 1604 u32 num; 1605 u8 *buf; 1606 1607 dev = container_of(work, struct mt7915_dev, dump_work); 1608 1609 mutex_lock(&dev->dump_mutex); 1610 1611 crash_data = mt7915_coredump_new(dev); 1612 if (!crash_data) { 1613 mutex_unlock(&dev->dump_mutex); 1614 goto skip_coredump; 1615 } 1616 1617 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1618 if (!mem_region || !crash_data->memdump_buf_len) { 1619 mutex_unlock(&dev->dump_mutex); 1620 goto skip_memdump; 1621 } 1622 1623 buf = crash_data->memdump_buf; 1624 buf_len = crash_data->memdump_buf_len; 1625 1626 /* dumping memory content... */ 1627 memset(buf, 0, buf_len); 1628 for (i = 0; i < num; i++) { 1629 if (mem_region->len > buf_len) { 1630 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1631 mem_region->name, 1632 (unsigned long)mem_region->len); 1633 break; 1634 } 1635 1636 /* reserve space for the header */ 1637 hdr = (void *)buf; 1638 buf += sizeof(*hdr); 1639 buf_len -= sizeof(*hdr); 1640 1641 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1642 mem_region->len); 1643 1644 hdr->start = mem_region->start; 1645 hdr->len = mem_region->len; 1646 1647 if (!mem_region->len) 1648 /* note: the header remains, just with zero length */ 1649 break; 1650 1651 buf += mem_region->len; 1652 buf_len -= mem_region->len; 1653 1654 mem_region++; 1655 } 1656 1657 mutex_unlock(&dev->dump_mutex); 1658 1659 skip_memdump: 1660 mt7915_coredump_submit(dev); 1661 skip_coredump: 1662 queue_work(dev->mt76.wq, &dev->reset_work); 1663 } 1664 1665 void mt7915_reset(struct mt7915_dev *dev) 1666 { 1667 if (!dev->recovery.hw_init_done) 1668 return; 1669 1670 if (dev->recovery.hw_full_reset) 1671 return; 1672 1673 /* wm/wa exception: do full recovery */ 1674 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1675 dev->recovery.restart = true; 1676 dev_info(dev->mt76.dev, 1677 "%s indicated firmware crash, attempting recovery\n", 1678 wiphy_name(dev->mt76.hw->wiphy)); 1679 1680 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1681 queue_work(dev->mt76.wq, &dev->dump_work); 1682 return; 1683 } 1684 1685 if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) { 1686 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1687 wake_up(&dev->mt76.mcu.wait); 1688 } 1689 1690 queue_work(dev->mt76.wq, &dev->reset_work); 1691 wake_up(&dev->reset_wait); 1692 } 1693 1694 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1695 { 1696 struct mt76_mib_stats *mib = &phy->mib; 1697 struct mt7915_dev *dev = phy->dev; 1698 int i, aggr0 = 0, aggr1, cnt; 1699 u8 band = phy->mt76->band_idx; 1700 u32 val; 1701 1702 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1703 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1704 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1705 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1706 1707 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1708 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1709 1710 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1711 mib->rx_mpdu_cnt += cnt; 1712 1713 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1714 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1715 1716 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1717 mib->rx_vector_mismatch_cnt += 1718 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1719 1720 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1721 mib->rx_delimiter_fail_cnt += 1722 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1723 1724 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1725 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1726 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1727 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1728 1729 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1730 mib->rx_len_mismatch_cnt += 1731 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1732 1733 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1734 mib->tx_ampdu_cnt += cnt; 1735 1736 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1737 mib->tx_stop_q_empty_cnt += 1738 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1739 1740 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1741 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1742 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1743 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1744 1745 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1746 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1747 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1748 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1749 1750 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1751 mib->primary_cca_busy_time += 1752 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1753 1754 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1755 mib->secondary_cca_busy_time += 1756 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1757 1758 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1759 mib->primary_energy_detect_time += 1760 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1761 1762 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1763 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1764 1765 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1766 mib->ofdm_mdrdy_time += 1767 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1768 1769 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1770 mib->green_mdrdy_time += 1771 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1772 1773 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1774 mib->rx_ampdu_cnt += cnt; 1775 1776 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1777 mib->rx_ampdu_bytes_cnt += cnt; 1778 1779 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1780 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1781 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1782 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1783 1784 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1785 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1786 1787 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1788 mib->tx_rwp_fail_cnt += 1789 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1790 1791 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1792 mib->tx_rwp_need_cnt += 1793 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1794 1795 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1796 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1797 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1798 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1799 1800 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1801 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1802 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1803 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1804 1805 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1806 mib->rx_ba_cnt += cnt; 1807 1808 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1809 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1810 1811 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1812 mib->tx_mu_mpdu_cnt += cnt; 1813 1814 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1815 mib->tx_mu_acked_mpdu_cnt += cnt; 1816 1817 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1818 mib->tx_su_acked_mpdu_cnt += cnt; 1819 1820 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1821 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1822 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1823 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1824 1825 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1826 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1827 mib->tx_amsdu[i] += cnt; 1828 mib->tx_amsdu_cnt += cnt; 1829 } 1830 1831 if (is_mt7915(&dev->mt76)) { 1832 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1833 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1834 mib->ba_miss_cnt += 1835 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1836 mib->ack_fail_cnt += 1837 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1838 1839 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1840 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1841 mib->rts_retries_cnt += 1842 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1843 1844 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1845 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1846 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1847 1848 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1849 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1850 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1851 } 1852 1853 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1854 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1855 1856 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1857 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1858 1859 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1860 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1861 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1862 1863 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1864 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1865 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1866 1867 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1868 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1869 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1870 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1871 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1872 } else { 1873 for (i = 0; i < 2; i++) { 1874 /* rts count */ 1875 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1876 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1877 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1878 1879 /* rts retry count */ 1880 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1881 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1882 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1883 1884 /* ba miss count */ 1885 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1886 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1887 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1888 1889 /* ack fail count */ 1890 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1891 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1892 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1893 } 1894 1895 for (i = 0; i < 8; i++) { 1896 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1897 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1898 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1899 } 1900 1901 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1902 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1903 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1904 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1905 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1906 1907 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1908 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1909 1910 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1911 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1912 1913 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1914 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1915 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1916 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1917 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1918 1919 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1920 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1921 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1922 } 1923 } 1924 1925 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1926 { 1927 struct mt7915_dev *dev = phy->dev; 1928 u32 trb; 1929 1930 if (!phy->omac_mask) 1931 return; 1932 1933 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1934 * stopping Rx, so check status periodically to see if TRB hardware 1935 * requires minimal recovery. 1936 */ 1937 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1938 1939 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1940 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1941 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 1942 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 1943 trb == phy->trb_ts) 1944 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 1945 phy->mt76->band_idx); 1946 1947 phy->trb_ts = trb; 1948 } 1949 1950 void mt7915_mac_sta_rc_work(struct work_struct *work) 1951 { 1952 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 1953 struct ieee80211_sta *sta; 1954 struct ieee80211_vif *vif; 1955 struct mt7915_sta *msta; 1956 u32 changed; 1957 LIST_HEAD(list); 1958 1959 spin_lock_bh(&dev->mt76.sta_poll_lock); 1960 list_splice_init(&dev->sta_rc_list, &list); 1961 1962 while (!list_empty(&list)) { 1963 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 1964 list_del_init(&msta->rc_list); 1965 changed = msta->changed; 1966 msta->changed = 0; 1967 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1968 1969 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 1970 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1971 1972 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 1973 IEEE80211_RC_NSS_CHANGED | 1974 IEEE80211_RC_BW_CHANGED)) 1975 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 1976 1977 if (changed & IEEE80211_RC_SMPS_CHANGED) 1978 mt7915_mcu_add_smps(dev, vif, sta); 1979 1980 spin_lock_bh(&dev->mt76.sta_poll_lock); 1981 } 1982 1983 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1984 } 1985 1986 void mt7915_mac_work(struct work_struct *work) 1987 { 1988 struct mt7915_phy *phy; 1989 struct mt76_phy *mphy; 1990 1991 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 1992 mac_work.work); 1993 phy = mphy->priv; 1994 1995 mutex_lock(&mphy->dev->mutex); 1996 1997 mt76_update_survey(mphy); 1998 if (++mphy->mac_work_count == 5) { 1999 mphy->mac_work_count = 0; 2000 2001 mt7915_mac_update_stats(phy); 2002 mt7915_mac_severe_check(phy); 2003 2004 if (phy->dev->muru_debug) 2005 mt7915_mcu_muru_debug_get(phy); 2006 } 2007 2008 mutex_unlock(&mphy->dev->mutex); 2009 2010 mt76_tx_status_check(mphy->dev, false); 2011 2012 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2013 MT7915_WATCHDOG_TIME); 2014 } 2015 2016 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2017 { 2018 struct mt7915_dev *dev = phy->dev; 2019 int rdd_idx = mt7915_get_rdd_idx(phy, false); 2020 2021 if (rdd_idx < 0) 2022 return; 2023 2024 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, rdd_idx, 0, 0); 2025 } 2026 2027 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int rdd_idx) 2028 { 2029 int err, region; 2030 2031 switch (dev->mt76.region) { 2032 case NL80211_DFS_ETSI: 2033 region = 0; 2034 break; 2035 case NL80211_DFS_JP: 2036 region = 2; 2037 break; 2038 case NL80211_DFS_FCC: 2039 default: 2040 region = 1; 2041 break; 2042 } 2043 2044 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, rdd_idx, 0, region); 2045 if (err < 0) 2046 return err; 2047 2048 if (is_mt7915(&dev->mt76)) { 2049 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, rdd_idx, 2050 0, dev->dbdc_support ? 2 : 0); 2051 if (err < 0) 2052 return err; 2053 } 2054 2055 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, rdd_idx, 0, 1); 2056 } 2057 2058 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2059 { 2060 struct mt7915_dev *dev = phy->dev; 2061 int err, rdd_idx; 2062 2063 rdd_idx = mt7915_get_rdd_idx(phy, false); 2064 if (rdd_idx < 0) 2065 return -EINVAL; 2066 2067 /* start CAC */ 2068 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, rdd_idx, 0, 0); 2069 if (err < 0) 2070 return err; 2071 2072 err = mt7915_dfs_start_rdd(dev, rdd_idx); 2073 if (err < 0) 2074 return err; 2075 2076 return 0; 2077 } 2078 2079 static int 2080 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2081 { 2082 const struct mt7915_dfs_radar_spec *radar_specs; 2083 struct mt7915_dev *dev = phy->dev; 2084 int err, i; 2085 2086 switch (dev->mt76.region) { 2087 case NL80211_DFS_FCC: 2088 radar_specs = &fcc_radar_specs; 2089 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2090 if (err < 0) 2091 return err; 2092 break; 2093 case NL80211_DFS_ETSI: 2094 radar_specs = &etsi_radar_specs; 2095 break; 2096 case NL80211_DFS_JP: 2097 radar_specs = &jp_radar_specs; 2098 break; 2099 default: 2100 return -EINVAL; 2101 } 2102 2103 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2104 err = mt7915_mcu_set_radar_th(dev, i, 2105 &radar_specs->radar_pattern[i]); 2106 if (err < 0) 2107 return err; 2108 } 2109 2110 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2111 } 2112 2113 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2114 { 2115 struct mt7915_dev *dev = phy->dev; 2116 enum mt76_dfs_state dfs_state, prev_state; 2117 int err, rdd_idx = mt7915_get_rdd_idx(phy, false); 2118 2119 prev_state = phy->mt76->dfs_state; 2120 dfs_state = mt76_phy_dfs_state(phy->mt76); 2121 2122 if (prev_state == dfs_state || rdd_idx < 0) 2123 return 0; 2124 2125 if (prev_state == MT_DFS_STATE_UNKNOWN) 2126 mt7915_dfs_stop_radar_detector(phy); 2127 2128 if (dfs_state == MT_DFS_STATE_DISABLED) 2129 goto stop; 2130 2131 if (prev_state <= MT_DFS_STATE_DISABLED) { 2132 err = mt7915_dfs_init_radar_specs(phy); 2133 if (err < 0) 2134 return err; 2135 2136 err = mt7915_dfs_start_radar_detector(phy); 2137 if (err < 0) 2138 return err; 2139 2140 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2141 } 2142 2143 if (dfs_state == MT_DFS_STATE_CAC) 2144 return 0; 2145 2146 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, rdd_idx, 0, 0); 2147 if (err < 0) { 2148 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2149 return err; 2150 } 2151 2152 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2153 return 0; 2154 2155 stop: 2156 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, rdd_idx, 0, 0); 2157 if (err < 0) 2158 return err; 2159 2160 if (is_mt7915(&dev->mt76)) { 2161 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2162 rdd_idx, 0, dev->dbdc_support ? 2 : 0); 2163 if (err < 0) 2164 return err; 2165 } 2166 2167 mt7915_dfs_stop_radar_detector(phy); 2168 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2169 2170 return 0; 2171 } 2172 2173 static int 2174 mt7915_mac_twt_duration_align(int duration) 2175 { 2176 return duration << 8; 2177 } 2178 2179 static u64 2180 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2181 struct mt7915_twt_flow *flow) 2182 { 2183 struct mt7915_twt_flow *iter, *iter_next; 2184 u32 duration = flow->duration << 8; 2185 u64 start_tsf; 2186 2187 iter = list_first_entry_or_null(&dev->twt_list, 2188 struct mt7915_twt_flow, list); 2189 if (!iter || !iter->sched || iter->start_tsf > duration) { 2190 /* add flow as first entry in the list */ 2191 list_add(&flow->list, &dev->twt_list); 2192 return 0; 2193 } 2194 2195 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2196 start_tsf = iter->start_tsf + 2197 mt7915_mac_twt_duration_align(iter->duration); 2198 if (list_is_last(&iter->list, &dev->twt_list)) 2199 break; 2200 2201 if (!iter_next->sched || 2202 iter_next->start_tsf > start_tsf + duration) { 2203 list_add(&flow->list, &iter->list); 2204 goto out; 2205 } 2206 } 2207 2208 /* add flow as last entry in the list */ 2209 list_add_tail(&flow->list, &dev->twt_list); 2210 out: 2211 return start_tsf; 2212 } 2213 2214 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2215 { 2216 struct ieee80211_twt_params *twt_agrt; 2217 u64 interval, duration; 2218 u16 mantissa; 2219 u8 exp; 2220 2221 /* only individual agreement supported */ 2222 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2223 return -EOPNOTSUPP; 2224 2225 /* only 256us unit supported */ 2226 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2227 return -EOPNOTSUPP; 2228 2229 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2230 2231 /* explicit agreement not supported */ 2232 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2233 return -EOPNOTSUPP; 2234 2235 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2236 le16_to_cpu(twt_agrt->req_type)); 2237 mantissa = le16_to_cpu(twt_agrt->mantissa); 2238 duration = twt_agrt->min_twt_dur << 8; 2239 2240 interval = (u64)mantissa << exp; 2241 if (interval < duration) 2242 return -EOPNOTSUPP; 2243 2244 return 0; 2245 } 2246 2247 static bool 2248 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2249 struct ieee80211_twt_params *twt_agrt) 2250 { 2251 u16 type = le16_to_cpu(twt_agrt->req_type); 2252 u8 exp; 2253 int i; 2254 2255 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2256 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2257 struct mt7915_twt_flow *f; 2258 2259 if (!(msta->twt.flowid_mask & BIT(i))) 2260 continue; 2261 2262 f = &msta->twt.flow[i]; 2263 if (f->duration == twt_agrt->min_twt_dur && 2264 f->mantissa == twt_agrt->mantissa && 2265 f->exp == exp && 2266 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2267 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2268 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2269 return true; 2270 } 2271 2272 return false; 2273 } 2274 2275 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2276 struct ieee80211_sta *sta, 2277 struct ieee80211_twt_setup *twt) 2278 { 2279 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2280 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2281 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2282 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2283 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2284 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2285 struct mt7915_twt_flow *flow; 2286 int flowid, table_id; 2287 u8 exp; 2288 2289 if (mt7915_mac_check_twt_req(twt)) 2290 goto out; 2291 2292 mutex_lock(&dev->mt76.mutex); 2293 2294 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2295 goto unlock; 2296 2297 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2298 goto unlock; 2299 2300 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2301 setup_cmd = TWT_SETUP_CMD_DICTATE; 2302 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2303 goto unlock; 2304 } 2305 2306 flowid = ffs(~msta->twt.flowid_mask) - 1; 2307 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2308 twt_agrt->req_type |= le16_encode_bits(flowid, 2309 IEEE80211_TWT_REQTYPE_FLOWID); 2310 2311 table_id = ffs(~dev->twt.table_mask) - 1; 2312 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2313 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2314 2315 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2316 goto unlock; 2317 2318 flow = &msta->twt.flow[flowid]; 2319 memset(flow, 0, sizeof(*flow)); 2320 INIT_LIST_HEAD(&flow->list); 2321 flow->wcid = msta->wcid.idx; 2322 flow->table_id = table_id; 2323 flow->id = flowid; 2324 flow->duration = twt_agrt->min_twt_dur; 2325 flow->mantissa = twt_agrt->mantissa; 2326 flow->exp = exp; 2327 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2328 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2329 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2330 2331 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2332 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2333 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2334 u64 flow_tsf, curr_tsf; 2335 u32 rem; 2336 2337 flow->sched = true; 2338 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2339 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2340 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2341 flow_tsf = curr_tsf + interval - rem; 2342 twt_agrt->twt = cpu_to_le64(flow_tsf); 2343 } else { 2344 list_add_tail(&flow->list, &dev->twt_list); 2345 } 2346 flow->tsf = le64_to_cpu(twt_agrt->twt); 2347 2348 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2349 goto unlock; 2350 2351 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2352 dev->twt.table_mask |= BIT(table_id); 2353 msta->twt.flowid_mask |= BIT(flowid); 2354 dev->twt.n_agrt++; 2355 2356 unlock: 2357 mutex_unlock(&dev->mt76.mutex); 2358 out: 2359 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2360 twt_agrt->req_type |= 2361 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2362 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2363 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2364 } 2365 2366 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2367 struct mt7915_sta *msta, 2368 u8 flowid) 2369 { 2370 struct mt7915_twt_flow *flow; 2371 2372 lockdep_assert_held(&dev->mt76.mutex); 2373 2374 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2375 return; 2376 2377 if (!(msta->twt.flowid_mask & BIT(flowid))) 2378 return; 2379 2380 flow = &msta->twt.flow[flowid]; 2381 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2382 MCU_TWT_AGRT_DELETE)) 2383 return; 2384 2385 list_del_init(&flow->list); 2386 msta->twt.flowid_mask &= ~BIT(flowid); 2387 dev->twt.table_mask &= ~BIT(flow->table_id); 2388 dev->twt.n_agrt--; 2389 } 2390