1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
3
4 #ifndef _HINIC3_COMMON_H_
5 #define _HINIC3_COMMON_H_
6
7 #include <linux/device.h>
8
9 #define HINIC3_MIN_PAGE_SIZE 0x1000
10
11 struct hinic3_dma_addr_align {
12 u32 real_size;
13
14 void *ori_vaddr;
15 dma_addr_t ori_paddr;
16
17 void *align_vaddr;
18 dma_addr_t align_paddr;
19 };
20
21 enum hinic3_wait_return {
22 HINIC3_WAIT_PROCESS_CPL = 0,
23 HINIC3_WAIT_PROCESS_WAITING = 1,
24 };
25
26 struct hinic3_sge {
27 __le32 hi_addr;
28 __le32 lo_addr;
29 __le32 len;
30 __le32 rsvd;
31 };
32
hinic3_set_sge(struct hinic3_sge * sge,dma_addr_t addr,__le32 len)33 static inline void hinic3_set_sge(struct hinic3_sge *sge, dma_addr_t addr,
34 __le32 len)
35 {
36 sge->hi_addr = cpu_to_le32(upper_32_bits(addr));
37 sge->lo_addr = cpu_to_le32(lower_32_bits(addr));
38 sge->len = len;
39 sge->rsvd = 0;
40 }
41
42 int hinic3_dma_zalloc_coherent_align(struct device *dev, u32 size, u32 align,
43 gfp_t flag,
44 struct hinic3_dma_addr_align *mem_align);
45 void hinic3_dma_free_coherent_align(struct device *dev,
46 struct hinic3_dma_addr_align *mem_align);
47
48 typedef enum hinic3_wait_return (*wait_cpl_handler)(void *priv_data);
49 int hinic3_wait_for_timeout(void *priv_data, wait_cpl_handler handler,
50 u32 wait_total_ms, u32 wait_once_us);
51
52 void hinic3_cmdq_buf_swab32(void *data, int len);
53
54 #endif
55