1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50
51 struct rtw89_h2creg_hdr {
52 u32 w0;
53 };
54
55 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
56 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
57
58 struct rtw89_h2creg_sch_tx_en {
59 u32 w0;
60 u32 w1;
61 } __packed;
62
63 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
64 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
65 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
66
67 #define RTW89_H2CREG_MAX 4
68 #define RTW89_C2HREG_MAX 4
69 #define RTW89_C2HREG_HDR_LEN 2
70 #define RTW89_H2CREG_HDR_LEN 2
71 #define RTW89_C2H_TIMEOUT 1000000
72 struct rtw89_mac_c2h_info {
73 u8 id;
74 u8 content_len;
75 union {
76 u32 c2hreg[RTW89_C2HREG_MAX];
77 struct rtw89_c2hreg_hdr hdr;
78 struct rtw89_c2hreg_phycap phycap;
79 } u;
80 };
81
82 struct rtw89_mac_h2c_info {
83 u8 id;
84 u8 content_len;
85 union {
86 u32 h2creg[RTW89_H2CREG_MAX];
87 struct rtw89_h2creg_hdr hdr;
88 struct rtw89_h2creg_sch_tx_en sch_tx_en;
89 } u;
90 };
91
92 enum rtw89_mac_h2c_type {
93 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
94 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
95 RTW89_FWCMD_H2CREG_FUNC_FWERR,
96 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
97 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
98 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
99 };
100
101 enum rtw89_mac_c2h_type {
102 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
103 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
104 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
105 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
106 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
107 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
108 };
109
110 enum rtw89_fw_c2h_category {
111 RTW89_C2H_CAT_TEST,
112 RTW89_C2H_CAT_MAC,
113 RTW89_C2H_CAT_OUTSRC,
114 };
115
116 enum rtw89_fw_log_level {
117 RTW89_FW_LOG_LEVEL_OFF,
118 RTW89_FW_LOG_LEVEL_CRT,
119 RTW89_FW_LOG_LEVEL_SER,
120 RTW89_FW_LOG_LEVEL_WARN,
121 RTW89_FW_LOG_LEVEL_LOUD,
122 RTW89_FW_LOG_LEVEL_TR,
123 };
124
125 enum rtw89_fw_log_path {
126 RTW89_FW_LOG_LEVEL_UART,
127 RTW89_FW_LOG_LEVEL_C2H,
128 RTW89_FW_LOG_LEVEL_SNI,
129 };
130
131 enum rtw89_fw_log_comp {
132 RTW89_FW_LOG_COMP_VER,
133 RTW89_FW_LOG_COMP_INIT,
134 RTW89_FW_LOG_COMP_TASK,
135 RTW89_FW_LOG_COMP_CNS,
136 RTW89_FW_LOG_COMP_H2C,
137 RTW89_FW_LOG_COMP_C2H,
138 RTW89_FW_LOG_COMP_TX,
139 RTW89_FW_LOG_COMP_RX,
140 RTW89_FW_LOG_COMP_IPSEC,
141 RTW89_FW_LOG_COMP_TIMER,
142 RTW89_FW_LOG_COMP_DBGPKT,
143 RTW89_FW_LOG_COMP_PS,
144 RTW89_FW_LOG_COMP_ERROR,
145 RTW89_FW_LOG_COMP_WOWLAN,
146 RTW89_FW_LOG_COMP_SECURE_BOOT,
147 RTW89_FW_LOG_COMP_BTC,
148 RTW89_FW_LOG_COMP_BB,
149 RTW89_FW_LOG_COMP_TWT,
150 RTW89_FW_LOG_COMP_RF,
151 RTW89_FW_LOG_COMP_MCC = 20,
152 };
153
154 enum rtw89_pkt_offload_op {
155 RTW89_PKT_OFLD_OP_ADD,
156 RTW89_PKT_OFLD_OP_DEL,
157 RTW89_PKT_OFLD_OP_READ,
158
159 NUM_OF_RTW89_PKT_OFFLOAD_OP,
160 };
161
162 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
163 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
164
165 enum rtw89_scanofld_notify_reason {
166 RTW89_SCAN_DWELL_NOTIFY,
167 RTW89_SCAN_PRE_TX_NOTIFY,
168 RTW89_SCAN_POST_TX_NOTIFY,
169 RTW89_SCAN_ENTER_CH_NOTIFY,
170 RTW89_SCAN_LEAVE_CH_NOTIFY,
171 RTW89_SCAN_END_SCAN_NOTIFY,
172 };
173
174 enum rtw89_chan_type {
175 RTW89_CHAN_OPERATE = 0,
176 RTW89_CHAN_ACTIVE,
177 RTW89_CHAN_DFS,
178 };
179
180 enum rtw89_p2pps_action {
181 RTW89_P2P_ACT_INIT = 0,
182 RTW89_P2P_ACT_UPDATE = 1,
183 RTW89_P2P_ACT_REMOVE = 2,
184 RTW89_P2P_ACT_TERMINATE = 3,
185 };
186
187 enum rtw89_bcn_fltr_offload_mode {
188 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
189 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
190 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
191 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
192
193 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
194 };
195
196 enum rtw89_bcn_fltr_type {
197 RTW89_BCN_FLTR_BEACON_LOSS,
198 RTW89_BCN_FLTR_RSSI,
199 RTW89_BCN_FLTR_NOTIFY,
200 };
201
202 enum rtw89_bcn_fltr_rssi_event {
203 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
204 RTW89_BCN_FLTR_RSSI_HIGH,
205 RTW89_BCN_FLTR_RSSI_LOW,
206 };
207
208 #define FWDL_SECTION_MAX_NUM 10
209 #define FWDL_SECTION_CHKSUM_LEN 8
210 #define FWDL_SECTION_PER_PKT_LEN 2020
211
212 struct rtw89_fw_hdr_section_info {
213 u8 redl;
214 const u8 *addr;
215 u32 len;
216 u32 dladdr;
217 u32 mssc;
218 u8 type;
219 };
220
221 struct rtw89_fw_bin_info {
222 u8 section_num;
223 u32 hdr_len;
224 bool dynamic_hdr_en;
225 u32 dynamic_hdr_len;
226 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
227 };
228
229 struct rtw89_fw_macid_pause_grp {
230 __le32 pause_grp[4];
231 __le32 mask_grp[4];
232 } __packed;
233
234 #define RTW89_H2C_MAX_SIZE 2048
235 #define RTW89_CHANNEL_TIME 45
236 #define RTW89_CHANNEL_TIME_6G 20
237 #define RTW89_DFS_CHAN_TIME 105
238 #define RTW89_OFF_CHAN_TIME 100
239 #define RTW89_DWELL_TIME 20
240 #define RTW89_DWELL_TIME_6G 10
241 #define RTW89_SCAN_WIDTH 0
242 #define RTW89_SCANOFLD_MAX_SSID 8
243 #define RTW89_SCANOFLD_MAX_IE_LEN 512
244 #define RTW89_SCANOFLD_PKT_NONE 0xFF
245 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
246 #define RTW89_MAC_CHINFO_SIZE 28
247 #define RTW89_SCAN_LIST_GUARD 4
248 #define RTW89_SCAN_LIST_LIMIT \
249 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
250
251 #define RTW89_BCN_LOSS_CNT 10
252
253 struct rtw89_mac_chinfo {
254 u8 period;
255 u8 dwell_time;
256 u8 central_ch;
257 u8 pri_ch;
258 u8 bw:3;
259 u8 notify_action:5;
260 u8 num_pkt:4;
261 u8 tx_pkt:1;
262 u8 pause_data:1;
263 u8 ch_band:2;
264 u8 probe_id;
265 u8 dfs_ch:1;
266 u8 tx_null:1;
267 u8 rand_seq_num:1;
268 u8 cfg_tx_pwr:1;
269 u8 rsvd0: 4;
270 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
271 u16 tx_pwr_idx;
272 u8 rsvd1;
273 struct list_head list;
274 bool is_psc;
275 };
276
277 struct rtw89_scan_option {
278 bool enable;
279 bool target_ch_mode;
280 };
281
282 struct rtw89_pktofld_info {
283 struct list_head list;
284 u8 id;
285
286 /* Below fields are for 6 GHz RNR use only */
287 u8 ssid[IEEE80211_MAX_SSID_LEN];
288 u8 ssid_len;
289 u8 bssid[ETH_ALEN];
290 u16 channel_6ghz;
291 bool cancel;
292 };
293
294 struct rtw89_h2c_ra {
295 __le32 w0;
296 __le32 w1;
297 __le32 w2;
298 __le32 w3;
299 } __packed;
300
301 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
302 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
303 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
304 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
305 #define RTW89_H2C_RA_W0_DCM BIT(16)
306 #define RTW89_H2C_RA_W0_ER BIT(17)
307 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
308 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
309 #define RTW89_H2C_RA_W0_SGI BIT(21)
310 #define RTW89_H2C_RA_W0_LDPC BIT(22)
311 #define RTW89_H2C_RA_W0_STBC BIT(23)
312 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
313 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
314 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
315 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
316 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
317 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
318 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
319 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
320 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
321 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
322 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
323 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
324 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
325 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
326 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
327 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
328 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
329
330 struct rtw89_h2c_ra_v1 {
331 struct rtw89_h2c_ra v0;
332 __le32 w4;
333 __le32 w5;
334 } __packed;
335
336 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
337 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
338 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
339 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
340
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)341 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
342 {
343 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
344 }
345
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)346 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
347 {
348 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
349 }
350
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)351 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
352 {
353 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
354 }
355
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)356 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
357 {
358 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
359 }
360
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)361 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
362 {
363 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
364 }
365
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)366 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
367 {
368 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
369 }
370
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)371 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
372 {
373 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
374 }
375
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)376 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
377 {
378 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
379 }
380
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)381 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
382 {
383 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
384 }
385
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)386 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
387 {
388 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
389 }
390
RTW89_SET_EDCA_SEL(void * cmd,u32 val)391 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
392 {
393 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
394 }
395
RTW89_SET_EDCA_BAND(void * cmd,u32 val)396 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
397 {
398 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
399 }
400
RTW89_SET_EDCA_WMM(void * cmd,u32 val)401 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
402 {
403 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
404 }
405
RTW89_SET_EDCA_AC(void * cmd,u32 val)406 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
407 {
408 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
409 }
410
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)411 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
412 {
413 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
414 }
415 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
416 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
417 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
418 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
419
420 #define FWDL_SECURITY_SECTION_TYPE 9
421 #define FWDL_SECURITY_SIGLEN 512
422
423 struct rtw89_fw_dynhdr_sec {
424 __le32 w0;
425 u8 content[];
426 } __packed;
427
428 struct rtw89_fw_dynhdr_hdr {
429 __le32 hdr_len;
430 __le32 setcion_count;
431 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
432 } __packed;
433
434 struct rtw89_fw_hdr_section {
435 __le32 w0;
436 __le32 w1;
437 __le32 w2;
438 __le32 w3;
439 } __packed;
440
441 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
442 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
443 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
444 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
445 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
446 #define FWSECTION_HDR_W1_REDL BIT(29)
447 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
448
449 struct rtw89_fw_hdr {
450 __le32 w0;
451 __le32 w1;
452 __le32 w2;
453 __le32 w3;
454 __le32 w4;
455 __le32 w5;
456 __le32 w6;
457 __le32 w7;
458 struct rtw89_fw_hdr_section sections[];
459 /* struct rtw89_fw_dynhdr_hdr (optional) */
460 } __packed;
461
462 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
463 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
464 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
465 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
466 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
467 #define FW_HDR_W3_LEN GENMASK(23, 16)
468 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
469 #define FW_HDR_W4_MONTH GENMASK(7, 0)
470 #define FW_HDR_W4_DATE GENMASK(15, 8)
471 #define FW_HDR_W4_HOUR GENMASK(23, 16)
472 #define FW_HDR_W4_MIN GENMASK(31, 24)
473 #define FW_HDR_W5_YEAR GENMASK(31, 0)
474 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
475 #define FW_HDR_W7_DYN_HDR BIT(16)
476 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
477
478 struct rtw89_fw_hdr_section_v1 {
479 __le32 w0;
480 __le32 w1;
481 __le32 w2;
482 __le32 w3;
483 } __packed;
484
485 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
486 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
487 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
488 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
489 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
490 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
491 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
492 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
493
494 struct rtw89_fw_hdr_v1 {
495 __le32 w0;
496 __le32 w1;
497 __le32 w2;
498 __le32 w3;
499 __le32 w4;
500 __le32 w5;
501 __le32 w6;
502 __le32 w7;
503 __le32 w8;
504 __le32 w9;
505 __le32 w10;
506 __le32 w11;
507 struct rtw89_fw_hdr_section_v1 sections[];
508 } __packed;
509
510 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
511 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
512 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
513 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
514 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
515 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
516 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
517 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
518 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
519 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
520 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
521 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
522 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
523 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
524 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
525
SET_FW_HDR_PART_SIZE(void * fwhdr,u32 val)526 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
527 {
528 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
529 }
530
SET_CTRL_INFO_MACID(void * table,u32 val)531 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
532 {
533 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
534 }
535
SET_CTRL_INFO_OPERATION(void * table,u32 val)536 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
537 {
538 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
539 }
540 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)541 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
542 {
543 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
544 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
545 GENMASK(8, 0));
546 }
547 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)548 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
549 {
550 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
551 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
552 BIT(9));
553 }
554 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)555 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
556 {
557 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
558 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
559 GENMASK(11, 10));
560 }
561 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)562 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
563 {
564 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
565 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
566 GENMASK(14, 12));
567 }
568 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)569 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
570 {
571 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
572 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
573 BIT(15));
574 }
575 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)576 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
577 {
578 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
579 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
580 GENMASK(19, 16));
581 }
582 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)583 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
584 {
585 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
586 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
587 BIT(20));
588 }
589 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)590 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
591 {
592 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
593 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
594 BIT(21));
595 }
596 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)597 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
598 {
599 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
600 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
601 BIT(22));
602 }
603 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)604 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
605 {
606 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
607 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
608 BIT(23));
609 }
610 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)611 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
612 {
613 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
614 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
615 BIT(25));
616 }
617 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)618 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
619 {
620 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
621 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
622 BIT(26));
623 }
624 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)625 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
626 {
627 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
628 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
629 BIT(27));
630 }
631 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)632 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
633 {
634 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
635 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
636 GENMASK(31, 28));
637 }
638 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)639 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
640 {
641 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
642 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
643 GENMASK(8, 0));
644 }
645 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)646 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
647 {
648 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
649 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
650 BIT(9));
651 }
652 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)653 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
654 {
655 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
656 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
657 BIT(10));
658 }
659 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)660 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
661 {
662 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
663 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
664 BIT(11));
665 }
666 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)667 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
668 {
669 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
670 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
671 GENMASK(15, 12));
672 }
673 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)674 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
675 {
676 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
677 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
678 GENMASK(24, 16));
679 }
680 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)681 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
682 {
683 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
684 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
685 BIT(27));
686 }
687 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)688 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
689 {
690 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
691 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
692 GENMASK(31, 28));
693 }
694 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)695 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
696 {
697 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
698 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
699 GENMASK(5, 0));
700 }
701 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)702 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
703 {
704 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
705 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
706 BIT(6));
707 }
708 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)709 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
710 {
711 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
712 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
713 BIT(7));
714 }
715 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)716 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
717 {
718 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
719 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
720 BIT(8));
721 }
722 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)723 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
724 {
725 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
726 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
727 BIT(9));
728 }
729 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)730 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
731 {
732 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
733 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
734 GENMASK(11, 10));
735 }
736 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)737 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
738 {
739 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
740 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
741 BIT(12));
742 }
743 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)744 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
745 {
746 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
747 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
748 GENMASK(14, 13));
749 }
750 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)751 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
752 {
753 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
754 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
755 GENMASK(26, 16));
756 }
757 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)758 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
759 {
760 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
761 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
762 BIT(27));
763 }
764 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)765 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
766 {
767 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
768 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
769 GENMASK(31, 28));
770 }
771 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)772 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
773 {
774 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
775 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
776 GENMASK(7, 0));
777 }
778 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)779 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
780 {
781 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
782 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
783 GENMASK(9, 8));
784 }
785 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)786 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
787 {
788 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
789 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
790 GENMASK(18, 16));
791 }
792 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)793 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
794 {
795 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
796 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
797 GENMASK(21, 19));
798 }
799 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)800 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
801 {
802 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
803 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
804 GENMASK(24, 22));
805 }
806 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)807 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
808 {
809 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
810 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
811 GENMASK(27, 25));
812 }
813 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)814 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
815 {
816 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
817 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
818 GENMASK(31, 28));
819 }
820 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)821 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
822 {
823 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
824 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
825 GENMASK(2, 0));
826 }
827 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)828 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
829 {
830 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
831 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
832 BIT(3));
833 }
834 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)835 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
836 {
837 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
838 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
839 GENMASK(7, 4));
840 }
841 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)842 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
843 {
844 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
845 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
846 BIT(8));
847 }
848 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)849 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
850 {
851 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
852 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
853 GENMASK(11, 9));
854 }
855 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)856 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
857 {
858 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
859 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
860 BIT(12));
861 }
862 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)863 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
864 {
865 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
866 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
867 BIT(13));
868 }
869 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)870 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
871 {
872 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
873 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
874 BIT(14));
875 }
876 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)877 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
878 {
879 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
880 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
881 BIT(15));
882 }
883 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)884 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
885 {
886 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
887 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
888 BIT(16));
889 }
890 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)891 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
892 {
893 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
894 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
895 BIT(17));
896 }
897 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)898 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
899 {
900 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
901 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
902 BIT(18));
903 }
904 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)905 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
906 {
907 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
908 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
909 BIT(19));
910 }
911 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)912 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
913 {
914 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
915 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
916 BIT(20));
917 }
918 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)919 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
920 {
921 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
922 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
923 BIT(21));
924 }
925 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)926 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
927 {
928 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
929 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
930 BIT(27));
931 }
932 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)933 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
934 {
935 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
936 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
937 GENMASK(31, 28));
938 }
939 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)940 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
941 {
942 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
943 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
944 GENMASK(8, 0));
945 }
946 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)947 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
948 {
949 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
950 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
951 BIT(12));
952 }
953 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)954 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
955 {
956 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
957 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
958 BIT(13));
959 }
960 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)961 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
962 {
963 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
964 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
965 GENMASK(19, 16));
966 }
967 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)968 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
969 {
970 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
971 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
972 GENMASK(21, 20));
973 }
974 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)975 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
976 {
977 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
978 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
979 GENMASK(23, 22));
980 }
981 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)982 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
983 {
984 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
985 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
986 GENMASK(25, 24));
987 }
988 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)989 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
990 {
991 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
992 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
993 GENMASK(27, 26));
994 }
995 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)996 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
997 {
998 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
999 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1000 BIT(28));
1001 }
1002 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1003 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1004 {
1005 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1006 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1007 BIT(29));
1008 }
1009 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1010 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1011 {
1012 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1013 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1014 BIT(30));
1015 }
1016 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1017 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1018 {
1019 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1020 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1021 BIT(31));
1022 }
1023
1024 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1025 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1026 {
1027 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1028 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1029 GENMASK(1, 0));
1030 }
1031
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1032 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1033 {
1034 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1035 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1036 GENMASK(3, 2));
1037 }
1038
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1039 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1040 {
1041 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1042 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1043 GENMASK(5, 4));
1044 }
1045
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1046 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1047 {
1048 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1049 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1050 GENMASK(7, 6));
1051 }
1052
1053 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1054 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1055 {
1056 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1057 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1058 GENMASK(7, 0));
1059 }
1060 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1061 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1062 {
1063 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1064 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1065 GENMASK(16, 8));
1066 }
1067 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1068 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1069 {
1070 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1071 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1072 BIT(17));
1073 }
1074 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1075 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1076 {
1077 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1078 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1079 GENMASK(19, 18));
1080 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1081 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1082 {
1083 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1084 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1085 GENMASK(21, 20));
1086 }
1087
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1088 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1089 {
1090 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1091 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1092 GENMASK(23, 22));
1093 }
1094 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1095 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1096 {
1097 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1098 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1099 GENMASK(27, 24));
1100 }
1101
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1102 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1103 {
1104 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1105 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1106 GENMASK(31, 30));
1107 }
1108 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1109 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1110 {
1111 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1112 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1113 GENMASK(2, 0));
1114 }
1115 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1116 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1117 {
1118 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1119 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1120 GENMASK(5, 3));
1121 }
1122 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1123 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1124 {
1125 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1126 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1127 GENMASK(7, 6));
1128 }
1129 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1130 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1131 {
1132 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1133 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1134 GENMASK(9, 8));
1135 }
1136 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1137 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1138 {
1139 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1140 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1141 GENMASK(11, 10));
1142 }
1143 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1144 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1145 {
1146 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1147 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1148 BIT(12));
1149 }
1150 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1151 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1152 {
1153 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1154 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1155 BIT(13));
1156 }
1157 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1158 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1159 {
1160 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1161 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1162 BIT(14));
1163 }
1164 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1165 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1166 {
1167 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1168 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1169 BIT(15));
1170 }
1171 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1172 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1173 {
1174 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1175 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1176 GENMASK(24, 16));
1177 }
1178 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1179 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1180 {
1181 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1182 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1183 GENMASK(27, 25));
1184 }
1185
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1186 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1187 {
1188 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1189 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1190 GENMASK(29, 28));
1191 }
1192
1193 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1194 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1195 {
1196 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1197 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1198 GENMASK(31, 30));
1199 }
1200
SET_DCTL_MACID_V1(void * table,u32 val)1201 static inline void SET_DCTL_MACID_V1(void *table, u32 val)
1202 {
1203 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
1204 }
1205
SET_DCTL_OPERATION_V1(void * table,u32 val)1206 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val)
1207 {
1208 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
1209 }
1210
1211 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0)
SET_DCTL_QOS_FIELD_V1(void * table,u32 val)1212 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val)
1213 {
1214 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0));
1215 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1,
1216 GENMASK(7, 0));
1217 }
1218
1219 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0)
SET_DCTL_HW_EXSEQ_MACID_V1(void * table,u32 val)1220 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val)
1221 {
1222 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8));
1223 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID,
1224 GENMASK(14, 8));
1225 }
1226
1227 #define SET_DCTL_MASK_QOS_DATA BIT(0)
SET_DCTL_QOS_DATA_V1(void * table,u32 val)1228 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val)
1229 {
1230 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
1231 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA,
1232 BIT(15));
1233 }
1234
1235 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0)
SET_DCTL_AES_IV_L_V1(void * table,u32 val)1236 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val)
1237 {
1238 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16));
1239 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L,
1240 GENMASK(31, 16));
1241 }
1242
1243 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0)
SET_DCTL_AES_IV_H_V1(void * table,u32 val)1244 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val)
1245 {
1246 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0));
1247 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H,
1248 GENMASK(31, 0));
1249 }
1250
1251 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0)
SET_DCTL_SEQ0_V1(void * table,u32 val)1252 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val)
1253 {
1254 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0));
1255 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0,
1256 GENMASK(11, 0));
1257 }
1258
1259 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0)
SET_DCTL_SEQ1_V1(void * table,u32 val)1260 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val)
1261 {
1262 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12));
1263 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1,
1264 GENMASK(23, 12));
1265 }
1266
1267 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0)
SET_DCTL_AMSDU_MAX_LEN_V1(void * table,u32 val)1268 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val)
1269 {
1270 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24));
1271 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN,
1272 GENMASK(26, 24));
1273 }
1274
1275 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0)
SET_DCTL_STA_AMSDU_EN_V1(void * table,u32 val)1276 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val)
1277 {
1278 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
1279 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN,
1280 BIT(27));
1281 }
1282
1283 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0)
SET_DCTL_CHKSUM_OFLD_EN_V1(void * table,u32 val)1284 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val)
1285 {
1286 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28));
1287 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN,
1288 BIT(28));
1289 }
1290
1291 #define SET_DCTL_MASK_WITH_LLC BIT(0)
SET_DCTL_WITH_LLC_V1(void * table,u32 val)1292 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val)
1293 {
1294 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29));
1295 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC,
1296 BIT(29));
1297 }
1298
1299 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0)
SET_DCTL_SEQ2_V1(void * table,u32 val)1300 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val)
1301 {
1302 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0));
1303 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2,
1304 GENMASK(11, 0));
1305 }
1306
1307 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0)
SET_DCTL_SEQ3_V1(void * table,u32 val)1308 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val)
1309 {
1310 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12));
1311 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3,
1312 GENMASK(23, 12));
1313 }
1314
1315 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0)
SET_DCTL_TGT_IND_V1(void * table,u32 val)1316 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val)
1317 {
1318 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24));
1319 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND,
1320 GENMASK(27, 24));
1321 }
1322
1323 #define SET_DCTL_MASK_TGT_IND_EN BIT(0)
SET_DCTL_TGT_IND_EN_V1(void * table,u32 val)1324 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val)
1325 {
1326 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28));
1327 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN,
1328 BIT(28));
1329 }
1330
1331 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0)
SET_DCTL_HTC_LB_V1(void * table,u32 val)1332 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val)
1333 {
1334 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29));
1335 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB,
1336 GENMASK(31, 29));
1337 }
1338
1339 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0)
SET_DCTL_MHDR_LEN_V1(void * table,u32 val)1340 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val)
1341 {
1342 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0));
1343 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN,
1344 GENMASK(4, 0));
1345 }
1346
1347 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0)
SET_DCTL_VLAN_TAG_VALID_V1(void * table,u32 val)1348 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val)
1349 {
1350 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5));
1351 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID,
1352 BIT(5));
1353 }
1354
1355 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0)
SET_DCTL_VLAN_TAG_SEL_V1(void * table,u32 val)1356 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val)
1357 {
1358 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6));
1359 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL,
1360 GENMASK(7, 6));
1361 }
1362
1363 #define SET_DCTL_MASK_HTC_ORDER BIT(0)
SET_DCTL_HTC_ORDER_V1(void * table,u32 val)1364 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val)
1365 {
1366 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1367 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER,
1368 BIT(8));
1369 }
1370
1371 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0)
SET_DCTL_SEC_KEY_ID_V1(void * table,u32 val)1372 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val)
1373 {
1374 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9));
1375 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID,
1376 GENMASK(10, 9));
1377 }
1378
1379 #define SET_DCTL_MASK_WAPI BIT(0)
SET_DCTL_WAPI_V1(void * table,u32 val)1380 static inline void SET_DCTL_WAPI_V1(void *table, u32 val)
1381 {
1382 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1383 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI,
1384 BIT(15));
1385 }
1386
1387 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0)
SET_DCTL_SEC_ENT_MODE_V1(void * table,u32 val)1388 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val)
1389 {
1390 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16));
1391 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE,
1392 GENMASK(17, 16));
1393 }
1394
1395 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0)
SET_DCTL_SEC_ENT0_KEYID_V1(void * table,u32 val)1396 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val)
1397 {
1398 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18));
1399 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1400 GENMASK(19, 18));
1401 }
1402
SET_DCTL_SEC_ENT1_KEYID_V1(void * table,u32 val)1403 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val)
1404 {
1405 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20));
1406 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1407 GENMASK(21, 20));
1408 }
1409
SET_DCTL_SEC_ENT2_KEYID_V1(void * table,u32 val)1410 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val)
1411 {
1412 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22));
1413 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1414 GENMASK(23, 22));
1415 }
1416
SET_DCTL_SEC_ENT3_KEYID_V1(void * table,u32 val)1417 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val)
1418 {
1419 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24));
1420 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1421 GENMASK(25, 24));
1422 }
1423
SET_DCTL_SEC_ENT4_KEYID_V1(void * table,u32 val)1424 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val)
1425 {
1426 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26));
1427 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1428 GENMASK(27, 26));
1429 }
1430
SET_DCTL_SEC_ENT5_KEYID_V1(void * table,u32 val)1431 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val)
1432 {
1433 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28));
1434 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1435 GENMASK(29, 28));
1436 }
1437
SET_DCTL_SEC_ENT6_KEYID_V1(void * table,u32 val)1438 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val)
1439 {
1440 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30));
1441 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1442 GENMASK(31, 30));
1443 }
1444
1445 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0)
SET_DCTL_SEC_ENT_VALID_V1(void * table,u32 val)1446 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val)
1447 {
1448 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0));
1449 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID,
1450 GENMASK(7, 0));
1451 }
1452
1453 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0)
SET_DCTL_SEC_ENT0_V1(void * table,u32 val)1454 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val)
1455 {
1456 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8));
1457 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1458 GENMASK(15, 8));
1459 }
1460
SET_DCTL_SEC_ENT1_V1(void * table,u32 val)1461 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val)
1462 {
1463 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16));
1464 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1465 GENMASK(23, 16));
1466 }
1467
SET_DCTL_SEC_ENT2_V1(void * table,u32 val)1468 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val)
1469 {
1470 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24));
1471 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1472 GENMASK(31, 24));
1473 }
1474
SET_DCTL_SEC_ENT3_V1(void * table,u32 val)1475 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val)
1476 {
1477 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1478 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1479 GENMASK(7, 0));
1480 }
1481
SET_DCTL_SEC_ENT4_V1(void * table,u32 val)1482 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val)
1483 {
1484 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8));
1485 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1486 GENMASK(15, 8));
1487 }
1488
SET_DCTL_SEC_ENT5_V1(void * table,u32 val)1489 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val)
1490 {
1491 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16));
1492 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1493 GENMASK(23, 16));
1494 }
1495
SET_DCTL_SEC_ENT6_V1(void * table,u32 val)1496 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val)
1497 {
1498 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24));
1499 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1500 GENMASK(31, 24));
1501 }
1502
SET_BCN_UPD_PORT(void * h2c,u32 val)1503 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val)
1504 {
1505 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1506 }
1507
SET_BCN_UPD_MBSSID(void * h2c,u32 val)1508 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val)
1509 {
1510 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1511 }
1512
SET_BCN_UPD_BAND(void * h2c,u32 val)1513 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val)
1514 {
1515 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1516 }
1517
SET_BCN_UPD_GRP_IE_OFST(void * h2c,u32 val)1518 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val)
1519 {
1520 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24));
1521 }
1522
SET_BCN_UPD_MACID(void * h2c,u32 val)1523 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val)
1524 {
1525 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1526 }
1527
SET_BCN_UPD_SSN_SEL(void * h2c,u32 val)1528 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val)
1529 {
1530 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8));
1531 }
1532
SET_BCN_UPD_SSN_MODE(void * h2c,u32 val)1533 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val)
1534 {
1535 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10));
1536 }
1537
SET_BCN_UPD_RATE(void * h2c,u32 val)1538 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val)
1539 {
1540 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12));
1541 }
1542
SET_BCN_UPD_TXPWR(void * h2c,u32 val)1543 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val)
1544 {
1545 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21));
1546 }
1547
SET_BCN_UPD_TXINFO_CTRL_EN(void * h2c,u32 val)1548 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val)
1549 {
1550 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0));
1551 }
1552
SET_BCN_UPD_NTX_PATH_EN(void * h2c,u32 val)1553 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val)
1554 {
1555 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1));
1556 }
1557
SET_BCN_UPD_PATH_MAP_A(void * h2c,u32 val)1558 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val)
1559 {
1560 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5));
1561 }
1562
SET_BCN_UPD_PATH_MAP_B(void * h2c,u32 val)1563 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val)
1564 {
1565 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7));
1566 }
1567
SET_BCN_UPD_PATH_MAP_C(void * h2c,u32 val)1568 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val)
1569 {
1570 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9));
1571 }
1572
SET_BCN_UPD_PATH_MAP_D(void * h2c,u32 val)1573 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val)
1574 {
1575 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11));
1576 }
1577
SET_BCN_UPD_PATH_ANTSEL_A(void * h2c,u32 val)1578 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val)
1579 {
1580 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13));
1581 }
1582
SET_BCN_UPD_PATH_ANTSEL_B(void * h2c,u32 val)1583 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val)
1584 {
1585 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14));
1586 }
1587
SET_BCN_UPD_PATH_ANTSEL_C(void * h2c,u32 val)1588 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val)
1589 {
1590 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15));
1591 }
1592
SET_BCN_UPD_PATH_ANTSEL_D(void * h2c,u32 val)1593 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val)
1594 {
1595 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16));
1596 }
1597
SET_BCN_UPD_CSA_OFST(void * h2c,u32 val)1598 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val)
1599 {
1600 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17));
1601 }
1602
SET_FWROLE_MAINTAIN_MACID(void * h2c,u32 val)1603 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1604 {
1605 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1606 }
1607
SET_FWROLE_MAINTAIN_SELF_ROLE(void * h2c,u32 val)1608 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1609 {
1610 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1611 }
1612
SET_FWROLE_MAINTAIN_UPD_MODE(void * h2c,u32 val)1613 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1614 {
1615 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1616 }
1617
SET_FWROLE_MAINTAIN_WIFI_ROLE(void * h2c,u32 val)1618 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1619 {
1620 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1621 }
1622
SET_JOININFO_MACID(void * h2c,u32 val)1623 static inline void SET_JOININFO_MACID(void *h2c, u32 val)
1624 {
1625 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1626 }
1627
SET_JOININFO_OP(void * h2c,u32 val)1628 static inline void SET_JOININFO_OP(void *h2c, u32 val)
1629 {
1630 le32p_replace_bits((__le32 *)h2c, val, BIT(8));
1631 }
1632
SET_JOININFO_BAND(void * h2c,u32 val)1633 static inline void SET_JOININFO_BAND(void *h2c, u32 val)
1634 {
1635 le32p_replace_bits((__le32 *)h2c, val, BIT(9));
1636 }
1637
SET_JOININFO_WMM(void * h2c,u32 val)1638 static inline void SET_JOININFO_WMM(void *h2c, u32 val)
1639 {
1640 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10));
1641 }
1642
SET_JOININFO_TGR(void * h2c,u32 val)1643 static inline void SET_JOININFO_TGR(void *h2c, u32 val)
1644 {
1645 le32p_replace_bits((__le32 *)h2c, val, BIT(12));
1646 }
1647
SET_JOININFO_ISHESTA(void * h2c,u32 val)1648 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val)
1649 {
1650 le32p_replace_bits((__le32 *)h2c, val, BIT(13));
1651 }
1652
SET_JOININFO_DLBW(void * h2c,u32 val)1653 static inline void SET_JOININFO_DLBW(void *h2c, u32 val)
1654 {
1655 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14));
1656 }
1657
SET_JOININFO_TF_MAC_PAD(void * h2c,u32 val)1658 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val)
1659 {
1660 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16));
1661 }
1662
SET_JOININFO_DL_T_PE(void * h2c,u32 val)1663 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val)
1664 {
1665 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18));
1666 }
1667
SET_JOININFO_PORT_ID(void * h2c,u32 val)1668 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val)
1669 {
1670 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21));
1671 }
1672
SET_JOININFO_NET_TYPE(void * h2c,u32 val)1673 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val)
1674 {
1675 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24));
1676 }
1677
SET_JOININFO_WIFI_ROLE(void * h2c,u32 val)1678 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val)
1679 {
1680 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26));
1681 }
1682
SET_JOININFO_SELF_ROLE(void * h2c,u32 val)1683 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val)
1684 {
1685 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30));
1686 }
1687
1688 struct rtw89_h2c_notify_dbcc {
1689 __le32 w0;
1690 } __packed;
1691
1692 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1693
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1694 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1695 {
1696 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1697 }
1698
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1699 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1700 {
1701 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1702 }
1703
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1704 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1705 {
1706 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1707 }
1708
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1709 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1710 {
1711 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1712 }
1713
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1714 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1715 {
1716 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1717 }
1718
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1719 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1720 {
1721 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1722 }
1723
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1724 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1725 {
1726 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1727 }
1728
SET_LOG_CFG_PATH(void * h2c,u32 val)1729 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1730 {
1731 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1732 }
1733
SET_LOG_CFG_COMP(void * h2c,u32 val)1734 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1735 {
1736 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1737 }
1738
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1739 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1740 {
1741 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1742 }
1743
SET_BA_CAM_VALID(void * h2c,u32 val)1744 static inline void SET_BA_CAM_VALID(void *h2c, u32 val)
1745 {
1746 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1747 }
1748
SET_BA_CAM_INIT_REQ(void * h2c,u32 val)1749 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val)
1750 {
1751 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1752 }
1753
SET_BA_CAM_ENTRY_IDX(void * h2c,u32 val)1754 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val)
1755 {
1756 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2));
1757 }
1758
SET_BA_CAM_TID(void * h2c,u32 val)1759 static inline void SET_BA_CAM_TID(void *h2c, u32 val)
1760 {
1761 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4));
1762 }
1763
SET_BA_CAM_MACID(void * h2c,u32 val)1764 static inline void SET_BA_CAM_MACID(void *h2c, u32 val)
1765 {
1766 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1767 }
1768
SET_BA_CAM_BMAP_SIZE(void * h2c,u32 val)1769 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val)
1770 {
1771 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1772 }
1773
SET_BA_CAM_SSN(void * h2c,u32 val)1774 static inline void SET_BA_CAM_SSN(void *h2c, u32 val)
1775 {
1776 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20));
1777 }
1778
SET_BA_CAM_UID(void * h2c,u32 val)1779 static inline void SET_BA_CAM_UID(void *h2c, u32 val)
1780 {
1781 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0));
1782 }
1783
SET_BA_CAM_STD_EN(void * h2c,u32 val)1784 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val)
1785 {
1786 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8));
1787 }
1788
SET_BA_CAM_BAND(void * h2c,u32 val)1789 static inline void SET_BA_CAM_BAND(void *h2c, u32 val)
1790 {
1791 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9));
1792 }
1793
SET_BA_CAM_ENTRY_IDX_V1(void * h2c,u32 val)1794 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val)
1795 {
1796 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28));
1797 }
1798
SET_LPS_PARM_MACID(void * h2c,u32 val)1799 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1800 {
1801 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1802 }
1803
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1804 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1805 {
1806 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1807 }
1808
SET_LPS_PARM_RLBM(void * h2c,u32 val)1809 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1810 {
1811 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1812 }
1813
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1814 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1815 {
1816 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1817 }
1818
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1819 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1820 {
1821 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1822 }
1823
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1824 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1825 {
1826 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1827 }
1828
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1829 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1830 {
1831 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1832 }
1833
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1834 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1835 {
1836 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1837 }
1838
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1839 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1840 {
1841 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1842 }
1843
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1844 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1845 {
1846 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1847 }
1848
RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void * cmd,u32 val)1849 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1850 {
1851 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1852 }
1853
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1854 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1855 {
1856 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1857 }
1858
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1859 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1860 {
1861 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1862 }
1863
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1864 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1865 {
1866 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1867 }
1868
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1869 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1870 {
1871 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1872 }
1873
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1874 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1875 {
1876 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1877 }
1878
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1879 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1880 {
1881 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1882 }
1883
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)1884 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1885 {
1886 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1887 }
1888
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)1889 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1890 {
1891 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1892 }
1893
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)1894 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1895 {
1896 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1897 }
1898
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)1899 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1900 {
1901 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1902 }
1903
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)1904 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1905 {
1906 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1907 }
1908
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)1909 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1910 {
1911 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1912 }
1913
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)1914 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1915 {
1916 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1917 }
1918
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)1919 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1920 {
1921 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1922 }
1923
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)1924 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1925 {
1926 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1927 }
1928
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)1929 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1930 {
1931 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1932 }
1933
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)1934 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1935 {
1936 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1937 }
1938
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)1939 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1940 {
1941 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1942 }
1943
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)1944 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1945 {
1946 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1947 }
1948
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)1949 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1950 {
1951 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1952 }
1953
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)1954 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1955 {
1956 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1957 }
1958
RTW89_SET_WOW_GLOBAL_ENABLE(void * h2c,u32 val)1959 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
1960 {
1961 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1962 }
1963
RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void * h2c,u32 val)1964 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
1965 {
1966 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1967 }
1968
RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void * h2c,u32 val)1969 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
1970 {
1971 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1972 }
1973
RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void * h2c,u32 val)1974 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
1975 {
1976 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1977 }
1978
RTW89_SET_WOW_GLOBAL_MAC_ID(void * h2c,u32 val)1979 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
1980 {
1981 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1982 }
1983
RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void * h2c,u32 val)1984 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
1985 {
1986 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1987 }
1988
RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void * h2c,u32 val)1989 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
1990 {
1991 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1992 }
1993
RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void * h2c,u32 val)1994 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
1995 {
1996 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1997 }
1998
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)1999 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2000 {
2001 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2002 }
2003
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)2004 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2005 {
2006 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2007 }
2008
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)2009 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2010 {
2011 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2012 }
2013
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)2014 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2015 {
2016 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2017 }
2018
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)2019 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2020 {
2021 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2022 }
2023
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)2024 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2025 {
2026 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2027 }
2028
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)2029 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2030 {
2031 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2032 }
2033
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)2034 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2035 {
2036 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2037 }
2038
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)2039 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2040 {
2041 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2042 }
2043
RTW89_SET_WOW_CAM_UPD_R_W(void * h2c,u32 val)2044 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2045 {
2046 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2047 }
2048
RTW89_SET_WOW_CAM_UPD_IDX(void * h2c,u32 val)2049 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2050 {
2051 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2052 }
2053
RTW89_SET_WOW_CAM_UPD_WKFM1(void * h2c,u32 val)2054 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2055 {
2056 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2057 }
2058
RTW89_SET_WOW_CAM_UPD_WKFM2(void * h2c,u32 val)2059 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2060 {
2061 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2062 }
2063
RTW89_SET_WOW_CAM_UPD_WKFM3(void * h2c,u32 val)2064 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2065 {
2066 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2067 }
2068
RTW89_SET_WOW_CAM_UPD_WKFM4(void * h2c,u32 val)2069 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2070 {
2071 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2072 }
2073
RTW89_SET_WOW_CAM_UPD_CRC(void * h2c,u32 val)2074 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2075 {
2076 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2077 }
2078
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void * h2c,u32 val)2079 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2080 {
2081 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2082 }
2083
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void * h2c,u32 val)2084 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2085 {
2086 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2087 }
2088
RTW89_SET_WOW_CAM_UPD_UC(void * h2c,u32 val)2089 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2090 {
2091 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2092 }
2093
RTW89_SET_WOW_CAM_UPD_MC(void * h2c,u32 val)2094 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2095 {
2096 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2097 }
2098
RTW89_SET_WOW_CAM_UPD_BC(void * h2c,u32 val)2099 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2100 {
2101 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2102 }
2103
RTW89_SET_WOW_CAM_UPD_VALID(void * h2c,u32 val)2104 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2105 {
2106 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2107 }
2108
2109 enum rtw89_btc_btf_h2c_class {
2110 BTFC_SET = 0x10,
2111 BTFC_GET = 0x11,
2112 BTFC_FW_EVENT = 0x12,
2113 };
2114
2115 enum rtw89_btc_btf_set {
2116 SET_REPORT_EN = 0x0,
2117 SET_SLOT_TABLE,
2118 SET_MREG_TABLE,
2119 SET_CX_POLICY,
2120 SET_GPIO_DBG,
2121 SET_DRV_INFO,
2122 SET_DRV_EVENT,
2123 SET_BT_WREG_ADDR,
2124 SET_BT_WREG_VAL,
2125 SET_BT_RREG_ADDR,
2126 SET_BT_WL_CH_INFO,
2127 SET_BT_INFO_REPORT,
2128 SET_BT_IGNORE_WLAN_ACT,
2129 SET_BT_TX_PWR,
2130 SET_BT_LNA_CONSTRAIN,
2131 SET_BT_GOLDEN_RX_RANGE,
2132 SET_BT_PSD_REPORT,
2133 SET_H2C_TEST,
2134 SET_MAX1,
2135 };
2136
2137 enum rtw89_btc_cxdrvinfo {
2138 CXDRVINFO_INIT = 0,
2139 CXDRVINFO_ROLE,
2140 CXDRVINFO_DBCC,
2141 CXDRVINFO_SMAP,
2142 CXDRVINFO_RFK,
2143 CXDRVINFO_RUN,
2144 CXDRVINFO_CTRL,
2145 CXDRVINFO_SCAN,
2146 CXDRVINFO_TRX, /* WL traffic to WL fw */
2147 CXDRVINFO_MAX,
2148 };
2149
2150 enum rtw89_scan_mode {
2151 RTW89_SCAN_IMMEDIATE,
2152 };
2153
2154 enum rtw89_scan_type {
2155 RTW89_SCAN_ONCE,
2156 };
2157
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2158 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2159 {
2160 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2161 }
2162
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2163 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2164 {
2165 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2166 }
2167
2168 struct rtw89_h2c_cxhdr {
2169 u8 type;
2170 u8 len;
2171 } __packed;
2172
2173 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2174
2175 struct rtw89_h2c_cxinit {
2176 struct rtw89_h2c_cxhdr hdr;
2177 u8 ant_type;
2178 u8 ant_num;
2179 u8 ant_iso;
2180 u8 ant_info;
2181 u8 mod_rfe;
2182 u8 mod_cv;
2183 u8 mod_info;
2184 u8 mod_adie_kt;
2185 u8 wl_gch;
2186 u8 info;
2187 u8 rsvd;
2188 u8 rsvd1;
2189 } __packed;
2190
2191 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2192 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2193 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2194 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2195
2196 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2197 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2198 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2199 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2200
2201 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2202 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2203 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2204 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2205 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2206
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2207 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2208 {
2209 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2210 }
2211
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2212 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2213 {
2214 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2215 }
2216
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2217 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2218 {
2219 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2220 }
2221
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2222 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2223 {
2224 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2225 }
2226
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2227 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2228 {
2229 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2230 }
2231
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2232 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2233 {
2234 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2235 }
2236
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2237 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2238 {
2239 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2240 }
2241
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2242 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2243 {
2244 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2245 }
2246
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2247 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2248 {
2249 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2250 }
2251
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2252 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2253 {
2254 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2255 }
2256
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2257 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2258 {
2259 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2260 }
2261
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2262 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2263 {
2264 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2265 }
2266
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2267 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2268 {
2269 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2270 }
2271
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2272 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2273 {
2274 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2275 }
2276
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2277 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2278 {
2279 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2280 }
2281
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2282 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2283 {
2284 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2285 }
2286
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2287 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2288 {
2289 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2290 }
2291
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2292 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2293 {
2294 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2295 }
2296
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2297 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2298 {
2299 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2300 }
2301
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2302 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2303 {
2304 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2305 }
2306
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2307 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2308 {
2309 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2310 }
2311
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2312 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2313 {
2314 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2315 }
2316
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2317 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2318 {
2319 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2320 }
2321
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2322 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2323 {
2324 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2325 }
2326
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2327 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2328 {
2329 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2330 }
2331
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2332 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2333 {
2334 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2335 }
2336
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2337 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2338 {
2339 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2340 }
2341
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2342 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2343 {
2344 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2345 }
2346
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2347 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2348 {
2349 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2350 }
2351
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2352 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2353 {
2354 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2355 }
2356
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2357 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2358 {
2359 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2360 }
2361
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2362 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2363 {
2364 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2365 }
2366
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2367 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2368 {
2369 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2370 }
2371
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2372 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2373 {
2374 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2375 }
2376
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2377 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2378 {
2379 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2380 }
2381
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2382 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2383 {
2384 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2385 }
2386
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2387 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2388 {
2389 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2390 }
2391
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2392 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2393 {
2394 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2395 }
2396
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2397 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2398 {
2399 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2400 }
2401
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2402 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2403 {
2404 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2405 }
2406
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2407 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2408 {
2409 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2410 }
2411
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2412 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2413 {
2414 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2415 }
2416
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2417 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2418 {
2419 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2420 }
2421
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2422 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2423 {
2424 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2425 }
2426
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2427 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2428 {
2429 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2430 }
2431
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2432 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2433 {
2434 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2435 }
2436
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2437 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2438 {
2439 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2440 }
2441
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2442 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2443 {
2444 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2445 }
2446
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2447 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2448 {
2449 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2450 }
2451
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2452 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2453 {
2454 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2455 }
2456
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2457 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2458 {
2459 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2460 }
2461
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2462 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2463 {
2464 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2465 }
2466
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2467 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2468 {
2469 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2470 }
2471
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2472 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2473 {
2474 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2475 }
2476
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2477 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2478 {
2479 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2480 }
2481
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2482 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2483 {
2484 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2485 }
2486
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2487 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2488 {
2489 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2490 }
2491
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2492 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2493 {
2494 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2495 }
2496
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2497 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2498 {
2499 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2500 }
2501
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2502 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2503 {
2504 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2505 }
2506
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2507 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2508 {
2509 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2510 }
2511
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2512 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2513 {
2514 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2515 }
2516
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2517 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2518 {
2519 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2520 }
2521
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2522 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2523 {
2524 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2525 }
2526
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2527 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2528 {
2529 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2530 }
2531
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2532 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2533 {
2534 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2535 }
2536
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2537 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2538 {
2539 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2540 }
2541
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2542 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2543 {
2544 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2545 }
2546
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2547 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2548 {
2549 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2550 }
2551
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2552 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2553 {
2554 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2555 }
2556
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2557 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2558 {
2559 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2560 }
2561
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2562 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2563 {
2564 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2565 }
2566
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2567 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2568 {
2569 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2570 }
2571
RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void * cmd,u32 val)2572 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val)
2573 {
2574 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2575 }
2576
RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void * cmd,u32 val)2577 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val)
2578 {
2579 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2580 }
2581
RTW89_SET_FWCMD_CHINFO_PERIOD(void * cmd,u32 val)2582 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val)
2583 {
2584 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2585 }
2586
RTW89_SET_FWCMD_CHINFO_DWELL(void * cmd,u32 val)2587 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val)
2588 {
2589 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2590 }
2591
RTW89_SET_FWCMD_CHINFO_CENTER_CH(void * cmd,u32 val)2592 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val)
2593 {
2594 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16));
2595 }
2596
RTW89_SET_FWCMD_CHINFO_PRI_CH(void * cmd,u32 val)2597 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val)
2598 {
2599 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24));
2600 }
2601
RTW89_SET_FWCMD_CHINFO_BW(void * cmd,u32 val)2602 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val)
2603 {
2604 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0));
2605 }
2606
RTW89_SET_FWCMD_CHINFO_ACTION(void * cmd,u32 val)2607 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val)
2608 {
2609 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3));
2610 }
2611
RTW89_SET_FWCMD_CHINFO_NUM_PKT(void * cmd,u32 val)2612 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val)
2613 {
2614 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8));
2615 }
2616
RTW89_SET_FWCMD_CHINFO_TX(void * cmd,u32 val)2617 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val)
2618 {
2619 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12));
2620 }
2621
RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void * cmd,u32 val)2622 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val)
2623 {
2624 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13));
2625 }
2626
RTW89_SET_FWCMD_CHINFO_BAND(void * cmd,u32 val)2627 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val)
2628 {
2629 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14));
2630 }
2631
RTW89_SET_FWCMD_CHINFO_PKT_ID(void * cmd,u32 val)2632 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val)
2633 {
2634 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2635 }
2636
RTW89_SET_FWCMD_CHINFO_DFS(void * cmd,u32 val)2637 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val)
2638 {
2639 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24));
2640 }
2641
RTW89_SET_FWCMD_CHINFO_TX_NULL(void * cmd,u32 val)2642 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val)
2643 {
2644 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25));
2645 }
2646
RTW89_SET_FWCMD_CHINFO_RANDOM(void * cmd,u32 val)2647 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val)
2648 {
2649 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26));
2650 }
2651
RTW89_SET_FWCMD_CHINFO_CFG_TX(void * cmd,u32 val)2652 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val)
2653 {
2654 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27));
2655 }
2656
RTW89_SET_FWCMD_CHINFO_PKT0(void * cmd,u32 val)2657 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val)
2658 {
2659 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0));
2660 }
2661
RTW89_SET_FWCMD_CHINFO_PKT1(void * cmd,u32 val)2662 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val)
2663 {
2664 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8));
2665 }
2666
RTW89_SET_FWCMD_CHINFO_PKT2(void * cmd,u32 val)2667 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val)
2668 {
2669 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2670 }
2671
RTW89_SET_FWCMD_CHINFO_PKT3(void * cmd,u32 val)2672 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val)
2673 {
2674 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24));
2675 }
2676
RTW89_SET_FWCMD_CHINFO_PKT4(void * cmd,u32 val)2677 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val)
2678 {
2679 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0));
2680 }
2681
RTW89_SET_FWCMD_CHINFO_PKT5(void * cmd,u32 val)2682 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val)
2683 {
2684 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8));
2685 }
2686
RTW89_SET_FWCMD_CHINFO_PKT6(void * cmd,u32 val)2687 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val)
2688 {
2689 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16));
2690 }
2691
RTW89_SET_FWCMD_CHINFO_PKT7(void * cmd,u32 val)2692 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val)
2693 {
2694 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24));
2695 }
2696
RTW89_SET_FWCMD_CHINFO_POWER_IDX(void * cmd,u32 val)2697 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val)
2698 {
2699 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0));
2700 }
2701
2702 struct rtw89_h2c_scanofld {
2703 __le32 w0;
2704 __le32 w1;
2705 __le32 w2;
2706 __le32 tsf_high;
2707 __le32 tsf_low;
2708 __le32 w5;
2709 __le32 w6;
2710 } __packed;
2711
2712 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2713 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2714 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2715 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2716 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2717 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2718 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2719 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2720 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2721 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2722 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2723 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2724 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2725 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2726 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2727 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2728
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2729 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2730 {
2731 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2732 }
2733
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2734 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2735 {
2736 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2737 }
2738
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2739 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2740 {
2741 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2742 }
2743
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2744 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2745 {
2746 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2747 }
2748
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2749 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2750 {
2751 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2752 }
2753
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2754 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2755 {
2756 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2757 }
2758
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2759 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2760 {
2761 *((__le32 *)cmd + 1) = val;
2762 }
2763
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2764 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2765 {
2766 *((__le32 *)cmd + 2) = val;
2767 }
2768
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2769 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2770 {
2771 *((__le32 *)cmd + 3) = val;
2772 }
2773
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2774 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2775 {
2776 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2777 }
2778
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2779 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2780 {
2781 u8 ctwnd;
2782
2783 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2784 return;
2785 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2786 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2787 }
2788
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2789 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2790 {
2791 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2792 }
2793
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2794 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2795 {
2796 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2797 }
2798
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2799 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2800 {
2801 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2802 }
2803
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)2804 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2805 {
2806 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2807 }
2808
2809 enum rtw89_fw_mcc_c2h_rpt_cfg {
2810 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2811 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2812 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2813 };
2814
2815 struct rtw89_fw_mcc_add_req {
2816 u8 macid;
2817 u8 central_ch_seg0;
2818 u8 central_ch_seg1;
2819 u8 primary_ch;
2820 enum rtw89_bandwidth bandwidth: 4;
2821 u32 group: 2;
2822 u32 c2h_rpt: 2;
2823 u32 dis_tx_null: 1;
2824 u32 dis_sw_retry: 1;
2825 u32 in_curr_ch: 1;
2826 u32 sw_retry_count: 3;
2827 u32 tx_null_early: 4;
2828 u32 btc_in_2g: 1;
2829 u32 pta_en: 1;
2830 u32 rfk_by_pass: 1;
2831 u32 ch_band_type: 2;
2832 u32 rsvd0: 9;
2833 u32 duration;
2834 u8 courtesy_en;
2835 u8 courtesy_num;
2836 u8 courtesy_target;
2837 u8 rsvd1;
2838 };
2839
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)2840 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2841 {
2842 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2843 }
2844
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)2845 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2846 {
2847 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2848 }
2849
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)2850 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2851 {
2852 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2853 }
2854
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)2855 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2856 {
2857 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2858 }
2859
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)2860 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2861 {
2862 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2863 }
2864
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)2865 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2866 {
2867 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2868 }
2869
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)2870 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2871 {
2872 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2873 }
2874
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)2875 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2876 {
2877 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2878 }
2879
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)2880 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2881 {
2882 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2883 }
2884
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)2885 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2886 {
2887 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2888 }
2889
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)2890 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2891 {
2892 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2893 }
2894
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)2895 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2896 {
2897 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2898 }
2899
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)2900 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2901 {
2902 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2903 }
2904
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)2905 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2906 {
2907 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2908 }
2909
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)2910 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
2911 {
2912 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2913 }
2914
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)2915 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
2916 {
2917 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
2918 }
2919
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)2920 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
2921 {
2922 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2923 }
2924
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)2925 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
2926 {
2927 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
2928 }
2929
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)2930 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
2931 {
2932 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
2933 }
2934
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)2935 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
2936 {
2937 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
2938 }
2939
2940 enum rtw89_fw_mcc_old_group_actions {
2941 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
2942 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
2943 };
2944
2945 struct rtw89_fw_mcc_start_req {
2946 u32 group: 2;
2947 u32 btc_in_group: 1;
2948 u32 old_group_action: 2;
2949 u32 old_group: 2;
2950 u32 rsvd0: 9;
2951 u32 notify_cnt: 3;
2952 u32 rsvd1: 2;
2953 u32 notify_rxdbg_en: 1;
2954 u32 rsvd2: 2;
2955 u32 macid: 8;
2956 u32 tsf_low;
2957 u32 tsf_high;
2958 };
2959
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)2960 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
2961 {
2962 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
2963 }
2964
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)2965 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
2966 {
2967 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
2968 }
2969
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)2970 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
2971 {
2972 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
2973 }
2974
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)2975 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
2976 {
2977 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
2978 }
2979
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)2980 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
2981 {
2982 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
2983 }
2984
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)2985 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
2986 {
2987 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2988 }
2989
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)2990 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
2991 {
2992 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2993 }
2994
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)2995 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
2996 {
2997 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
2998 }
2999
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3000 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3001 {
3002 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3003 }
3004
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3005 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3006 {
3007 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3008 }
3009
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3010 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3011 {
3012 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3013 }
3014
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3015 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3016 {
3017 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3018 }
3019
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3020 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3021 {
3022 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3023 }
3024
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3025 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3026 {
3027 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3028 }
3029
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3030 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3031 {
3032 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3033 }
3034
3035 struct rtw89_fw_mcc_tsf_req {
3036 u8 group: 2;
3037 u8 rsvd0: 6;
3038 u8 macid_x;
3039 u8 macid_y;
3040 u8 rsvd1;
3041 };
3042
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3043 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3044 {
3045 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3046 }
3047
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3048 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3049 {
3050 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3051 }
3052
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3053 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3054 {
3055 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3056 }
3057
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3058 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3059 {
3060 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3061 }
3062
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3063 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3064 {
3065 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3066 }
3067
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3068 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3069 {
3070 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3071 }
3072
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3073 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3074 u8 *bitmap, u8 len)
3075 {
3076 memcpy((__le32 *)cmd + 1, bitmap, len);
3077 }
3078
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3079 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3080 {
3081 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3082 }
3083
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3084 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3085 {
3086 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3087 }
3088
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3089 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3090 {
3091 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3092 }
3093
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3094 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3095 {
3096 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3097 }
3098
3099 struct rtw89_fw_mcc_duration {
3100 u32 group: 2;
3101 u32 btc_in_group: 1;
3102 u32 rsvd0: 5;
3103 u32 start_macid: 8;
3104 u32 macid_x: 8;
3105 u32 macid_y: 8;
3106 u32 start_tsf_low;
3107 u32 start_tsf_high;
3108 u32 duration_x;
3109 u32 duration_y;
3110 };
3111
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3112 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3113 {
3114 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3115 }
3116
3117 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3118 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3119 {
3120 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3121 }
3122
3123 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3124 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3125 {
3126 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3127 }
3128
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3129 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3130 {
3131 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3132 }
3133
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3134 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3135 {
3136 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3137 }
3138
3139 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3140 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3141 {
3142 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3143 }
3144
3145 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3146 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3147 {
3148 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3149 }
3150
3151 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3152 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3153 {
3154 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3155 }
3156
3157 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3158 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3159 {
3160 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3161 }
3162
3163 #define RTW89_C2H_HEADER_LEN 8
3164
3165 struct rtw89_c2h_hdr {
3166 __le32 w0;
3167 __le32 w1;
3168 } __packed;
3169
3170 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3171 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3172 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3173 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3174
3175 struct rtw89_fw_c2h_attr {
3176 u8 category;
3177 u8 class;
3178 u8 func;
3179 u16 len;
3180 };
3181
RTW89_SKB_C2H_CB(struct sk_buff * skb)3182 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3183 {
3184 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3185
3186 return (struct rtw89_fw_c2h_attr *)skb->cb;
3187 }
3188
3189 struct rtw89_c2h_done_ack {
3190 __le32 w0;
3191 __le32 w1;
3192 __le32 w2;
3193 } __packed;
3194
3195 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3196 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3197 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3198 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3199 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3200
3201 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3202 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3203 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3204 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3205 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3206 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3207 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3208 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3209
3210 struct rtw89_fw_c2h_log_fmt {
3211 __le16 signature;
3212 u8 feature;
3213 u8 syntax;
3214 __le32 fmt_id;
3215 u8 file_num;
3216 __le16 line_num;
3217 u8 argc;
3218 union {
3219 DECLARE_FLEX_ARRAY(u8, raw);
3220 DECLARE_FLEX_ARRAY(__le32, argv);
3221 } __packed u;
3222 } __packed;
3223
3224 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3225 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3226 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3227 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3228 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3229
3230 struct rtw89_c2h_mac_bcnfltr_rpt {
3231 __le32 w0;
3232 __le32 w1;
3233 __le32 w2;
3234 } __packed;
3235
3236 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3237 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3238 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3239 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3240
3241 struct rtw89_c2h_ra_rpt {
3242 struct rtw89_c2h_hdr hdr;
3243 __le32 w2;
3244 __le32 w3;
3245 } __packed;
3246
3247 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3248 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3249 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3250 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3251 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3252 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3253 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3254 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3255 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3256
3257 /* For WiFi 6 chips:
3258 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3259 * HT-new: [6:5]: NA, [4:0]: MCS
3260 * For WiFi 7 chips (V1):
3261 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3262 */
3263 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3264 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3265 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3266 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3267 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3268 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3269 FIELD_PREP(GENMASK(2, 0), mcs))
3270
3271 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3272 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3273 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3274 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3275 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3276 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3277
3278 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \
3279 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3280 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \
3281 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16))
3282 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \
3283 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20))
3284 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \
3285 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
3286 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \
3287 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0))
3288 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \
3289 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4))
3290 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
3291 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
3292
3293 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3294 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3295 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3296 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3297
3298 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3299 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3300 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3301 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3302 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3303 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3304
3305 struct rtw89_mac_mcc_tsf_rpt {
3306 u32 macid_x;
3307 u32 macid_y;
3308 u32 tsf_x_low;
3309 u32 tsf_x_high;
3310 u32 tsf_y_low;
3311 u32 tsf_y_high;
3312 };
3313
3314 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3315
3316 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3317 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3318 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3319 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3320 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3321 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3322 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3323 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3324 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3325 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3326 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3327 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3328 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3329 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3330
3331 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3332 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3333 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3334 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3335 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3336 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3337 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3338 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3339 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3340 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3341
3342 struct rtw89_c2h_pkt_ofld_rsp {
3343 __le32 w0;
3344 __le32 w1;
3345 __le32 w2;
3346 } __packed;
3347
3348 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3349 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3350 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3351
3352 struct rtw89_h2c_bcnfltr {
3353 __le32 w0;
3354 } __packed;
3355
3356 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3357 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3358 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3359 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3360 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3361 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3362 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3363 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3364
3365 struct rtw89_h2c_ofld_rssi {
3366 __le32 w0;
3367 __le32 w1;
3368 } __packed;
3369
3370 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3371 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3372 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3373
3374 struct rtw89_h2c_ofld {
3375 __le32 w0;
3376 } __packed;
3377
3378 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3379 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3380 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3381
3382 #define RTW89_MFW_SIG 0xFF
3383
3384 struct rtw89_mfw_info {
3385 u8 cv;
3386 u8 type; /* enum rtw89_fw_type */
3387 u8 mp;
3388 u8 rsvd;
3389 __le32 shift;
3390 __le32 size;
3391 u8 rsvd2[4];
3392 } __packed;
3393
3394 struct rtw89_mfw_hdr {
3395 u8 sig; /* RTW89_MFW_SIG */
3396 u8 fw_nr;
3397 u8 rsvd0[2];
3398 struct {
3399 u8 major;
3400 u8 minor;
3401 u8 sub;
3402 u8 idx;
3403 } ver;
3404 u8 rsvd1[8];
3405 struct rtw89_mfw_info info[];
3406 } __packed;
3407
3408 struct rtw89_fw_logsuit_hdr {
3409 __le32 rsvd;
3410 __le32 count;
3411 __le32 ids[];
3412 } __packed;
3413
3414 #define RTW89_FW_ELEMENT_ALIGN 16
3415
3416 enum rtw89_fw_element_id {
3417 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3418 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3419 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3420 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3421 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3422 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3423 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3424 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3425 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3426 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3427 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3428 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3429 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3430 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3431 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3432 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3433 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3434 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3435 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3436 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3437
3438 RTW89_FW_ELEMENT_ID_NUM,
3439 };
3440
3441 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3442 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3443 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3444 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3445 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3446 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3447 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3448 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ) | \
3449 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3450 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3451
3452 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3453 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3454 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3455 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3456 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3457 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3458 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3459
3460 struct __rtw89_fw_txpwr_element {
3461 u8 rsvd0;
3462 u8 rsvd1;
3463 u8 rfe_type;
3464 u8 ent_sz;
3465 __le32 num_ents;
3466 u8 content[];
3467 } __packed;
3468
3469 enum rtw89_fw_txpwr_trk_type {
3470 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3471 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3472 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3473 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3474 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3475 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3476
3477 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3478 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3479 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3480 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3481 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3482 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3483
3484 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
3485 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
3486 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
3487 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
3488 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
3489 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3490 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
3491 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
3492 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
3493 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
3494
3495 RTW89_FW_TXPWR_TRK_TYPE_NR,
3496 };
3497
3498 struct rtw89_fw_txpwr_track_cfg {
3499 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
3500 };
3501
3502 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
3503 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3504 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3505 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3506 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3507 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
3508 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3509 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3510 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3511 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3512 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
3513 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3514 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3515 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3516 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3517 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3518 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3519 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3520 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3521
3522 struct rtw89_fw_element_hdr {
3523 __le32 id; /* enum rtw89_fw_element_id */
3524 __le32 size; /* exclude header size */
3525 u8 ver[4];
3526 __le32 rsvd0;
3527 __le32 rsvd1;
3528 __le32 rsvd2;
3529 union {
3530 struct {
3531 u8 priv[8];
3532 u8 contents[];
3533 } __packed common;
3534 struct {
3535 u8 idx;
3536 u8 rsvd[7];
3537 struct {
3538 __le32 addr;
3539 __le32 data;
3540 } __packed regs[];
3541 } __packed reg2;
3542 struct {
3543 u8 cv;
3544 u8 priv[7];
3545 u8 contents[];
3546 } __packed bbmcu;
3547 struct {
3548 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
3549 __le32 rsvd;
3550 s8 contents[][DELTA_SWINGIDX_SIZE];
3551 } __packed txpwr_trk;
3552 struct {
3553 u8 nr;
3554 u8 rsvd[3];
3555 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
3556 u8 rsvd1[3];
3557 __le16 offset[];
3558 } __packed rfk_log_fmt;
3559 struct __rtw89_fw_txpwr_element txpwr;
3560 } __packed u;
3561 } __packed;
3562
3563 struct fwcmd_hdr {
3564 __le32 hdr0;
3565 __le32 hdr1;
3566 };
3567
3568 union rtw89_compat_fw_hdr {
3569 struct rtw89_mfw_hdr mfw_hdr;
3570 struct rtw89_fw_hdr fw_hdr;
3571 };
3572
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)3573 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3574 {
3575 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3576
3577 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3578 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3579 else
3580 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3581 }
3582
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)3583 static inline void rtw89_fw_get_filename(char *buf, size_t size,
3584 const char *fw_basename, int fw_format)
3585 {
3586 if (fw_format <= 0)
3587 snprintf(buf, size, "%s.bin", fw_basename);
3588 else
3589 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3590 }
3591
3592 #define RTW89_H2C_RF_PAGE_SIZE 500
3593 #define RTW89_H2C_RF_PAGE_NUM 3
3594 struct rtw89_fw_h2c_rf_reg_info {
3595 enum rtw89_rf_path rf_path;
3596 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3597 u16 curr_idx;
3598 };
3599
3600 #define H2C_SEC_CAM_LEN 24
3601
3602 #define H2C_HEADER_LEN 8
3603 #define H2C_HDR_CAT GENMASK(1, 0)
3604 #define H2C_HDR_CLASS GENMASK(7, 2)
3605 #define H2C_HDR_FUNC GENMASK(15, 8)
3606 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
3607 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
3608 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
3609 #define H2C_HDR_REC_ACK BIT(14)
3610 #define H2C_HDR_DONE_ACK BIT(15)
3611
3612 #define FWCMD_TYPE_H2C 0
3613
3614 #define H2C_CAT_TEST 0x0
3615
3616 /* CLASS 5 - FW STATUS TEST */
3617 #define H2C_CL_FW_STATUS_TEST 0x5
3618 #define H2C_FUNC_CPU_EXCEPTION 0x1
3619
3620 #define H2C_CAT_MAC 0x1
3621
3622 /* CLASS 0 - FW INFO */
3623 #define H2C_CL_FW_INFO 0x0
3624 #define H2C_FUNC_LOG_CFG 0x0
3625 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
3626
3627 /* CLASS 1 - WOW */
3628 #define H2C_CL_MAC_WOW 0x1
3629 #define H2C_FUNC_KEEP_ALIVE 0x0
3630 #define H2C_FUNC_DISCONNECT_DETECT 0x1
3631 #define H2C_FUNC_WOW_GLOBAL 0x2
3632 #define H2C_FUNC_WAKEUP_CTRL 0x8
3633 #define H2C_FUNC_WOW_CAM_UPD 0xC
3634
3635 /* CLASS 2 - PS */
3636 #define H2C_CL_MAC_PS 0x2
3637 #define H2C_FUNC_MAC_LPS_PARM 0x0
3638 #define H2C_FUNC_P2P_ACT 0x1
3639
3640 /* CLASS 3 - FW download */
3641 #define H2C_CL_MAC_FWDL 0x3
3642 #define H2C_FUNC_MAC_FWHDR_DL 0x0
3643
3644 /* CLASS 5 - Frame Exchange */
3645 #define H2C_CL_MAC_FR_EXCHG 0x5
3646 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
3647 #define H2C_FUNC_MAC_BCN_UPD 0x5
3648 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
3649 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
3650
3651 /* CLASS 6 - Address CAM */
3652 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
3653 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
3654
3655 /* CLASS 8 - Media Status Report */
3656 #define H2C_CL_MAC_MEDIA_RPT 0x8
3657 #define H2C_FUNC_MAC_JOININFO 0x0
3658 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
3659 #define H2C_FUNC_NOTIFY_DBCC 0x5
3660
3661 /* CLASS 9 - FW offload */
3662 #define H2C_CL_MAC_FW_OFLD 0x9
3663 enum rtw89_fw_ofld_h2c_func {
3664 H2C_FUNC_PACKET_OFLD = 0x1,
3665 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
3666 H2C_FUNC_USR_EDCA = 0xF,
3667 H2C_FUNC_TSF32_TOGL = 0x10,
3668 H2C_FUNC_OFLD_CFG = 0x14,
3669 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
3670 H2C_FUNC_SCANOFLD = 0x17,
3671 H2C_FUNC_PKT_DROP = 0x1b,
3672 H2C_FUNC_CFG_BCNFLTR = 0x1e,
3673 H2C_FUNC_OFLD_RSSI = 0x1f,
3674 H2C_FUNC_OFLD_TP = 0x20,
3675
3676 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
3677 };
3678
3679 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
3680 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
3681
3682 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
3683 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
3684 H2C_FUNC_PACKET_OFLD)
3685
3686 /* CLASS 10 - Security CAM */
3687 #define H2C_CL_MAC_SEC_CAM 0xa
3688 #define H2C_FUNC_MAC_SEC_UPD 0x1
3689
3690 /* CLASS 12 - BA CAM */
3691 #define H2C_CL_BA_CAM 0xc
3692 #define H2C_FUNC_MAC_BA_CAM 0x0
3693
3694 /* CLASS 14 - MCC */
3695 #define H2C_CL_MCC 0xe
3696 enum rtw89_mcc_h2c_func {
3697 H2C_FUNC_ADD_MCC = 0x0,
3698 H2C_FUNC_START_MCC = 0x1,
3699 H2C_FUNC_STOP_MCC = 0x2,
3700 H2C_FUNC_DEL_MCC_GROUP = 0x3,
3701 H2C_FUNC_RESET_MCC_GROUP = 0x4,
3702 H2C_FUNC_MCC_REQ_TSF = 0x5,
3703 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
3704 H2C_FUNC_MCC_SYNC = 0x7,
3705 H2C_FUNC_MCC_SET_DURATION = 0x8,
3706
3707 NUM_OF_RTW89_MCC_H2C_FUNC,
3708 };
3709
3710 #define RTW89_MCC_WAIT_COND(group, func) \
3711 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
3712
3713 #define H2C_CAT_OUTSRC 0x2
3714
3715 #define H2C_CL_OUTSRC_RA 0x1
3716 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
3717
3718 #define H2C_CL_OUTSRC_RF_REG_A 0x8
3719 #define H2C_CL_OUTSRC_RF_REG_B 0x9
3720 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
3721 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
3722
3723 struct rtw89_fw_h2c_rf_get_mccch {
3724 __le32 ch_0;
3725 __le32 ch_1;
3726 __le32 band_0;
3727 __le32 band_1;
3728 __le32 current_channel;
3729 __le32 current_band_type;
3730 } __packed;
3731
3732 enum rtw89_rf_log_type {
3733 RTW89_RF_RUN_LOG = 0,
3734 RTW89_RF_RPT_LOG = 1,
3735 };
3736
3737 struct rtw89_c2h_rf_log_hdr {
3738 u8 type; /* enum rtw89_rf_log_type */
3739 __le16 len;
3740 u8 content[];
3741 } __packed;
3742
3743 struct rtw89_c2h_rf_run_log {
3744 __le32 fmt_idx;
3745 __le32 arg[4];
3746 } __packed;
3747
3748 struct rtw89_c2h_rf_dpk_rpt_log {
3749 u8 ver;
3750 u8 idx[2];
3751 u8 band[2];
3752 u8 bw[2];
3753 u8 ch[2];
3754 u8 path_ok[2];
3755 u8 txagc[2];
3756 u8 ther[2];
3757 u8 gs[2];
3758 u8 dc_i[4];
3759 u8 dc_q[4];
3760 u8 corr_val[2];
3761 u8 corr_idx[2];
3762 u8 is_timeout[2];
3763 u8 rxbb_ov[2];
3764 u8 rsvd;
3765 } __packed;
3766
3767 struct rtw89_c2h_rf_dack_rpt_log {
3768 u8 fwdack_ver;
3769 u8 fwdack_rpt_ver;
3770 u8 msbk_d[2][2][16];
3771 u8 dadck_d[2][2];
3772 u8 cdack_d[2][2][2];
3773 __le16 addck2_d[2][2][2];
3774 u8 adgaink_d[2][2];
3775 __le16 biask_d[2][2];
3776 u8 addck_timeout;
3777 u8 cdack_timeout;
3778 u8 dadck_timeout;
3779 u8 msbk_timeout;
3780 u8 adgaink_timeout;
3781 u8 dack_fail;
3782 } __packed;
3783
3784 struct rtw89_c2h_rf_rxdck_rpt_log {
3785 u8 ver;
3786 u8 band[2];
3787 u8 bw[2];
3788 u8 ch[2];
3789 u8 timeout[2];
3790 } __packed;
3791
3792 struct rtw89_c2h_rf_txgapk_rpt_log {
3793 __le32 r0x8010[2];
3794 __le32 chk_cnt;
3795 u8 track_d[2][17];
3796 u8 power_d[2][17];
3797 u8 is_txgapk_ok;
3798 u8 chk_id;
3799 u8 ver;
3800 u8 rsv1;
3801 } __packed;
3802
3803 #define RTW89_FW_RSVD_PLE_SIZE 0x800
3804
3805 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
3806 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
3807 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
3808
3809 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
3810 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
3811
3812 #define FWDL_WAIT_CNT 400000
3813
3814 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
3815 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
3816 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
3817 const struct firmware *
3818 rtw89_early_fw_feature_recognize(struct device *device,
3819 const struct rtw89_chip_info *chip,
3820 struct rtw89_fw_info *early_fw,
3821 int *used_fw_format);
3822 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
3823 bool include_bb);
3824 void rtw89_load_firmware_work(struct work_struct *work);
3825 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
3826 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
3827 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
3828 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
3829 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3830 u8 type, u8 cat, u8 class, u8 func,
3831 bool rack, bool dack, u32 len);
3832 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
3833 struct rtw89_vif *rtwvif);
3834 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
3835 struct ieee80211_vif *vif,
3836 struct ieee80211_sta *sta);
3837 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
3838 struct rtw89_sta *rtwsta);
3839 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
3840 struct rtw89_sta *rtwsta);
3841 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
3842 struct rtw89_vif *rtwvif);
3843 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
3844 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
3845 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
3846 struct rtw89_vif *rtwvif,
3847 struct rtw89_sta *rtwsta);
3848 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
3849 void rtw89_fw_c2h_work(struct work_struct *work);
3850 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
3851 struct rtw89_vif *rtwvif,
3852 struct rtw89_sta *rtwsta,
3853 enum rtw89_upd_mode upd_mode);
3854 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3855 struct rtw89_sta *rtwsta, bool dis_conn);
3856 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
3857 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
3858 bool pause);
3859 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3860 u8 ac, u32 val);
3861 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
3862 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
3863 struct ieee80211_vif *vif,
3864 bool connect);
3865 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
3866 struct rtw89_rx_phy_ppdu *phy_ppdu);
3867 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
3868 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
3869 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev);
3870 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev);
3871 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev);
3872 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev);
3873 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev);
3874 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev);
3875 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev);
3876 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
3877 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
3878 struct sk_buff *skb_ofld);
3879 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
3880 struct list_head *chan_list);
3881 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
3882 struct rtw89_scan_option *opt,
3883 struct rtw89_vif *vif);
3884 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
3885 struct rtw89_fw_h2c_rf_reg_info *info,
3886 u16 len, u8 page);
3887 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
3888 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
3889 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
3890 bool rack, bool dack);
3891 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
3892 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
3893 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
3894 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3895 u8 macid);
3896 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
3897 struct rtw89_vif *rtwvif, bool notify_fw);
3898 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
3899 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3900 bool valid, struct ieee80211_ampdu_params *params);
3901 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
3902
3903 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
3904 struct rtw89_lps_parm *lps_param);
3905 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
3906 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
3907 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
3908 struct rtw89_mac_h2c_info *h2c_info,
3909 struct rtw89_mac_c2h_info *c2h_info);
3910 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
3911 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
3912 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3913 struct ieee80211_scan_request *req);
3914 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3915 bool aborted);
3916 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3917 bool enable);
3918 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
3919 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
3920 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
3921 const struct rtw89_pkt_drop_params *params);
3922 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3923 struct ieee80211_p2p_noa_desc *desc,
3924 u8 act, u8 noa_id);
3925 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3926 bool en);
3927 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3928 bool enable);
3929 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3930 struct rtw89_vif *rtwvif, bool enable);
3931 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3932 bool enable);
3933 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
3934 struct rtw89_vif *rtwvif, bool enable);
3935 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3936 bool enable);
3937 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3938 struct rtw89_vif *rtwvif, bool enable);
3939 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
3940 struct rtw89_wow_cam_info *cam_info);
3941 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
3942 const struct rtw89_fw_mcc_add_req *p);
3943 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
3944 const struct rtw89_fw_mcc_start_req *p);
3945 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3946 bool prev_groups);
3947 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
3948 bool prev_groups);
3949 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
3950 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
3951 const struct rtw89_fw_mcc_tsf_req *req,
3952 struct rtw89_mac_mcc_tsf_rpt *rpt);
3953 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3954 u8 *bitmap);
3955 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
3956 u8 target, u8 offset);
3957 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
3958 const struct rtw89_fw_mcc_duration *p);
3959
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)3960 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
3961 {
3962 const struct rtw89_chip_info *chip = rtwdev->chip;
3963
3964 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
3965 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
3966 }
3967
3968 /* must consider compatibility; don't insert new in the mid */
3969 struct rtw89_fw_txpwr_byrate_entry {
3970 u8 band;
3971 u8 nss;
3972 u8 rs;
3973 u8 shf;
3974 u8 len;
3975 __le32 data;
3976 u8 bw;
3977 u8 ofdma;
3978 } __packed;
3979
3980 /* must consider compatibility; don't insert new in the mid */
3981 struct rtw89_fw_txpwr_lmt_2ghz_entry {
3982 u8 bw;
3983 u8 nt;
3984 u8 rs;
3985 u8 bf;
3986 u8 regd;
3987 u8 ch_idx;
3988 s8 v;
3989 } __packed;
3990
3991 /* must consider compatibility; don't insert new in the mid */
3992 struct rtw89_fw_txpwr_lmt_5ghz_entry {
3993 u8 bw;
3994 u8 nt;
3995 u8 rs;
3996 u8 bf;
3997 u8 regd;
3998 u8 ch_idx;
3999 s8 v;
4000 } __packed;
4001
4002 /* must consider compatibility; don't insert new in the mid */
4003 struct rtw89_fw_txpwr_lmt_6ghz_entry {
4004 u8 bw;
4005 u8 nt;
4006 u8 rs;
4007 u8 bf;
4008 u8 regd;
4009 u8 reg_6ghz_power;
4010 u8 ch_idx;
4011 s8 v;
4012 } __packed;
4013
4014 /* must consider compatibility; don't insert new in the mid */
4015 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4016 u8 ru;
4017 u8 nt;
4018 u8 regd;
4019 u8 ch_idx;
4020 s8 v;
4021 } __packed;
4022
4023 /* must consider compatibility; don't insert new in the mid */
4024 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4025 u8 ru;
4026 u8 nt;
4027 u8 regd;
4028 u8 ch_idx;
4029 s8 v;
4030 } __packed;
4031
4032 /* must consider compatibility; don't insert new in the mid */
4033 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4034 u8 ru;
4035 u8 nt;
4036 u8 regd;
4037 u8 reg_6ghz_power;
4038 u8 ch_idx;
4039 s8 v;
4040 } __packed;
4041
4042 /* must consider compatibility; don't insert new in the mid */
4043 struct rtw89_fw_tx_shape_lmt_entry {
4044 u8 band;
4045 u8 tx_shape_rs;
4046 u8 regd;
4047 u8 v;
4048 } __packed;
4049
4050 /* must consider compatibility; don't insert new in the mid */
4051 struct rtw89_fw_tx_shape_lmt_ru_entry {
4052 u8 band;
4053 u8 regd;
4054 u8 v;
4055 } __packed;
4056
4057 const struct rtw89_rfe_parms *
4058 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
4059 const struct rtw89_rfe_parms *init);
4060
4061 #endif
4062