1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * vsp1_drm.c -- R-Car VSP1 DRM/KMS Interface
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/export.h>
13 #include <linux/slab.h>
14
15 #include <media/media-entity.h>
16 #include <media/v4l2-subdev.h>
17 #include <media/vsp1.h>
18
19 #include "vsp1.h"
20 #include "vsp1_brx.h"
21 #include "vsp1_dl.h"
22 #include "vsp1_drm.h"
23 #include "vsp1_lif.h"
24 #include "vsp1_pipe.h"
25 #include "vsp1_rwpf.h"
26 #include "vsp1_uif.h"
27
28 #define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
29
30 /* -----------------------------------------------------------------------------
31 * Interrupt Handling
32 */
33
vsp1_du_pipeline_frame_end(struct vsp1_pipeline * pipe,unsigned int completion)34 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
35 unsigned int completion)
36 {
37 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
38
39 if (drm_pipe->du_complete) {
40 struct vsp1_entity *uif = drm_pipe->uif;
41 unsigned int status = completion
42 & (VSP1_DU_STATUS_COMPLETE |
43 VSP1_DU_STATUS_WRITEBACK);
44 u32 crc;
45
46 crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0;
47 drm_pipe->du_complete(drm_pipe->du_private, status, crc);
48 }
49
50 if (completion & VSP1_DL_FRAME_END_INTERNAL) {
51 drm_pipe->force_brx_release = false;
52 wake_up(&drm_pipe->wait_queue);
53 }
54 }
55
56 /* -----------------------------------------------------------------------------
57 * Pipeline Configuration
58 */
59
60 /*
61 * Insert the UIF in the pipeline between the prev and next entities. If no UIF
62 * is available connect the two entities directly.
63 */
vsp1_du_insert_uif(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe,struct vsp1_entity * uif,struct vsp1_entity * prev,unsigned int prev_pad,struct vsp1_entity * next,unsigned int next_pad)64 static int vsp1_du_insert_uif(struct vsp1_device *vsp1,
65 struct vsp1_pipeline *pipe,
66 struct vsp1_entity *uif,
67 struct vsp1_entity *prev, unsigned int prev_pad,
68 struct vsp1_entity *next, unsigned int next_pad)
69 {
70 struct v4l2_subdev_format format = {
71 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
72 };
73 int ret;
74
75 if (!uif) {
76 /*
77 * If there's no UIF to be inserted, connect the previous and
78 * next entities directly.
79 */
80 prev->sink = next;
81 prev->sink_pad = next_pad;
82 return 0;
83 }
84
85 prev->sink = uif;
86 prev->sink_pad = UIF_PAD_SINK;
87
88 format.pad = prev_pad;
89
90 ret = v4l2_subdev_call(&prev->subdev, pad, get_fmt, NULL, &format);
91 if (ret < 0)
92 return ret;
93
94 format.pad = UIF_PAD_SINK;
95
96 ret = v4l2_subdev_call(&uif->subdev, pad, set_fmt, NULL, &format);
97 if (ret < 0)
98 return ret;
99
100 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on UIF sink\n",
101 __func__, format.format.width, format.format.height,
102 format.format.code);
103
104 /*
105 * The UIF doesn't mangle the format between its sink and source pads,
106 * so there is no need to retrieve the format on its source pad.
107 */
108
109 uif->sink = next;
110 uif->sink_pad = next_pad;
111
112 return 0;
113 }
114
115 /* Setup one RPF and the connected BRx sink pad. */
vsp1_du_pipeline_setup_rpf(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe,struct vsp1_rwpf * rpf,struct vsp1_entity * uif,unsigned int brx_input)116 static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
117 struct vsp1_pipeline *pipe,
118 struct vsp1_rwpf *rpf,
119 struct vsp1_entity *uif,
120 unsigned int brx_input)
121 {
122 const struct vsp1_drm_input *input = &vsp1->drm->inputs[rpf->entity.index];
123 struct v4l2_subdev_selection sel = {
124 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
125 };
126 struct v4l2_subdev_format format = {
127 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
128 };
129 int ret;
130
131 /*
132 * Configure the format on the RPF sink pad and propagate it up to the
133 * BRx sink pad.
134 */
135 format.pad = RWPF_PAD_SINK;
136 format.format.width = input->crop.width + input->crop.left;
137 format.format.height = input->crop.height + input->crop.top;
138 format.format.code = rpf->fmtinfo->mbus;
139 format.format.field = V4L2_FIELD_NONE;
140 format.format.ycbcr_enc = input->ycbcr_enc;
141 format.format.quantization = input->quantization;
142
143 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
144 &format);
145 if (ret < 0)
146 return ret;
147
148 dev_dbg(vsp1->dev,
149 "%s: set format %ux%u (%x) on RPF%u sink\n",
150 __func__, format.format.width, format.format.height,
151 format.format.code, rpf->entity.index);
152
153 sel.pad = RWPF_PAD_SINK;
154 sel.target = V4L2_SEL_TGT_CROP;
155 sel.r = input->crop;
156
157 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
158 &sel);
159 if (ret < 0)
160 return ret;
161
162 dev_dbg(vsp1->dev,
163 "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
164 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
165 rpf->entity.index);
166
167 /*
168 * RPF source, hardcode the format to ARGB8888 to turn on format
169 * conversion if needed.
170 */
171 format.pad = RWPF_PAD_SOURCE;
172
173 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
174 &format);
175 if (ret < 0)
176 return ret;
177
178 dev_dbg(vsp1->dev,
179 "%s: got format %ux%u (%x) on RPF%u source\n",
180 __func__, format.format.width, format.format.height,
181 format.format.code, rpf->entity.index);
182
183 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
184
185 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
186 &format);
187 if (ret < 0)
188 return ret;
189
190 /* Insert and configure the UIF if available. */
191 ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,
192 pipe->brx, brx_input);
193 if (ret < 0)
194 return ret;
195
196 /* BRx sink, propagate the format from the RPF source. */
197 format.pad = brx_input;
198
199 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
200 &format);
201 if (ret < 0)
202 return ret;
203
204 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
205 __func__, format.format.width, format.format.height,
206 format.format.code, BRX_NAME(pipe->brx), format.pad);
207
208 sel.pad = brx_input;
209 sel.target = V4L2_SEL_TGT_COMPOSE;
210 sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
211
212 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
213 &sel);
214 if (ret < 0)
215 return ret;
216
217 dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
218 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
219 BRX_NAME(pipe->brx), sel.pad);
220
221 return 0;
222 }
223
224 /* Setup the BRx source pad. */
225 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
226 struct vsp1_pipeline *pipe);
227 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
228
vsp1_du_pipeline_setup_brx(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)229 static int vsp1_du_pipeline_setup_brx(struct vsp1_device *vsp1,
230 struct vsp1_pipeline *pipe)
231 {
232 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
233 struct v4l2_subdev_format format = {
234 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
235 };
236 struct vsp1_entity *brx;
237 int ret;
238
239 /*
240 * Pick a BRx:
241 * - If we need more than two inputs, use the BRU.
242 * - Otherwise, if we are not forced to release our BRx, keep it.
243 * - Else, use any free BRx (randomly starting with the BRU).
244 */
245 if (pipe->num_inputs > 2)
246 brx = &vsp1->bru->entity;
247 else if (pipe->brx && !drm_pipe->force_brx_release)
248 brx = pipe->brx;
249 else if (vsp1_feature(vsp1, VSP1_HAS_BRU) && !vsp1->bru->entity.pipe)
250 brx = &vsp1->bru->entity;
251 else
252 brx = &vsp1->brs->entity;
253
254 /* Switch BRx if needed. */
255 if (brx != pipe->brx) {
256 struct vsp1_entity *released_brx = NULL;
257
258 /* Release our BRx if we have one. */
259 if (pipe->brx) {
260 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
261 __func__, pipe->lif->index,
262 BRX_NAME(pipe->brx));
263
264 /*
265 * The BRx might be acquired by the other pipeline in
266 * the next step. We must thus remove it from the list
267 * of entities for this pipeline. The other pipeline's
268 * hardware configuration will reconfigure the BRx
269 * routing.
270 *
271 * However, if the other pipeline doesn't acquire our
272 * BRx, we need to keep it in the list, otherwise the
273 * hardware configuration step won't disconnect it from
274 * the pipeline. To solve this, store the released BRx
275 * pointer to add it back to the list of entities later
276 * if it isn't acquired by the other pipeline.
277 */
278 released_brx = pipe->brx;
279
280 list_del(&pipe->brx->list_pipe);
281 pipe->brx->sink = NULL;
282 pipe->brx->pipe = NULL;
283 pipe->brx = NULL;
284 }
285
286 /*
287 * If the BRx we need is in use, force the owner pipeline to
288 * switch to the other BRx and wait until the switch completes.
289 */
290 if (brx->pipe) {
291 struct vsp1_drm_pipeline *owner_pipe;
292
293 dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
294 __func__, pipe->lif->index, BRX_NAME(brx));
295
296 owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
297 owner_pipe->force_brx_release = true;
298
299 vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
300 vsp1_du_pipeline_configure(&owner_pipe->pipe);
301
302 ret = wait_event_timeout(owner_pipe->wait_queue,
303 !owner_pipe->force_brx_release,
304 msecs_to_jiffies(500));
305 if (ret == 0)
306 dev_warn(vsp1->dev,
307 "DRM pipeline %u reconfiguration timeout\n",
308 owner_pipe->pipe.lif->index);
309 }
310
311 /*
312 * If the BRx we have released previously hasn't been acquired
313 * by the other pipeline, add it back to the entities list (with
314 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
315 * disconnect it from the hardware pipeline.
316 */
317 if (released_brx && !released_brx->pipe)
318 list_add_tail(&released_brx->list_pipe,
319 &pipe->entities);
320
321 /*
322 * Add the BRx to the pipeline, inserting it just before the
323 * WPF.
324 */
325 dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
326 __func__, pipe->lif->index, BRX_NAME(brx));
327
328 pipe->brx = brx;
329 pipe->brx->pipe = pipe;
330 pipe->brx->sink = &pipe->output->entity;
331 pipe->brx->sink_pad = 0;
332
333 list_add_tail(&pipe->brx->list_pipe,
334 &pipe->output->entity.list_pipe);
335 }
336
337 /*
338 * Configure the format on the BRx source and verify that it matches the
339 * requested format. We don't set the media bus code as it is configured
340 * on the BRx sink pad 0 and propagated inside the entity, not on the
341 * source pad.
342 */
343 format.pad = brx->source_pad;
344 format.format.width = drm_pipe->width;
345 format.format.height = drm_pipe->height;
346 format.format.field = V4L2_FIELD_NONE;
347
348 ret = v4l2_subdev_call(&brx->subdev, pad, set_fmt, NULL,
349 &format);
350 if (ret < 0)
351 return ret;
352
353 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
354 __func__, format.format.width, format.format.height,
355 format.format.code, BRX_NAME(brx), brx->source_pad);
356
357 if (format.format.width != drm_pipe->width ||
358 format.format.height != drm_pipe->height) {
359 dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
360 return -EPIPE;
361 }
362
363 return 0;
364 }
365
rpf_zpos(struct vsp1_device * vsp1,struct vsp1_rwpf * rpf)366 static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
367 {
368 return vsp1->drm->inputs[rpf->entity.index].zpos;
369 }
370
371 /* Setup the input side of the pipeline (RPFs and BRx). */
vsp1_du_pipeline_setup_inputs(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)372 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
373 struct vsp1_pipeline *pipe)
374 {
375 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
376 struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
377 struct vsp1_entity *uif;
378 bool use_uif = false;
379 struct vsp1_brx *brx;
380 unsigned int i;
381 int ret;
382
383 /* Count the number of enabled inputs and sort them by Z-order. */
384 pipe->num_inputs = 0;
385
386 for (i = 0; i < vsp1->info->rpf_count; ++i) {
387 struct vsp1_rwpf *rpf = vsp1->rpf[i];
388 unsigned int j;
389
390 if (!pipe->inputs[i])
391 continue;
392
393 /* Insert the RPF in the sorted RPFs array. */
394 for (j = pipe->num_inputs++; j > 0; --j) {
395 if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
396 break;
397 inputs[j] = inputs[j-1];
398 }
399
400 inputs[j] = rpf;
401 }
402
403 /*
404 * Setup the BRx. This must be done before setting up the RPF input
405 * pipelines as the BRx sink compose rectangles depend on the BRx source
406 * format.
407 */
408 ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
409 if (ret < 0) {
410 dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,
411 BRX_NAME(pipe->brx));
412 return ret;
413 }
414
415 brx = to_brx(&pipe->brx->subdev);
416
417 /* Setup the RPF input pipeline for every enabled input. */
418 for (i = 0; i < pipe->brx->source_pad; ++i) {
419 struct vsp1_rwpf *rpf = inputs[i];
420
421 if (!rpf) {
422 brx->inputs[i].rpf = NULL;
423 continue;
424 }
425
426 if (!rpf->entity.pipe) {
427 rpf->entity.pipe = pipe;
428 list_add(&rpf->entity.list_pipe, &pipe->entities);
429 }
430
431 brx->inputs[i].rpf = rpf;
432 rpf->brx_input = i;
433 rpf->entity.sink = pipe->brx;
434 rpf->entity.sink_pad = i;
435
436 dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
437 __func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
438
439 uif = drm_pipe->crc.source == VSP1_DU_CRC_PLANE &&
440 drm_pipe->crc.index == i ? drm_pipe->uif : NULL;
441 if (uif)
442 use_uif = true;
443 ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);
444 if (ret < 0) {
445 dev_err(vsp1->dev,
446 "%s: failed to setup RPF.%u\n",
447 __func__, rpf->entity.index);
448 return ret;
449 }
450 }
451
452 /* Insert and configure the UIF at the BRx output if available. */
453 uif = drm_pipe->crc.source == VSP1_DU_CRC_OUTPUT ? drm_pipe->uif : NULL;
454 if (uif)
455 use_uif = true;
456 ret = vsp1_du_insert_uif(vsp1, pipe, uif,
457 pipe->brx, pipe->brx->source_pad,
458 &pipe->output->entity, 0);
459 if (ret < 0)
460 dev_err(vsp1->dev, "%s: failed to setup UIF after %s\n",
461 __func__, BRX_NAME(pipe->brx));
462
463 /* If the DRM pipe does not have a UIF there is nothing we can update. */
464 if (!drm_pipe->uif)
465 return 0;
466
467 /*
468 * If the UIF is not in use schedule it for removal by setting its pipe
469 * pointer to NULL, vsp1_du_pipeline_configure() will remove it from the
470 * hardware pipeline and from the pipeline's list of entities. Otherwise
471 * make sure it is present in the pipeline's list of entities if it
472 * wasn't already.
473 */
474 if (!use_uif) {
475 drm_pipe->uif->pipe = NULL;
476 } else if (!drm_pipe->uif->pipe) {
477 drm_pipe->uif->pipe = pipe;
478 list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);
479 }
480
481 return 0;
482 }
483
484 /* Setup the output side of the pipeline (WPF and LIF). */
vsp1_du_pipeline_setup_output(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)485 static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
486 struct vsp1_pipeline *pipe)
487 {
488 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
489 struct v4l2_subdev_format format = {
490 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
491 };
492 int ret;
493
494 format.pad = RWPF_PAD_SINK;
495 format.format.width = drm_pipe->width;
496 format.format.height = drm_pipe->height;
497 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
498 format.format.field = V4L2_FIELD_NONE;
499
500 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
501 &format);
502 if (ret < 0)
503 return ret;
504
505 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
506 __func__, format.format.width, format.format.height,
507 format.format.code, pipe->output->entity.index);
508
509 format.pad = RWPF_PAD_SOURCE;
510 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
511 &format);
512 if (ret < 0)
513 return ret;
514
515 dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
516 __func__, format.format.width, format.format.height,
517 format.format.code, pipe->output->entity.index);
518
519 format.pad = LIF_PAD_SINK;
520 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
521 &format);
522 if (ret < 0)
523 return ret;
524
525 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
526 __func__, format.format.width, format.format.height,
527 format.format.code, pipe->lif->index);
528
529 /*
530 * Verify that the format at the output of the pipeline matches the
531 * requested frame size and media bus code.
532 */
533 if (format.format.width != drm_pipe->width ||
534 format.format.height != drm_pipe->height ||
535 format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
536 dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,
537 pipe->lif->index);
538 return -EPIPE;
539 }
540
541 return 0;
542 }
543
544 /* Configure all entities in the pipeline. */
vsp1_du_pipeline_configure(struct vsp1_pipeline * pipe)545 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
546 {
547 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
548 struct vsp1_entity *entity;
549 struct vsp1_entity *next;
550 struct vsp1_dl_list *dl;
551 struct vsp1_dl_body *dlb;
552 unsigned int dl_flags = 0;
553
554 vsp1_pipeline_calculate_partition(pipe, &pipe->part_table[0],
555 drm_pipe->width, 0);
556
557 if (drm_pipe->force_brx_release)
558 dl_flags |= VSP1_DL_FRAME_END_INTERNAL;
559 if (pipe->output->writeback)
560 dl_flags |= VSP1_DL_FRAME_END_WRITEBACK;
561
562 dl = vsp1_dl_list_get(pipe->output->dlm);
563 dlb = vsp1_dl_list_get_body0(dl);
564
565 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
566 /* Disconnect unused entities from the pipeline. */
567 if (!entity->pipe) {
568 vsp1_dl_body_write(dlb, entity->route->reg,
569 VI6_DPR_NODE_UNUSED);
570
571 entity->sink = NULL;
572 list_del(&entity->list_pipe);
573
574 continue;
575 }
576
577 vsp1_entity_route_setup(entity, pipe, dlb);
578 vsp1_entity_configure_stream(entity, entity->state, pipe,
579 dl, dlb);
580 vsp1_entity_configure_frame(entity, pipe, dl, dlb);
581 vsp1_entity_configure_partition(entity, pipe,
582 &pipe->part_table[0], dl, dlb);
583 }
584
585 vsp1_dl_list_commit(dl, dl_flags);
586 }
587
vsp1_du_pipeline_set_rwpf_format(struct vsp1_device * vsp1,struct vsp1_rwpf * rwpf,u32 pixelformat,unsigned int pitch)588 static int vsp1_du_pipeline_set_rwpf_format(struct vsp1_device *vsp1,
589 struct vsp1_rwpf *rwpf,
590 u32 pixelformat, unsigned int pitch)
591 {
592 const struct vsp1_format_info *fmtinfo;
593 unsigned int chroma_hsub;
594
595 fmtinfo = vsp1_get_format_info(vsp1, pixelformat);
596 if (!fmtinfo) {
597 dev_dbg(vsp1->dev, "Unsupported pixel format %p4cc\n",
598 &pixelformat);
599 return -EINVAL;
600 }
601
602 /*
603 * Only formats with three planes can affect the chroma planes pitch.
604 * All formats with two planes have a horizontal subsampling value of 2,
605 * but combine U and V in a single chroma plane, which thus results in
606 * the luma plane and chroma plane having the same pitch.
607 */
608 chroma_hsub = (fmtinfo->planes == 3) ? fmtinfo->hsub : 1;
609
610 rwpf->fmtinfo = fmtinfo;
611 rwpf->format.num_planes = fmtinfo->planes;
612 rwpf->format.plane_fmt[0].bytesperline = pitch;
613 rwpf->format.plane_fmt[1].bytesperline = pitch / chroma_hsub;
614
615 return 0;
616 }
617
618 /* -----------------------------------------------------------------------------
619 * DU Driver API
620 */
621
vsp1_du_init(struct device * dev)622 int vsp1_du_init(struct device *dev)
623 {
624 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
625
626 if (!vsp1)
627 return -EPROBE_DEFER;
628
629 return 0;
630 }
631 EXPORT_SYMBOL_GPL(vsp1_du_init);
632
633 /**
634 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
635 * @dev: the VSP device
636 * @pipe_index: the DRM pipeline index
637 * @cfg: the LIF configuration
638 *
639 * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
640 * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and
641 * source pads, and the LIF sink pad.
642 *
643 * The @pipe_index argument selects which DRM pipeline to setup. The number of
644 * available pipelines depend on the VSP instance.
645 *
646 * As the media bus code on the blend unit source pad is conditioned by the
647 * configuration of its sink 0 pad, we also set up the formats on all blend unit
648 * sinks, even if the configuration will be overwritten later by
649 * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to
650 * a well defined state.
651 *
652 * Return 0 on success or a negative error code on failure.
653 */
vsp1_du_setup_lif(struct device * dev,unsigned int pipe_index,const struct vsp1_du_lif_config * cfg)654 int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
655 const struct vsp1_du_lif_config *cfg)
656 {
657 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
658 struct vsp1_drm_pipeline *drm_pipe;
659 struct vsp1_pipeline *pipe;
660 unsigned long flags;
661 unsigned int i;
662 int ret;
663
664 if (pipe_index >= vsp1->info->lif_count)
665 return -EINVAL;
666
667 drm_pipe = &vsp1->drm->pipe[pipe_index];
668 pipe = &drm_pipe->pipe;
669
670 if (!cfg) {
671 struct vsp1_brx *brx;
672
673 mutex_lock(&vsp1->drm->lock);
674
675 brx = to_brx(&pipe->brx->subdev);
676
677 /*
678 * NULL configuration means the CRTC is being disabled, stop
679 * the pipeline and turn the light off.
680 */
681 ret = vsp1_pipeline_stop(pipe);
682 if (ret == -ETIMEDOUT)
683 dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
684
685 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
686 struct vsp1_rwpf *rpf = pipe->inputs[i];
687
688 if (!rpf)
689 continue;
690
691 /*
692 * Remove the RPF from the pipe and the list of BRx
693 * inputs.
694 */
695 WARN_ON(!rpf->entity.pipe);
696 rpf->entity.pipe = NULL;
697 list_del(&rpf->entity.list_pipe);
698 pipe->inputs[i] = NULL;
699
700 brx->inputs[rpf->brx_input].rpf = NULL;
701 }
702
703 drm_pipe->du_complete = NULL;
704 pipe->num_inputs = 0;
705
706 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
707 __func__, pipe->lif->index,
708 BRX_NAME(pipe->brx));
709
710 list_del(&pipe->brx->list_pipe);
711 pipe->brx->pipe = NULL;
712 pipe->brx = NULL;
713
714 mutex_unlock(&vsp1->drm->lock);
715
716 vsp1_dlm_reset(pipe->output->dlm);
717 vsp1_device_put(vsp1);
718
719 dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
720
721 return 0;
722 }
723
724 /* Reset the underrun counter */
725 pipe->underrun_count = 0;
726
727 drm_pipe->width = cfg->width;
728 drm_pipe->height = cfg->height;
729 pipe->interlaced = cfg->interlaced;
730
731 dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u%s\n",
732 __func__, pipe_index, cfg->width, cfg->height,
733 pipe->interlaced ? "i" : "");
734
735 mutex_lock(&vsp1->drm->lock);
736
737 /* Setup formats through the pipeline. */
738 ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
739 if (ret < 0)
740 goto unlock;
741
742 ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
743 if (ret < 0)
744 goto unlock;
745
746 vsp1_pipeline_dump(pipe, "LIF setup");
747
748 /* Enable the VSP1. */
749 ret = vsp1_device_get(vsp1);
750 if (ret < 0)
751 goto unlock;
752
753 /*
754 * Register a callback to allow us to notify the DRM driver of frame
755 * completion events.
756 */
757 drm_pipe->du_complete = cfg->callback;
758 drm_pipe->du_private = cfg->callback_data;
759
760 /* Disable the display interrupts. */
761 vsp1_write(vsp1, VI6_DISP_IRQ_STA(pipe_index), 0);
762 vsp1_write(vsp1, VI6_DISP_IRQ_ENB(pipe_index), 0);
763
764 /* Configure all entities in the pipeline. */
765 vsp1_du_pipeline_configure(pipe);
766
767 unlock:
768 mutex_unlock(&vsp1->drm->lock);
769
770 if (ret < 0)
771 return ret;
772
773 /* Start the pipeline. */
774 spin_lock_irqsave(&pipe->irqlock, flags);
775 vsp1_pipeline_run(pipe);
776 spin_unlock_irqrestore(&pipe->irqlock, flags);
777
778 dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
779
780 return 0;
781 }
782 EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
783
784 /**
785 * vsp1_du_atomic_begin - Prepare for an atomic update
786 * @dev: the VSP device
787 * @pipe_index: the DRM pipeline index
788 */
vsp1_du_atomic_begin(struct device * dev,unsigned int pipe_index)789 void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
790 {
791 }
792 EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
793
794 /**
795 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
796 * @dev: the VSP device
797 * @pipe_index: the DRM pipeline index
798 * @rpf_index: index of the RPF to setup (0-based)
799 * @cfg: the RPF configuration
800 *
801 * Configure the VSP to perform image composition through RPF @rpf_index as
802 * described by the @cfg configuration. The image to compose is referenced by
803 * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst
804 * composition rectangle. The Z-order is configurable with higher @zpos values
805 * displayed on top.
806 *
807 * If the @cfg configuration is NULL, the RPF will be disabled. Calling the
808 * function on a disabled RPF is allowed.
809 *
810 * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat
811 * value. The memory pitch is configurable to allow for padding at end of lines,
812 * or simply for images that extend beyond the crop rectangle boundaries. The
813 * @cfg.pitch value is expressed in bytes and applies to all planes for
814 * multiplanar formats.
815 *
816 * The source memory buffer is referenced by the DMA address of its planes in
817 * the @cfg.mem array. Up to two planes are supported. The second plane DMA
818 * address is ignored for formats using a single plane.
819 *
820 * This function isn't reentrant, the caller needs to serialize calls.
821 *
822 * Return 0 on success or a negative error code on failure.
823 */
vsp1_du_atomic_update(struct device * dev,unsigned int pipe_index,unsigned int rpf_index,const struct vsp1_du_atomic_config * cfg)824 int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
825 unsigned int rpf_index,
826 const struct vsp1_du_atomic_config *cfg)
827 {
828 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
829 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
830 struct vsp1_drm_input *input;
831 struct vsp1_rwpf *rpf;
832 int ret;
833
834 if (rpf_index >= vsp1->info->rpf_count)
835 return -EINVAL;
836
837 input = &vsp1->drm->inputs[rpf_index];
838 rpf = vsp1->rpf[rpf_index];
839
840 if (!cfg) {
841 dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
842 rpf_index);
843
844 /*
845 * Remove the RPF from the pipeline's inputs. Keep it in the
846 * pipeline's entity list to let vsp1_du_pipeline_configure()
847 * remove it from the hardware pipeline.
848 */
849 rpf->entity.pipe = NULL;
850 drm_pipe->pipe.inputs[rpf_index] = NULL;
851 return 0;
852 }
853
854 dev_dbg(vsp1->dev,
855 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%p4cc), pitch %u dma { %pad, %pad, %pad } zpos %u\n",
856 __func__, rpf_index,
857 cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height,
858 cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height,
859 &cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1],
860 &cfg->mem[2], cfg->zpos);
861
862 /*
863 * Store the format, stride, memory buffer address, crop and compose
864 * rectangles and Z-order position and for the input.
865 */
866 ret = vsp1_du_pipeline_set_rwpf_format(vsp1, rpf, cfg->pixelformat,
867 cfg->pitch);
868 if (ret < 0)
869 return ret;
870
871 rpf->alpha = cfg->alpha;
872
873 rpf->mem.addr[0] = cfg->mem[0];
874 rpf->mem.addr[1] = cfg->mem[1];
875 rpf->mem.addr[2] = cfg->mem[2];
876
877 rpf->format.flags = cfg->premult ? V4L2_PIX_FMT_FLAG_PREMUL_ALPHA : 0;
878
879 input->crop = cfg->src;
880 input->compose = cfg->dst;
881 input->zpos = cfg->zpos;
882 input->ycbcr_enc = cfg->color_encoding;
883 input->quantization = cfg->color_range;
884
885 drm_pipe->pipe.inputs[rpf_index] = rpf;
886
887 return 0;
888 }
889 EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
890
891 /**
892 * vsp1_du_atomic_flush - Commit an atomic update
893 * @dev: the VSP device
894 * @pipe_index: the DRM pipeline index
895 * @cfg: atomic pipe configuration
896 */
vsp1_du_atomic_flush(struct device * dev,unsigned int pipe_index,const struct vsp1_du_atomic_pipe_config * cfg)897 void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
898 const struct vsp1_du_atomic_pipe_config *cfg)
899 {
900 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
901 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
902 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
903 int ret;
904
905 drm_pipe->crc = cfg->crc;
906
907 mutex_lock(&vsp1->drm->lock);
908
909 if (cfg->writeback.pixelformat) {
910 const struct vsp1_du_writeback_config *wb_cfg = &cfg->writeback;
911
912 ret = vsp1_du_pipeline_set_rwpf_format(vsp1, pipe->output,
913 wb_cfg->pixelformat,
914 wb_cfg->pitch);
915 if (WARN_ON(ret < 0))
916 goto done;
917
918 pipe->output->mem.addr[0] = wb_cfg->mem[0];
919 pipe->output->mem.addr[1] = wb_cfg->mem[1];
920 pipe->output->mem.addr[2] = wb_cfg->mem[2];
921 pipe->output->writeback = true;
922 }
923
924 vsp1_du_pipeline_setup_inputs(vsp1, pipe);
925
926 vsp1_pipeline_dump(pipe, "atomic update");
927
928 vsp1_du_pipeline_configure(pipe);
929
930 done:
931 mutex_unlock(&vsp1->drm->lock);
932 }
933 EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
934
vsp1_du_map_sg(struct device * dev,struct sg_table * sgt)935 int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt)
936 {
937 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
938
939 /*
940 * As all the buffers allocated by the DU driver are coherent, we can
941 * skip cache sync. This will need to be revisited when support for
942 * non-coherent buffers will be added to the DU driver.
943 */
944 return dma_map_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE,
945 DMA_ATTR_SKIP_CPU_SYNC);
946 }
947 EXPORT_SYMBOL_GPL(vsp1_du_map_sg);
948
vsp1_du_unmap_sg(struct device * dev,struct sg_table * sgt)949 void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt)
950 {
951 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
952
953 dma_unmap_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE,
954 DMA_ATTR_SKIP_CPU_SYNC);
955 }
956 EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);
957
958 /* -----------------------------------------------------------------------------
959 * Initialization
960 */
961
vsp1_drm_init(struct vsp1_device * vsp1)962 int vsp1_drm_init(struct vsp1_device *vsp1)
963 {
964 unsigned int i;
965
966 vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
967 if (!vsp1->drm)
968 return -ENOMEM;
969
970 mutex_init(&vsp1->drm->lock);
971
972 /* Create one DRM pipeline per LIF. */
973 for (i = 0; i < vsp1->info->lif_count; ++i) {
974 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
975 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
976
977 init_waitqueue_head(&drm_pipe->wait_queue);
978
979 vsp1_pipeline_init(pipe);
980
981 pipe->partitions = 1;
982 pipe->part_table = &drm_pipe->partition;
983
984 pipe->frame_end = vsp1_du_pipeline_frame_end;
985
986 /*
987 * The output side of the DRM pipeline is static, add the
988 * corresponding entities manually.
989 */
990 pipe->output = vsp1->wpf[i];
991 pipe->lif = &vsp1->lif[i]->entity;
992
993 pipe->output->entity.pipe = pipe;
994 pipe->output->entity.sink = pipe->lif;
995 pipe->output->entity.sink_pad = 0;
996 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
997
998 pipe->lif->pipe = pipe;
999 list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
1000
1001 /*
1002 * CRC computation is initially disabled, don't add the UIF to
1003 * the pipeline.
1004 */
1005 if (i < vsp1->info->uif_count)
1006 drm_pipe->uif = &vsp1->uif[i]->entity;
1007 }
1008
1009 /* Disable all RPFs initially. */
1010 for (i = 0; i < vsp1->info->rpf_count; ++i) {
1011 struct vsp1_rwpf *input = vsp1->rpf[i];
1012
1013 INIT_LIST_HEAD(&input->entity.list_pipe);
1014 }
1015
1016 return 0;
1017 }
1018
vsp1_drm_cleanup(struct vsp1_device * vsp1)1019 void vsp1_drm_cleanup(struct vsp1_device *vsp1)
1020 {
1021 mutex_destroy(&vsp1->drm->lock);
1022 }
1023