1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include <linux/debugfs.h>
7
8 #include <drm/drm_print.h>
9
10 #include "g4x_dp.h"
11 #include "i915_reg.h"
12 #include "i915_utils.h"
13 #include "intel_de.h"
14 #include "intel_display_power_well.h"
15 #include "intel_display_regs.h"
16 #include "intel_display_types.h"
17 #include "intel_dp.h"
18 #include "intel_dpio_phy.h"
19 #include "intel_dpll.h"
20 #include "intel_lvds.h"
21 #include "intel_lvds_regs.h"
22 #include "intel_pps.h"
23 #include "intel_pps_regs.h"
24 #include "intel_quirks.h"
25
26 static void vlv_steal_power_sequencer(struct intel_display *display,
27 enum pipe pipe);
28
29 static void pps_init_delays(struct intel_dp *intel_dp);
30 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
31
pps_name(struct intel_dp * intel_dp)32 static const char *pps_name(struct intel_dp *intel_dp)
33 {
34 struct intel_display *display = to_intel_display(intel_dp);
35 struct intel_pps *pps = &intel_dp->pps;
36
37 if (display->platform.valleyview || display->platform.cherryview) {
38 switch (pps->vlv_pps_pipe) {
39 case INVALID_PIPE:
40 /*
41 * FIXME would be nice if we can guarantee
42 * to always have a valid PPS when calling this.
43 */
44 return "PPS <none>";
45 case PIPE_A:
46 return "PPS A";
47 case PIPE_B:
48 return "PPS B";
49 default:
50 MISSING_CASE(pps->vlv_pps_pipe);
51 break;
52 }
53 } else {
54 switch (pps->pps_idx) {
55 case 0:
56 return "PPS 0";
57 case 1:
58 return "PPS 1";
59 default:
60 MISSING_CASE(pps->pps_idx);
61 break;
62 }
63 }
64
65 return "PPS <invalid>";
66 }
67
intel_pps_lock(struct intel_dp * intel_dp)68 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
69 {
70 struct intel_display *display = to_intel_display(intel_dp);
71 intel_wakeref_t wakeref;
72
73 /*
74 * See vlv_pps_reset_all() why we need a power domain reference here.
75 */
76 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
77 mutex_lock(&display->pps.mutex);
78
79 return wakeref;
80 }
81
intel_pps_unlock(struct intel_dp * intel_dp,intel_wakeref_t wakeref)82 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
83 intel_wakeref_t wakeref)
84 {
85 struct intel_display *display = to_intel_display(intel_dp);
86
87 mutex_unlock(&display->pps.mutex);
88 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
89
90 return NULL;
91 }
92
93 static void
vlv_power_sequencer_kick(struct intel_dp * intel_dp)94 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
95 {
96 struct intel_display *display = to_intel_display(intel_dp);
97 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
98 enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
99 bool pll_enabled, release_cl_override = false;
100 enum dpio_phy phy = vlv_pipe_to_phy(pipe);
101 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
102 u32 DP;
103
104 if (drm_WARN(display->drm,
105 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,
106 "skipping %s kick due to [ENCODER:%d:%s] being active\n",
107 pps_name(intel_dp),
108 dig_port->base.base.base.id, dig_port->base.base.name))
109 return;
110
111 drm_dbg_kms(display->drm,
112 "kicking %s for [ENCODER:%d:%s]\n",
113 pps_name(intel_dp),
114 dig_port->base.base.base.id, dig_port->base.base.name);
115
116 /* Preserve the BIOS-computed detected bit. This is
117 * supposed to be read-only.
118 */
119 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
120 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
121 DP |= DP_PORT_WIDTH(1);
122 DP |= DP_LINK_TRAIN_PAT_1;
123
124 if (display->platform.cherryview)
125 DP |= DP_PIPE_SEL_CHV(pipe);
126 else
127 DP |= DP_PIPE_SEL(pipe);
128
129 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
130
131 /*
132 * The DPLL for the pipe must be enabled for this to work.
133 * So enable temporarily it if it's not already enabled.
134 */
135 if (!pll_enabled) {
136 release_cl_override = display->platform.cherryview &&
137 !chv_phy_powergate_ch(display, phy, ch, true);
138
139 if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) {
140 drm_err(display->drm,
141 "Failed to force on PLL for pipe %c!\n",
142 pipe_name(pipe));
143 return;
144 }
145 }
146
147 /*
148 * Similar magic as in intel_dp_enable_port().
149 * We _must_ do this port enable + disable trick
150 * to make this power sequencer lock onto the port.
151 * Otherwise even VDD force bit won't work.
152 */
153 intel_de_write(display, intel_dp->output_reg, DP);
154 intel_de_posting_read(display, intel_dp->output_reg);
155
156 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);
157 intel_de_posting_read(display, intel_dp->output_reg);
158
159 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);
160 intel_de_posting_read(display, intel_dp->output_reg);
161
162 if (!pll_enabled) {
163 vlv_force_pll_off(display, pipe);
164
165 if (release_cl_override)
166 chv_phy_powergate_ch(display, phy, ch, false);
167 }
168 }
169
vlv_find_free_pps(struct intel_display * display)170 static enum pipe vlv_find_free_pps(struct intel_display *display)
171 {
172 struct intel_encoder *encoder;
173 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
174
175 /*
176 * We don't have power sequencer currently.
177 * Pick one that's not used by other ports.
178 */
179 for_each_intel_dp(display->drm, encoder) {
180 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
181
182 if (encoder->type == INTEL_OUTPUT_EDP) {
183 drm_WARN_ON(display->drm,
184 intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
185 intel_dp->pps.vlv_active_pipe !=
186 intel_dp->pps.vlv_pps_pipe);
187
188 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)
189 pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);
190 } else {
191 drm_WARN_ON(display->drm,
192 intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);
193
194 if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)
195 pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);
196 }
197 }
198
199 if (pipes == 0)
200 return INVALID_PIPE;
201
202 return ffs(pipes) - 1;
203 }
204
205 static enum pipe
vlv_power_sequencer_pipe(struct intel_dp * intel_dp)206 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
207 {
208 struct intel_display *display = to_intel_display(intel_dp);
209 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
210 enum pipe pipe;
211
212 lockdep_assert_held(&display->pps.mutex);
213
214 /* We should never land here with regular DP ports */
215 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
216
217 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
218 intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);
219
220 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)
221 return intel_dp->pps.vlv_pps_pipe;
222
223 pipe = vlv_find_free_pps(display);
224
225 /*
226 * Didn't find one. This should not happen since there
227 * are two power sequencers and up to two eDP ports.
228 */
229 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))
230 pipe = PIPE_A;
231
232 vlv_steal_power_sequencer(display, pipe);
233 intel_dp->pps.vlv_pps_pipe = pipe;
234
235 drm_dbg_kms(display->drm,
236 "picked %s for [ENCODER:%d:%s]\n",
237 pps_name(intel_dp),
238 dig_port->base.base.base.id, dig_port->base.base.name);
239
240 /* init power sequencer on this pipe and port */
241 pps_init_delays(intel_dp);
242 pps_init_registers(intel_dp, true);
243
244 /*
245 * Even vdd force doesn't work until we've made
246 * the power sequencer lock in on the port.
247 */
248 vlv_power_sequencer_kick(intel_dp);
249
250 return intel_dp->pps.vlv_pps_pipe;
251 }
252
253 static int
bxt_power_sequencer_idx(struct intel_dp * intel_dp)254 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
255 {
256 struct intel_display *display = to_intel_display(intel_dp);
257 int pps_idx = intel_dp->pps.pps_idx;
258
259 lockdep_assert_held(&display->pps.mutex);
260
261 /* We should never land here with regular DP ports */
262 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
263
264 if (!intel_dp->pps.bxt_pps_reset)
265 return pps_idx;
266
267 intel_dp->pps.bxt_pps_reset = false;
268
269 /*
270 * Only the HW needs to be reprogrammed, the SW state is fixed and
271 * has been setup during connector init.
272 */
273 pps_init_registers(intel_dp, false);
274
275 return pps_idx;
276 }
277
278 typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
279
pps_has_pp_on(struct intel_display * display,int pps_idx)280 static bool pps_has_pp_on(struct intel_display *display, int pps_idx)
281 {
282 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;
283 }
284
pps_has_vdd_on(struct intel_display * display,int pps_idx)285 static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)
286 {
287 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;
288 }
289
pps_any(struct intel_display * display,int pps_idx)290 static bool pps_any(struct intel_display *display, int pps_idx)
291 {
292 return true;
293 }
294
295 static enum pipe
vlv_initial_pps_pipe(struct intel_display * display,enum port port,pps_check check)296 vlv_initial_pps_pipe(struct intel_display *display,
297 enum port port, pps_check check)
298 {
299 enum pipe pipe;
300
301 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
302 u32 port_sel = intel_de_read(display,
303 PP_ON_DELAYS(display, pipe)) &
304 PANEL_PORT_SELECT_MASK;
305
306 if (port_sel != PANEL_PORT_SELECT_VLV(port))
307 continue;
308
309 if (!check(display, pipe))
310 continue;
311
312 return pipe;
313 }
314
315 return INVALID_PIPE;
316 }
317
318 static void
vlv_initial_power_sequencer_setup(struct intel_dp * intel_dp)319 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
320 {
321 struct intel_display *display = to_intel_display(intel_dp);
322 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
323 enum port port = dig_port->base.port;
324
325 lockdep_assert_held(&display->pps.mutex);
326
327 /* try to find a pipe with this port selected */
328 /* first pick one where the panel is on */
329 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
330 pps_has_pp_on);
331 /* didn't find one? pick one where vdd is on */
332 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
333 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
334 pps_has_vdd_on);
335 /* didn't find one? pick one with just the correct port */
336 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
337 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
338 pps_any);
339
340 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
341 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {
342 drm_dbg_kms(display->drm,
343 "[ENCODER:%d:%s] no initial power sequencer\n",
344 dig_port->base.base.base.id, dig_port->base.base.name);
345 return;
346 }
347
348 drm_dbg_kms(display->drm,
349 "[ENCODER:%d:%s] initial power sequencer: %s\n",
350 dig_port->base.base.base.id, dig_port->base.base.name,
351 pps_name(intel_dp));
352 }
353
intel_num_pps(struct intel_display * display)354 static int intel_num_pps(struct intel_display *display)
355 {
356 if (display->platform.valleyview || display->platform.cherryview)
357 return 2;
358
359 if (display->platform.geminilake || display->platform.broxton)
360 return 2;
361
362 if (INTEL_PCH_TYPE(display) >= PCH_MTL)
363 return 2;
364
365 if (INTEL_PCH_TYPE(display) >= PCH_DG1)
366 return 1;
367
368 if (INTEL_PCH_TYPE(display) >= PCH_ICP)
369 return 2;
370
371 return 1;
372 }
373
intel_pps_is_valid(struct intel_dp * intel_dp)374 static bool intel_pps_is_valid(struct intel_dp *intel_dp)
375 {
376 struct intel_display *display = to_intel_display(intel_dp);
377
378 if (intel_dp->pps.pps_idx == 1 &&
379 INTEL_PCH_TYPE(display) >= PCH_ICP &&
380 INTEL_PCH_TYPE(display) <= PCH_ADP)
381 return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
382
383 return true;
384 }
385
386 static int
bxt_initial_pps_idx(struct intel_display * display,pps_check check)387 bxt_initial_pps_idx(struct intel_display *display, pps_check check)
388 {
389 int pps_idx, pps_num = intel_num_pps(display);
390
391 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
392 if (check(display, pps_idx))
393 return pps_idx;
394 }
395
396 return -1;
397 }
398
399 static bool
pps_initial_setup(struct intel_dp * intel_dp)400 pps_initial_setup(struct intel_dp *intel_dp)
401 {
402 struct intel_display *display = to_intel_display(intel_dp);
403 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
404 struct intel_connector *connector = intel_dp->attached_connector;
405
406 lockdep_assert_held(&display->pps.mutex);
407
408 if (display->platform.valleyview || display->platform.cherryview) {
409 vlv_initial_power_sequencer_setup(intel_dp);
410 return true;
411 }
412
413 /* first ask the VBT */
414 if (intel_num_pps(display) > 1)
415 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
416 else
417 intel_dp->pps.pps_idx = 0;
418
419 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))
420 intel_dp->pps.pps_idx = -1;
421
422 /* VBT wasn't parsed yet? pick one where the panel is on */
423 if (intel_dp->pps.pps_idx < 0)
424 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);
425 /* didn't find one? pick one where vdd is on */
426 if (intel_dp->pps.pps_idx < 0)
427 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);
428 /* didn't find one? pick any */
429 if (intel_dp->pps.pps_idx < 0) {
430 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);
431
432 drm_dbg_kms(display->drm,
433 "[ENCODER:%d:%s] no initial power sequencer, assuming %s\n",
434 encoder->base.base.id, encoder->base.name,
435 pps_name(intel_dp));
436 } else {
437 drm_dbg_kms(display->drm,
438 "[ENCODER:%d:%s] initial power sequencer: %s\n",
439 encoder->base.base.id, encoder->base.name,
440 pps_name(intel_dp));
441 }
442
443 return intel_pps_is_valid(intel_dp);
444 }
445
vlv_pps_reset_all(struct intel_display * display)446 void vlv_pps_reset_all(struct intel_display *display)
447 {
448 struct intel_encoder *encoder;
449
450 if (!HAS_DISPLAY(display))
451 return;
452
453 /*
454 * We can't grab pps_mutex here due to deadlock with power_domain
455 * mutex when power_domain functions are called while holding pps_mutex.
456 * That also means that in order to use vlv_pps_pipe the code needs to
457 * hold both a power domain reference and pps_mutex, and the power domain
458 * reference get/put must be done while _not_ holding pps_mutex.
459 * pps_{lock,unlock}() do these steps in the correct order, so one
460 * should use them always.
461 */
462
463 for_each_intel_dp(display->drm, encoder) {
464 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
465
466 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
467
468 if (encoder->type == INTEL_OUTPUT_EDP)
469 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
470 }
471 }
472
bxt_pps_reset_all(struct intel_display * display)473 void bxt_pps_reset_all(struct intel_display *display)
474 {
475 struct intel_encoder *encoder;
476
477 if (!HAS_DISPLAY(display))
478 return;
479
480 /* See vlv_pps_reset_all() for why we can't grab pps_mutex here. */
481
482 for_each_intel_dp(display->drm, encoder) {
483 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
484
485 if (encoder->type == INTEL_OUTPUT_EDP)
486 intel_dp->pps.bxt_pps_reset = true;
487 }
488 }
489
490 struct pps_registers {
491 i915_reg_t pp_ctrl;
492 i915_reg_t pp_stat;
493 i915_reg_t pp_on;
494 i915_reg_t pp_off;
495 i915_reg_t pp_div;
496 };
497
intel_pps_get_registers(struct intel_dp * intel_dp,struct pps_registers * regs)498 static void intel_pps_get_registers(struct intel_dp *intel_dp,
499 struct pps_registers *regs)
500 {
501 struct intel_display *display = to_intel_display(intel_dp);
502 int pps_idx;
503
504 memset(regs, 0, sizeof(*regs));
505
506 if (display->platform.valleyview || display->platform.cherryview)
507 pps_idx = vlv_power_sequencer_pipe(intel_dp);
508 else if (display->platform.geminilake || display->platform.broxton)
509 pps_idx = bxt_power_sequencer_idx(intel_dp);
510 else
511 pps_idx = intel_dp->pps.pps_idx;
512
513 regs->pp_ctrl = PP_CONTROL(display, pps_idx);
514 regs->pp_stat = PP_STATUS(display, pps_idx);
515 regs->pp_on = PP_ON_DELAYS(display, pps_idx);
516 regs->pp_off = PP_OFF_DELAYS(display, pps_idx);
517
518 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
519 if (display->platform.geminilake || display->platform.broxton ||
520 INTEL_PCH_TYPE(display) >= PCH_CNP)
521 regs->pp_div = INVALID_MMIO_REG;
522 else
523 regs->pp_div = PP_DIVISOR(display, pps_idx);
524 }
525
526 static i915_reg_t
_pp_ctrl_reg(struct intel_dp * intel_dp)527 _pp_ctrl_reg(struct intel_dp *intel_dp)
528 {
529 struct pps_registers regs;
530
531 intel_pps_get_registers(intel_dp, ®s);
532
533 return regs.pp_ctrl;
534 }
535
536 static i915_reg_t
_pp_stat_reg(struct intel_dp * intel_dp)537 _pp_stat_reg(struct intel_dp *intel_dp)
538 {
539 struct pps_registers regs;
540
541 intel_pps_get_registers(intel_dp, ®s);
542
543 return regs.pp_stat;
544 }
545
edp_have_panel_power(struct intel_dp * intel_dp)546 static bool edp_have_panel_power(struct intel_dp *intel_dp)
547 {
548 struct intel_display *display = to_intel_display(intel_dp);
549
550 lockdep_assert_held(&display->pps.mutex);
551
552 if ((display->platform.valleyview || display->platform.cherryview) &&
553 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
554 return false;
555
556 return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
557 }
558
edp_have_panel_vdd(struct intel_dp * intel_dp)559 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
560 {
561 struct intel_display *display = to_intel_display(intel_dp);
562
563 lockdep_assert_held(&display->pps.mutex);
564
565 if ((display->platform.valleyview || display->platform.cherryview) &&
566 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
567 return false;
568
569 return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
570 }
571
intel_pps_check_power_unlocked(struct intel_dp * intel_dp)572 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
573 {
574 struct intel_display *display = to_intel_display(intel_dp);
575 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
576
577 if (!intel_dp_is_edp(intel_dp))
578 return;
579
580 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
581 drm_WARN(display->drm, 1,
582 "[ENCODER:%d:%s] %s powered off while attempting AUX CH communication.\n",
583 dig_port->base.base.base.id, dig_port->base.base.name,
584 pps_name(intel_dp));
585 drm_dbg_kms(display->drm,
586 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
587 dig_port->base.base.base.id, dig_port->base.base.name,
588 pps_name(intel_dp),
589 intel_de_read(display, _pp_stat_reg(intel_dp)),
590 intel_de_read(display, _pp_ctrl_reg(intel_dp)));
591 }
592 }
593
594 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
595 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
596
597 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
598 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
599
600 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
601 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
602
603 static void intel_pps_verify_state(struct intel_dp *intel_dp);
604
wait_panel_status(struct intel_dp * intel_dp,u32 mask,u32 value)605 static void wait_panel_status(struct intel_dp *intel_dp,
606 u32 mask, u32 value)
607 {
608 struct intel_display *display = to_intel_display(intel_dp);
609 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
610 i915_reg_t pp_stat_reg, pp_ctrl_reg;
611
612 lockdep_assert_held(&display->pps.mutex);
613
614 intel_pps_verify_state(intel_dp);
615
616 pp_stat_reg = _pp_stat_reg(intel_dp);
617 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
618
619 drm_dbg_kms(display->drm,
620 "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
621 dig_port->base.base.base.id, dig_port->base.base.name,
622 pps_name(intel_dp),
623 mask, value,
624 intel_de_read(display, pp_stat_reg),
625 intel_de_read(display, pp_ctrl_reg));
626
627 if (intel_de_wait(display, pp_stat_reg, mask, value, 5000))
628 drm_err(display->drm,
629 "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
630 dig_port->base.base.base.id, dig_port->base.base.name,
631 pps_name(intel_dp),
632 intel_de_read(display, pp_stat_reg),
633 intel_de_read(display, pp_ctrl_reg));
634
635 drm_dbg_kms(display->drm, "Wait complete\n");
636 }
637
wait_panel_on(struct intel_dp * intel_dp)638 static void wait_panel_on(struct intel_dp *intel_dp)
639 {
640 struct intel_display *display = to_intel_display(intel_dp);
641 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
642
643 drm_dbg_kms(display->drm,
644 "[ENCODER:%d:%s] %s wait for panel power on\n",
645 dig_port->base.base.base.id, dig_port->base.base.name,
646 pps_name(intel_dp));
647 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
648 }
649
wait_panel_off(struct intel_dp * intel_dp)650 static void wait_panel_off(struct intel_dp *intel_dp)
651 {
652 struct intel_display *display = to_intel_display(intel_dp);
653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
654
655 drm_dbg_kms(display->drm,
656 "[ENCODER:%d:%s] %s wait for panel power off time\n",
657 dig_port->base.base.base.id, dig_port->base.base.name,
658 pps_name(intel_dp));
659 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
660 }
661
wait_panel_power_cycle(struct intel_dp * intel_dp)662 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
663 {
664 struct intel_display *display = to_intel_display(intel_dp);
665 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
666 ktime_t panel_power_on_time;
667 s64 panel_power_off_duration, remaining;
668
669 /* take the difference of current time and panel power off time
670 * and then make panel wait for power_cycle if needed. */
671 panel_power_on_time = ktime_get_boottime();
672 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
673
674 remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
675
676 drm_dbg_kms(display->drm,
677 "[ENCODER:%d:%s] %s wait for panel power cycle (%lld ms remaining)\n",
678 dig_port->base.base.base.id, dig_port->base.base.name,
679 pps_name(intel_dp), remaining);
680
681 /* When we disable the VDD override bit last we have to do the manual
682 * wait. */
683 if (remaining)
684 wait_remaining_ms_from_jiffies(jiffies, remaining);
685
686 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
687 }
688
intel_pps_wait_power_cycle(struct intel_dp * intel_dp)689 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
690 {
691 intel_wakeref_t wakeref;
692
693 if (!intel_dp_is_edp(intel_dp))
694 return;
695
696 with_intel_pps_lock(intel_dp, wakeref)
697 wait_panel_power_cycle(intel_dp);
698 }
699
wait_backlight_on(struct intel_dp * intel_dp)700 static void wait_backlight_on(struct intel_dp *intel_dp)
701 {
702 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
703 intel_dp->pps.backlight_on_delay);
704 }
705
edp_wait_backlight_off(struct intel_dp * intel_dp)706 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
707 {
708 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
709 intel_dp->pps.backlight_off_delay);
710 }
711
712 /* Read the current pp_control value, unlocking the register if it
713 * is locked
714 */
715
ilk_get_pp_control(struct intel_dp * intel_dp)716 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
717 {
718 struct intel_display *display = to_intel_display(intel_dp);
719 u32 control;
720
721 lockdep_assert_held(&display->pps.mutex);
722
723 control = intel_de_read(display, _pp_ctrl_reg(intel_dp));
724 if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&
725 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
726 control &= ~PANEL_UNLOCK_MASK;
727 control |= PANEL_UNLOCK_REGS;
728 }
729 return control;
730 }
731
732 /*
733 * Must be paired with intel_pps_vdd_off_unlocked().
734 * Must hold pps_mutex around the whole on/off sequence.
735 * Can be nested with intel_pps_vdd_{on,off}() calls.
736 */
intel_pps_vdd_on_unlocked(struct intel_dp * intel_dp)737 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
738 {
739 struct intel_display *display = to_intel_display(intel_dp);
740 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
741 u32 pp;
742 i915_reg_t pp_stat_reg, pp_ctrl_reg;
743 bool need_to_disable = !intel_dp->pps.want_panel_vdd;
744
745 if (!intel_dp_is_edp(intel_dp))
746 return false;
747
748 lockdep_assert_held(&display->pps.mutex);
749
750 cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
751 intel_dp->pps.want_panel_vdd = true;
752
753 if (edp_have_panel_vdd(intel_dp))
754 return need_to_disable;
755
756 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
757 intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
758 intel_aux_power_domain(dig_port));
759
760 pp_stat_reg = _pp_stat_reg(intel_dp);
761 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
762
763 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
764 dig_port->base.base.base.id, dig_port->base.base.name,
765 pps_name(intel_dp));
766
767 if (!edp_have_panel_power(intel_dp))
768 wait_panel_power_cycle(intel_dp);
769
770 pp = ilk_get_pp_control(intel_dp);
771 pp |= EDP_FORCE_VDD;
772
773 intel_de_write(display, pp_ctrl_reg, pp);
774 intel_de_posting_read(display, pp_ctrl_reg);
775 drm_dbg_kms(display->drm,
776 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
777 dig_port->base.base.base.id, dig_port->base.base.name,
778 pps_name(intel_dp),
779 intel_de_read(display, pp_stat_reg),
780 intel_de_read(display, pp_ctrl_reg));
781 /*
782 * If the panel wasn't on, delay before accessing aux channel
783 */
784 if (!edp_have_panel_power(intel_dp)) {
785 drm_dbg_kms(display->drm,
786 "[ENCODER:%d:%s] %s panel power wasn't enabled\n",
787 dig_port->base.base.base.id, dig_port->base.base.name,
788 pps_name(intel_dp));
789 msleep(intel_dp->pps.panel_power_up_delay);
790 }
791
792 return need_to_disable;
793 }
794
795 /*
796 * Must be paired with intel_pps_vdd_off() or - to disable
797 * both VDD and panel power - intel_pps_off().
798 * Nested calls to these functions are not allowed since
799 * we drop the lock. Caller must use some higher level
800 * locking to prevent nested calls from other threads.
801 */
intel_pps_vdd_on(struct intel_dp * intel_dp)802 void intel_pps_vdd_on(struct intel_dp *intel_dp)
803 {
804 struct intel_display *display = to_intel_display(intel_dp);
805 intel_wakeref_t wakeref;
806 bool vdd;
807
808 if (!intel_dp_is_edp(intel_dp))
809 return;
810
811 vdd = false;
812 with_intel_pps_lock(intel_dp, wakeref)
813 vdd = intel_pps_vdd_on_unlocked(intel_dp);
814 INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
815 dp_to_dig_port(intel_dp)->base.base.base.id,
816 dp_to_dig_port(intel_dp)->base.base.name,
817 pps_name(intel_dp));
818 }
819
intel_pps_vdd_off_sync_unlocked(struct intel_dp * intel_dp)820 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
821 {
822 struct intel_display *display = to_intel_display(intel_dp);
823 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
824 u32 pp;
825 i915_reg_t pp_stat_reg, pp_ctrl_reg;
826
827 lockdep_assert_held(&display->pps.mutex);
828
829 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);
830
831 if (!edp_have_panel_vdd(intel_dp))
832 return;
833
834 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
835 dig_port->base.base.base.id, dig_port->base.base.name,
836 pps_name(intel_dp));
837
838 pp = ilk_get_pp_control(intel_dp);
839 pp &= ~EDP_FORCE_VDD;
840
841 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
842 pp_stat_reg = _pp_stat_reg(intel_dp);
843
844 intel_de_write(display, pp_ctrl_reg, pp);
845 intel_de_posting_read(display, pp_ctrl_reg);
846
847 /* Make sure sequencer is idle before allowing subsequent activity */
848 drm_dbg_kms(display->drm,
849 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
850 dig_port->base.base.base.id, dig_port->base.base.name,
851 pps_name(intel_dp),
852 intel_de_read(display, pp_stat_reg),
853 intel_de_read(display, pp_ctrl_reg));
854
855 if ((pp & PANEL_POWER_ON) == 0) {
856 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
857 intel_dp_invalidate_source_oui(intel_dp);
858 }
859
860 intel_display_power_put(display,
861 intel_aux_power_domain(dig_port),
862 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
863 }
864
intel_pps_vdd_off_sync(struct intel_dp * intel_dp)865 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
866 {
867 intel_wakeref_t wakeref;
868
869 if (!intel_dp_is_edp(intel_dp))
870 return;
871
872 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
873 /*
874 * vdd might still be enabled due to the delayed vdd off.
875 * Make sure vdd is actually turned off here.
876 */
877 with_intel_pps_lock(intel_dp, wakeref)
878 intel_pps_vdd_off_sync_unlocked(intel_dp);
879 }
880
edp_panel_vdd_work(struct work_struct * __work)881 static void edp_panel_vdd_work(struct work_struct *__work)
882 {
883 struct intel_pps *pps = container_of(to_delayed_work(__work),
884 struct intel_pps, panel_vdd_work);
885 struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
886 intel_wakeref_t wakeref;
887
888 with_intel_pps_lock(intel_dp, wakeref) {
889 if (!intel_dp->pps.want_panel_vdd)
890 intel_pps_vdd_off_sync_unlocked(intel_dp);
891 }
892 }
893
edp_panel_vdd_schedule_off(struct intel_dp * intel_dp)894 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
895 {
896 struct intel_display *display = to_intel_display(intel_dp);
897 unsigned long delay;
898
899 /*
900 * We may not yet know the real power sequencing delays,
901 * so keep VDD enabled until we're done with init.
902 */
903 if (intel_dp->pps.initializing)
904 return;
905
906 /*
907 * Queue the timer to fire a long time from now (relative to the power
908 * down delay) to keep the panel power up across a sequence of
909 * operations.
910 */
911 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
912 queue_delayed_work(display->wq.unordered,
913 &intel_dp->pps.panel_vdd_work, delay);
914 }
915
916 /*
917 * Must be paired with edp_panel_vdd_on().
918 * Must hold pps_mutex around the whole on/off sequence.
919 * Can be nested with intel_pps_vdd_{on,off}() calls.
920 */
intel_pps_vdd_off_unlocked(struct intel_dp * intel_dp,bool sync)921 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
922 {
923 struct intel_display *display = to_intel_display(intel_dp);
924
925 if (!intel_dp_is_edp(intel_dp))
926 return;
927
928 lockdep_assert_held(&display->pps.mutex);
929
930 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
931 "[ENCODER:%d:%s] %s VDD not forced on",
932 dp_to_dig_port(intel_dp)->base.base.base.id,
933 dp_to_dig_port(intel_dp)->base.base.name,
934 pps_name(intel_dp));
935
936 intel_dp->pps.want_panel_vdd = false;
937
938 if (sync)
939 intel_pps_vdd_off_sync_unlocked(intel_dp);
940 else
941 edp_panel_vdd_schedule_off(intel_dp);
942 }
943
intel_pps_vdd_off(struct intel_dp * intel_dp)944 void intel_pps_vdd_off(struct intel_dp *intel_dp)
945 {
946 intel_wakeref_t wakeref;
947
948 if (!intel_dp_is_edp(intel_dp))
949 return;
950
951 with_intel_pps_lock(intel_dp, wakeref)
952 intel_pps_vdd_off_unlocked(intel_dp, false);
953 }
954
intel_pps_on_unlocked(struct intel_dp * intel_dp)955 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
956 {
957 struct intel_display *display = to_intel_display(intel_dp);
958 u32 pp;
959 i915_reg_t pp_ctrl_reg;
960
961 lockdep_assert_held(&display->pps.mutex);
962
963 if (!intel_dp_is_edp(intel_dp))
964 return;
965
966 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
967 dp_to_dig_port(intel_dp)->base.base.base.id,
968 dp_to_dig_port(intel_dp)->base.base.name,
969 pps_name(intel_dp));
970
971 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),
972 "[ENCODER:%d:%s] %s panel power already on\n",
973 dp_to_dig_port(intel_dp)->base.base.base.id,
974 dp_to_dig_port(intel_dp)->base.base.name,
975 pps_name(intel_dp)))
976 return;
977
978 wait_panel_power_cycle(intel_dp);
979
980 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
981 pp = ilk_get_pp_control(intel_dp);
982 if (display->platform.ironlake) {
983 /* ILK workaround: disable reset around power sequence */
984 pp &= ~PANEL_POWER_RESET;
985 intel_de_write(display, pp_ctrl_reg, pp);
986 intel_de_posting_read(display, pp_ctrl_reg);
987 }
988
989 /*
990 * WA: 22019252566
991 * Disable DPLS gating around power sequence.
992 */
993 if (IS_DISPLAY_VER(display, 13, 14))
994 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
995 0, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
996
997 pp |= PANEL_POWER_ON;
998 if (!display->platform.ironlake)
999 pp |= PANEL_POWER_RESET;
1000
1001 intel_de_write(display, pp_ctrl_reg, pp);
1002 intel_de_posting_read(display, pp_ctrl_reg);
1003
1004 wait_panel_on(intel_dp);
1005 intel_dp->pps.last_power_on = jiffies;
1006
1007 if (IS_DISPLAY_VER(display, 13, 14))
1008 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1009 PCH_DPLSUNIT_CLOCK_GATE_DISABLE, 0);
1010
1011 if (display->platform.ironlake) {
1012 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1013 intel_de_write(display, pp_ctrl_reg, pp);
1014 intel_de_posting_read(display, pp_ctrl_reg);
1015 }
1016 }
1017
intel_pps_on(struct intel_dp * intel_dp)1018 void intel_pps_on(struct intel_dp *intel_dp)
1019 {
1020 intel_wakeref_t wakeref;
1021
1022 if (!intel_dp_is_edp(intel_dp))
1023 return;
1024
1025 with_intel_pps_lock(intel_dp, wakeref)
1026 intel_pps_on_unlocked(intel_dp);
1027 }
1028
intel_pps_off_unlocked(struct intel_dp * intel_dp)1029 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
1030 {
1031 struct intel_display *display = to_intel_display(intel_dp);
1032 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1033 u32 pp;
1034 i915_reg_t pp_ctrl_reg;
1035
1036 lockdep_assert_held(&display->pps.mutex);
1037
1038 if (!intel_dp_is_edp(intel_dp))
1039 return;
1040
1041 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
1042 dig_port->base.base.base.id, dig_port->base.base.name,
1043 pps_name(intel_dp));
1044
1045 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,
1046 "[ENCODER:%d:%s] %s need VDD to turn off panel\n",
1047 dig_port->base.base.base.id, dig_port->base.base.name,
1048 pps_name(intel_dp));
1049
1050 pp = ilk_get_pp_control(intel_dp);
1051 /* We need to switch off panel power _and_ force vdd, for otherwise some
1052 * panels get very unhappy and cease to work. */
1053 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1054 EDP_BLC_ENABLE);
1055
1056 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1057
1058 intel_dp->pps.want_panel_vdd = false;
1059
1060 intel_de_write(display, pp_ctrl_reg, pp);
1061 intel_de_posting_read(display, pp_ctrl_reg);
1062
1063 wait_panel_off(intel_dp);
1064 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1065
1066 intel_dp_invalidate_source_oui(intel_dp);
1067
1068 /* We got a reference when we enabled the VDD. */
1069 intel_display_power_put(display,
1070 intel_aux_power_domain(dig_port),
1071 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
1072 }
1073
intel_pps_off(struct intel_dp * intel_dp)1074 void intel_pps_off(struct intel_dp *intel_dp)
1075 {
1076 intel_wakeref_t wakeref;
1077
1078 if (!intel_dp_is_edp(intel_dp))
1079 return;
1080
1081 with_intel_pps_lock(intel_dp, wakeref)
1082 intel_pps_off_unlocked(intel_dp);
1083 }
1084
1085 /* Enable backlight in the panel power control. */
intel_pps_backlight_on(struct intel_dp * intel_dp)1086 void intel_pps_backlight_on(struct intel_dp *intel_dp)
1087 {
1088 struct intel_display *display = to_intel_display(intel_dp);
1089 intel_wakeref_t wakeref;
1090
1091 /*
1092 * If we enable the backlight right away following a panel power
1093 * on, we may see slight flicker as the panel syncs with the eDP
1094 * link. So delay a bit to make sure the image is solid before
1095 * allowing it to appear.
1096 */
1097 wait_backlight_on(intel_dp);
1098
1099 with_intel_pps_lock(intel_dp, wakeref) {
1100 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1101 u32 pp;
1102
1103 pp = ilk_get_pp_control(intel_dp);
1104 pp |= EDP_BLC_ENABLE;
1105
1106 intel_de_write(display, pp_ctrl_reg, pp);
1107 intel_de_posting_read(display, pp_ctrl_reg);
1108 }
1109 }
1110
1111 /* Disable backlight in the panel power control. */
intel_pps_backlight_off(struct intel_dp * intel_dp)1112 void intel_pps_backlight_off(struct intel_dp *intel_dp)
1113 {
1114 struct intel_display *display = to_intel_display(intel_dp);
1115 intel_wakeref_t wakeref;
1116
1117 if (!intel_dp_is_edp(intel_dp))
1118 return;
1119
1120 with_intel_pps_lock(intel_dp, wakeref) {
1121 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1122 u32 pp;
1123
1124 pp = ilk_get_pp_control(intel_dp);
1125 pp &= ~EDP_BLC_ENABLE;
1126
1127 intel_de_write(display, pp_ctrl_reg, pp);
1128 intel_de_posting_read(display, pp_ctrl_reg);
1129 }
1130
1131 intel_dp->pps.last_backlight_off = jiffies;
1132 edp_wait_backlight_off(intel_dp);
1133 }
1134
1135 /*
1136 * Hook for controlling the panel power control backlight through the bl_power
1137 * sysfs attribute. Take care to handle multiple calls.
1138 */
intel_pps_backlight_power(struct intel_connector * connector,bool enable)1139 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
1140 {
1141 struct intel_display *display = to_intel_display(connector);
1142 struct intel_dp *intel_dp = intel_attached_dp(connector);
1143 intel_wakeref_t wakeref;
1144 bool is_enabled;
1145
1146 is_enabled = false;
1147 with_intel_pps_lock(intel_dp, wakeref)
1148 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1149 if (is_enabled == enable)
1150 return;
1151
1152 drm_dbg_kms(display->drm, "panel power control backlight %s\n",
1153 str_enable_disable(enable));
1154
1155 if (enable)
1156 intel_pps_backlight_on(intel_dp);
1157 else
1158 intel_pps_backlight_off(intel_dp);
1159 }
1160
vlv_detach_power_sequencer(struct intel_dp * intel_dp)1161 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
1162 {
1163 struct intel_display *display = to_intel_display(intel_dp);
1164 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1165 enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
1166 i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
1167
1168 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1169
1170 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
1171 return;
1172
1173 intel_pps_vdd_off_sync_unlocked(intel_dp);
1174
1175 /*
1176 * VLV seems to get confused when multiple power sequencers
1177 * have the same port selected (even if only one has power/vdd
1178 * enabled). The failure manifests as vlv_wait_port_ready() failing
1179 * CHV on the other hand doesn't seem to mind having the same port
1180 * selected in multiple power sequencers, but let's clear the
1181 * port select always when logically disconnecting a power sequencer
1182 * from a port.
1183 */
1184 drm_dbg_kms(display->drm,
1185 "detaching %s from [ENCODER:%d:%s]\n",
1186 pps_name(intel_dp),
1187 dig_port->base.base.base.id, dig_port->base.base.name);
1188 intel_de_write(display, pp_on_reg, 0);
1189 intel_de_posting_read(display, pp_on_reg);
1190
1191 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
1192 }
1193
vlv_steal_power_sequencer(struct intel_display * display,enum pipe pipe)1194 static void vlv_steal_power_sequencer(struct intel_display *display,
1195 enum pipe pipe)
1196 {
1197 struct intel_encoder *encoder;
1198
1199 lockdep_assert_held(&display->pps.mutex);
1200
1201 for_each_intel_dp(display->drm, encoder) {
1202 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1203
1204 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,
1205 "stealing PPS %c from active [ENCODER:%d:%s]\n",
1206 pipe_name(pipe), encoder->base.base.id,
1207 encoder->base.name);
1208
1209 if (intel_dp->pps.vlv_pps_pipe != pipe)
1210 continue;
1211
1212 drm_dbg_kms(display->drm,
1213 "stealing PPS %c from [ENCODER:%d:%s]\n",
1214 pipe_name(pipe), encoder->base.base.id,
1215 encoder->base.name);
1216
1217 /* make sure vdd is off before we steal it */
1218 vlv_detach_power_sequencer(intel_dp);
1219 }
1220 }
1221
vlv_active_pipe(struct intel_dp * intel_dp)1222 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
1223 {
1224 struct intel_display *display = to_intel_display(intel_dp);
1225 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1226 enum pipe pipe;
1227
1228 if (g4x_dp_port_enabled(display, intel_dp->output_reg,
1229 encoder->port, &pipe))
1230 return pipe;
1231
1232 return INVALID_PIPE;
1233 }
1234
1235 /* Call on all DP, not just eDP */
vlv_pps_pipe_init(struct intel_dp * intel_dp)1236 void vlv_pps_pipe_init(struct intel_dp *intel_dp)
1237 {
1238 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
1239 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
1240 }
1241
1242 /* Call on all DP, not just eDP */
vlv_pps_pipe_reset(struct intel_dp * intel_dp)1243 void vlv_pps_pipe_reset(struct intel_dp *intel_dp)
1244 {
1245 intel_wakeref_t wakeref;
1246
1247 with_intel_pps_lock(intel_dp, wakeref)
1248 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
1249 }
1250
vlv_pps_backlight_initial_pipe(struct intel_dp * intel_dp)1251 enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp)
1252 {
1253 enum pipe pipe;
1254
1255 /*
1256 * Figure out the current pipe for the initial backlight setup. If the
1257 * current pipe isn't valid, try the PPS pipe, and if that fails just
1258 * assume pipe A.
1259 */
1260 pipe = vlv_active_pipe(intel_dp);
1261
1262 if (pipe != PIPE_A && pipe != PIPE_B)
1263 pipe = intel_dp->pps.vlv_pps_pipe;
1264
1265 if (pipe != PIPE_A && pipe != PIPE_B)
1266 pipe = PIPE_A;
1267
1268 return pipe;
1269 }
1270
1271 /* Call on all DP, not just eDP */
vlv_pps_port_enable_unlocked(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1272 void vlv_pps_port_enable_unlocked(struct intel_encoder *encoder,
1273 const struct intel_crtc_state *crtc_state)
1274 {
1275 struct intel_display *display = to_intel_display(encoder);
1276 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1278
1279 lockdep_assert_held(&display->pps.mutex);
1280
1281 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1282
1283 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&
1284 intel_dp->pps.vlv_pps_pipe != crtc->pipe) {
1285 /*
1286 * If another power sequencer was being used on this
1287 * port previously make sure to turn off vdd there while
1288 * we still have control of it.
1289 */
1290 vlv_detach_power_sequencer(intel_dp);
1291 }
1292
1293 /*
1294 * We may be stealing the power
1295 * sequencer from another port.
1296 */
1297 vlv_steal_power_sequencer(display, crtc->pipe);
1298
1299 intel_dp->pps.vlv_active_pipe = crtc->pipe;
1300
1301 if (!intel_dp_is_edp(intel_dp))
1302 return;
1303
1304 /* now it's all ours */
1305 intel_dp->pps.vlv_pps_pipe = crtc->pipe;
1306
1307 drm_dbg_kms(display->drm,
1308 "initializing %s for [ENCODER:%d:%s]\n",
1309 pps_name(intel_dp),
1310 encoder->base.base.id, encoder->base.name);
1311
1312 /* init power sequencer on this pipe and port */
1313 pps_init_delays(intel_dp);
1314 pps_init_registers(intel_dp, true);
1315 }
1316
1317 /* Call on all DP, not just eDP */
vlv_pps_port_disable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1318 void vlv_pps_port_disable(struct intel_encoder *encoder,
1319 const struct intel_crtc_state *crtc_state)
1320 {
1321 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1322
1323 intel_wakeref_t wakeref;
1324
1325 with_intel_pps_lock(intel_dp, wakeref)
1326 intel_dp->pps.vlv_active_pipe = INVALID_PIPE;
1327 }
1328
pps_vdd_init(struct intel_dp * intel_dp)1329 static void pps_vdd_init(struct intel_dp *intel_dp)
1330 {
1331 struct intel_display *display = to_intel_display(intel_dp);
1332 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1333
1334 lockdep_assert_held(&display->pps.mutex);
1335
1336 if (!edp_have_panel_vdd(intel_dp))
1337 return;
1338
1339 /*
1340 * The VDD bit needs a power domain reference, so if the bit is
1341 * already enabled when we boot or resume, grab this reference and
1342 * schedule a vdd off, so we don't hold on to the reference
1343 * indefinitely.
1344 */
1345 drm_dbg_kms(display->drm,
1346 "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n",
1347 dig_port->base.base.base.id, dig_port->base.base.name,
1348 pps_name(intel_dp));
1349 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
1350 intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
1351 intel_aux_power_domain(dig_port));
1352 }
1353
intel_pps_have_panel_power_or_vdd(struct intel_dp * intel_dp)1354 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
1355 {
1356 intel_wakeref_t wakeref;
1357 bool have_power = false;
1358
1359 with_intel_pps_lock(intel_dp, wakeref) {
1360 have_power = edp_have_panel_power(intel_dp) ||
1361 edp_have_panel_vdd(intel_dp);
1362 }
1363
1364 return have_power;
1365 }
1366
pps_init_timestamps(struct intel_dp * intel_dp)1367 static void pps_init_timestamps(struct intel_dp *intel_dp)
1368 {
1369 /*
1370 * Initialize panel power off time to 0, assuming panel power could have
1371 * been toggled between kernel boot and now only by a previously loaded
1372 * and removed i915, which has already ensured sufficient power off
1373 * delay at module remove.
1374 */
1375 intel_dp->pps.panel_power_off_time = 0;
1376 intel_dp->pps.last_power_on = jiffies;
1377 intel_dp->pps.last_backlight_off = jiffies;
1378 }
1379
1380 static void
intel_pps_readout_hw_state(struct intel_dp * intel_dp,struct intel_pps_delays * seq)1381 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *seq)
1382 {
1383 struct intel_display *display = to_intel_display(intel_dp);
1384 u32 pp_on, pp_off, pp_ctl, power_cycle_delay;
1385 struct pps_registers regs;
1386
1387 intel_pps_get_registers(intel_dp, ®s);
1388
1389 pp_ctl = ilk_get_pp_control(intel_dp);
1390
1391 /* Ensure PPS is unlocked */
1392 if (!HAS_DDI(display))
1393 intel_de_write(display, regs.pp_ctrl, pp_ctl);
1394
1395 pp_on = intel_de_read(display, regs.pp_on);
1396 pp_off = intel_de_read(display, regs.pp_off);
1397
1398 /* Pull timing values out of registers */
1399 seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1400 seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1401 seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1402 seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1403
1404 if (i915_mmio_reg_valid(regs.pp_div)) {
1405 u32 pp_div;
1406
1407 pp_div = intel_de_read(display, regs.pp_div);
1408
1409 power_cycle_delay = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div);
1410 } else {
1411 power_cycle_delay = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl);
1412 }
1413
1414 /* hardware wants <delay>+1 in 100ms units */
1415 seq->power_cycle = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0;
1416 }
1417
1418 static void
intel_pps_dump_state(struct intel_dp * intel_dp,const char * state_name,const struct intel_pps_delays * seq)1419 intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
1420 const struct intel_pps_delays *seq)
1421 {
1422 struct intel_display *display = to_intel_display(intel_dp);
1423
1424 drm_dbg_kms(display->drm,
1425 "%s power_up %d backlight_on %d backlight_off %d power_down %d power_cycle %d\n",
1426 state_name, seq->power_up, seq->backlight_on,
1427 seq->backlight_off, seq->power_down, seq->power_cycle);
1428 }
1429
1430 static void
intel_pps_verify_state(struct intel_dp * intel_dp)1431 intel_pps_verify_state(struct intel_dp *intel_dp)
1432 {
1433 struct intel_display *display = to_intel_display(intel_dp);
1434 struct intel_pps_delays hw;
1435 struct intel_pps_delays *sw = &intel_dp->pps.pps_delays;
1436
1437 intel_pps_readout_hw_state(intel_dp, &hw);
1438
1439 if (hw.power_up != sw->power_up ||
1440 hw.backlight_on != sw->backlight_on ||
1441 hw.backlight_off != sw->backlight_off ||
1442 hw.power_down != sw->power_down ||
1443 hw.power_cycle != sw->power_cycle) {
1444 drm_err(display->drm, "PPS state mismatch\n");
1445 intel_pps_dump_state(intel_dp, "sw", sw);
1446 intel_pps_dump_state(intel_dp, "hw", &hw);
1447 }
1448 }
1449
pps_delays_valid(struct intel_pps_delays * delays)1450 static bool pps_delays_valid(struct intel_pps_delays *delays)
1451 {
1452 return delays->power_up || delays->backlight_on || delays->backlight_off ||
1453 delays->power_down || delays->power_cycle;
1454 }
1455
msecs_to_pps_units(int msecs)1456 static int msecs_to_pps_units(int msecs)
1457 {
1458 /* PPS uses 100us units */
1459 return msecs * 10;
1460 }
1461
pps_units_to_msecs(int val)1462 static int pps_units_to_msecs(int val)
1463 {
1464 /* PPS uses 100us units */
1465 return DIV_ROUND_UP(val, 10);
1466 }
1467
pps_init_delays_bios(struct intel_dp * intel_dp,struct intel_pps_delays * bios)1468 static void pps_init_delays_bios(struct intel_dp *intel_dp,
1469 struct intel_pps_delays *bios)
1470 {
1471 struct intel_display *display = to_intel_display(intel_dp);
1472
1473 lockdep_assert_held(&display->pps.mutex);
1474
1475 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
1476 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
1477
1478 *bios = intel_dp->pps.bios_pps_delays;
1479
1480 intel_pps_dump_state(intel_dp, "bios", bios);
1481 }
1482
pps_init_delays_vbt(struct intel_dp * intel_dp,struct intel_pps_delays * vbt)1483 static void pps_init_delays_vbt(struct intel_dp *intel_dp,
1484 struct intel_pps_delays *vbt)
1485 {
1486 struct intel_display *display = to_intel_display(intel_dp);
1487 struct intel_connector *connector = intel_dp->attached_connector;
1488
1489 *vbt = connector->panel.vbt.edp.pps;
1490
1491 if (!pps_delays_valid(vbt))
1492 return;
1493
1494 /*
1495 * On Toshiba Satellite P50-C-18C system the VBT T12 delay
1496 * of 500ms appears to be too short. Occasionally the panel
1497 * just fails to power back on. Increasing the delay to 800ms
1498 * seems sufficient to avoid this problem.
1499 */
1500 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {
1501 vbt->power_cycle = max_t(u16, vbt->power_cycle, msecs_to_pps_units(1300));
1502 drm_dbg_kms(display->drm,
1503 "Increasing T12 panel delay as per the quirk to %d\n",
1504 vbt->power_cycle);
1505 }
1506
1507 intel_pps_dump_state(intel_dp, "vbt", vbt);
1508 }
1509
pps_init_delays_spec(struct intel_dp * intel_dp,struct intel_pps_delays * spec)1510 static void pps_init_delays_spec(struct intel_dp *intel_dp,
1511 struct intel_pps_delays *spec)
1512 {
1513 struct intel_display *display = to_intel_display(intel_dp);
1514
1515 lockdep_assert_held(&display->pps.mutex);
1516
1517 /* Upper limits from eDP 1.3 spec */
1518 spec->power_up = msecs_to_pps_units(10 + 200); /* T1+T3 */
1519 spec->backlight_on = msecs_to_pps_units(50); /* no limit for T8, use T7 instead */
1520 spec->backlight_off = msecs_to_pps_units(50); /* no limit for T9, make it symmetric with T8 */
1521 spec->power_down = msecs_to_pps_units(500); /* T10 */
1522 spec->power_cycle = msecs_to_pps_units(10 + 500); /* T11+T12 */
1523
1524 intel_pps_dump_state(intel_dp, "spec", spec);
1525 }
1526
pps_init_delays(struct intel_dp * intel_dp)1527 static void pps_init_delays(struct intel_dp *intel_dp)
1528 {
1529 struct intel_display *display = to_intel_display(intel_dp);
1530 struct intel_pps_delays cur, vbt, spec,
1531 *final = &intel_dp->pps.pps_delays;
1532
1533 lockdep_assert_held(&display->pps.mutex);
1534
1535 /* already initialized? */
1536 if (pps_delays_valid(final))
1537 return;
1538
1539 pps_init_delays_bios(intel_dp, &cur);
1540 pps_init_delays_vbt(intel_dp, &vbt);
1541 pps_init_delays_spec(intel_dp, &spec);
1542
1543 /* Use the max of the register settings and vbt. If both are
1544 * unset, fall back to the spec limits. */
1545 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
1546 spec.field : \
1547 max(cur.field, vbt.field))
1548 assign_final(power_up);
1549 assign_final(backlight_on);
1550 assign_final(backlight_off);
1551 assign_final(power_down);
1552 assign_final(power_cycle);
1553 #undef assign_final
1554
1555 intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up);
1556 intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on);
1557 intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off);
1558 intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down);
1559 intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle);
1560
1561 drm_dbg_kms(display->drm,
1562 "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1563 intel_dp->pps.panel_power_up_delay,
1564 intel_dp->pps.panel_power_down_delay,
1565 intel_dp->pps.panel_power_cycle_delay);
1566
1567 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",
1568 intel_dp->pps.backlight_on_delay,
1569 intel_dp->pps.backlight_off_delay);
1570
1571 /*
1572 * We override the HW backlight delays to 1 because we do manual waits
1573 * on them. For backlight_on, even BSpec recommends doing it. For
1574 * backlight_off, if we don't do this, we'll end up waiting for the
1575 * backlight off delay twice: once when we do the manual sleep, and
1576 * once when we disable the panel and wait for the PP_STATUS bit to
1577 * become zero.
1578 */
1579 final->backlight_on = 1;
1580 final->backlight_off = 1;
1581
1582 /*
1583 * HW has only a 100msec granularity for power_cycle so round it up
1584 * accordingly.
1585 */
1586 final->power_cycle = roundup(final->power_cycle, msecs_to_pps_units(100));
1587 }
1588
pps_init_registers(struct intel_dp * intel_dp,bool force_disable_vdd)1589 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
1590 {
1591 struct intel_display *display = to_intel_display(intel_dp);
1592 u32 pp_on, pp_off, port_sel = 0;
1593 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;
1594 struct pps_registers regs;
1595 enum port port = dp_to_dig_port(intel_dp)->base.port;
1596 const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays;
1597
1598 lockdep_assert_held(&display->pps.mutex);
1599
1600 intel_pps_get_registers(intel_dp, ®s);
1601
1602 /*
1603 * On some VLV machines the BIOS can leave the VDD
1604 * enabled even on power sequencers which aren't
1605 * hooked up to any port. This would mess up the
1606 * power domain tracking the first time we pick
1607 * one of these power sequencers for use since
1608 * intel_pps_vdd_on_unlocked() would notice that the VDD was
1609 * already on and therefore wouldn't grab the power
1610 * domain reference. Disable VDD first to avoid this.
1611 * This also avoids spuriously turning the VDD on as
1612 * soon as the new power sequencer gets initialized.
1613 */
1614 if (force_disable_vdd) {
1615 u32 pp = ilk_get_pp_control(intel_dp);
1616
1617 drm_WARN(display->drm, pp & PANEL_POWER_ON,
1618 "Panel power already on\n");
1619
1620 if (pp & EDP_FORCE_VDD)
1621 drm_dbg_kms(display->drm,
1622 "VDD already on, disabling first\n");
1623
1624 pp &= ~EDP_FORCE_VDD;
1625
1626 intel_de_write(display, regs.pp_ctrl, pp);
1627 }
1628
1629 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->power_up) |
1630 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->backlight_on);
1631 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->backlight_off) |
1632 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->power_down);
1633
1634 /* Haswell doesn't have any port selection bits for the panel
1635 * power sequencer any more. */
1636 if (display->platform.valleyview || display->platform.cherryview) {
1637 port_sel = PANEL_PORT_SELECT_VLV(port);
1638 } else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {
1639 switch (port) {
1640 case PORT_A:
1641 port_sel = PANEL_PORT_SELECT_DPA;
1642 break;
1643 case PORT_C:
1644 port_sel = PANEL_PORT_SELECT_DPC;
1645 break;
1646 case PORT_D:
1647 port_sel = PANEL_PORT_SELECT_DPD;
1648 break;
1649 default:
1650 MISSING_CASE(port);
1651 break;
1652 }
1653 }
1654
1655 pp_on |= port_sel;
1656
1657 intel_de_write(display, regs.pp_on, pp_on);
1658 intel_de_write(display, regs.pp_off, pp_off);
1659
1660 /*
1661 * Compute the divisor for the pp clock, simply match the Bspec formula.
1662 */
1663 if (i915_mmio_reg_valid(regs.pp_div))
1664 intel_de_write(display, regs.pp_div,
1665 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK,
1666 (100 * div) / 2 - 1) |
1667 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
1668 DIV_ROUND_UP(seq->power_cycle, 1000) + 1));
1669 else
1670 intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,
1671 REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK,
1672 DIV_ROUND_UP(seq->power_cycle, 1000) + 1));
1673
1674 drm_dbg_kms(display->drm,
1675 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1676 intel_de_read(display, regs.pp_on),
1677 intel_de_read(display, regs.pp_off),
1678 i915_mmio_reg_valid(regs.pp_div) ?
1679 intel_de_read(display, regs.pp_div) :
1680 (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1681 }
1682
intel_pps_encoder_reset(struct intel_dp * intel_dp)1683 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1684 {
1685 struct intel_display *display = to_intel_display(intel_dp);
1686 intel_wakeref_t wakeref;
1687
1688 if (!intel_dp_is_edp(intel_dp))
1689 return;
1690
1691 with_intel_pps_lock(intel_dp, wakeref) {
1692 /*
1693 * Reinit the power sequencer also on the resume path, in case
1694 * BIOS did something nasty with it.
1695 */
1696 if (display->platform.valleyview || display->platform.cherryview)
1697 vlv_initial_power_sequencer_setup(intel_dp);
1698
1699 pps_init_delays(intel_dp);
1700 pps_init_registers(intel_dp, false);
1701 pps_vdd_init(intel_dp);
1702
1703 if (edp_have_panel_vdd(intel_dp))
1704 edp_panel_vdd_schedule_off(intel_dp);
1705 }
1706 }
1707
intel_pps_init(struct intel_dp * intel_dp)1708 bool intel_pps_init(struct intel_dp *intel_dp)
1709 {
1710 intel_wakeref_t wakeref;
1711 bool ret;
1712
1713 intel_dp->pps.initializing = true;
1714 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1715
1716 pps_init_timestamps(intel_dp);
1717
1718 with_intel_pps_lock(intel_dp, wakeref) {
1719 ret = pps_initial_setup(intel_dp);
1720
1721 pps_init_delays(intel_dp);
1722 pps_init_registers(intel_dp, false);
1723 pps_vdd_init(intel_dp);
1724 }
1725
1726 return ret;
1727 }
1728
pps_init_late(struct intel_dp * intel_dp)1729 static void pps_init_late(struct intel_dp *intel_dp)
1730 {
1731 struct intel_display *display = to_intel_display(intel_dp);
1732 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1733 struct intel_connector *connector = intel_dp->attached_connector;
1734
1735 if (display->platform.valleyview || display->platform.cherryview)
1736 return;
1737
1738 if (intel_num_pps(display) < 2)
1739 return;
1740
1741 drm_WARN(display->drm,
1742 connector->panel.vbt.backlight.controller >= 0 &&
1743 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,
1744 "[ENCODER:%d:%s] power sequencer mismatch: %d (initial) vs. %d (VBT)\n",
1745 encoder->base.base.id, encoder->base.name,
1746 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);
1747
1748 if (connector->panel.vbt.backlight.controller >= 0)
1749 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
1750 }
1751
intel_pps_init_late(struct intel_dp * intel_dp)1752 void intel_pps_init_late(struct intel_dp *intel_dp)
1753 {
1754 intel_wakeref_t wakeref;
1755
1756 with_intel_pps_lock(intel_dp, wakeref) {
1757 /* Reinit delays after per-panel info has been parsed from VBT */
1758 pps_init_late(intel_dp);
1759
1760 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
1761 pps_init_delays(intel_dp);
1762 pps_init_registers(intel_dp, false);
1763
1764 intel_dp->pps.initializing = false;
1765
1766 if (edp_have_panel_vdd(intel_dp))
1767 edp_panel_vdd_schedule_off(intel_dp);
1768 }
1769 }
1770
intel_pps_unlock_regs_wa(struct intel_display * display)1771 void intel_pps_unlock_regs_wa(struct intel_display *display)
1772 {
1773 int pps_num;
1774 int pps_idx;
1775
1776 if (!HAS_DISPLAY(display) || HAS_DDI(display))
1777 return;
1778 /*
1779 * This w/a is needed at least on CPT/PPT, but to be sure apply it
1780 * everywhere where registers can be write protected.
1781 */
1782 pps_num = intel_num_pps(display);
1783
1784 for (pps_idx = 0; pps_idx < pps_num; pps_idx++)
1785 intel_de_rmw(display, PP_CONTROL(display, pps_idx),
1786 PANEL_UNLOCK_MASK, PANEL_UNLOCK_REGS);
1787 }
1788
intel_pps_setup(struct intel_display * display)1789 void intel_pps_setup(struct intel_display *display)
1790 {
1791 if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton)
1792 display->pps.mmio_base = PCH_PPS_BASE;
1793 else if (display->platform.valleyview || display->platform.cherryview)
1794 display->pps.mmio_base = VLV_PPS_BASE;
1795 else
1796 display->pps.mmio_base = PPS_BASE;
1797 }
1798
intel_pps_show(struct seq_file * m,void * data)1799 static int intel_pps_show(struct seq_file *m, void *data)
1800 {
1801 struct intel_connector *connector = m->private;
1802 struct intel_dp *intel_dp = intel_attached_dp(connector);
1803
1804 if (connector->base.status != connector_status_connected)
1805 return -ENODEV;
1806
1807 seq_printf(m, "Panel power up delay: %d\n",
1808 intel_dp->pps.panel_power_up_delay);
1809 seq_printf(m, "Panel power down delay: %d\n",
1810 intel_dp->pps.panel_power_down_delay);
1811 seq_printf(m, "Panel power cycle delay: %d\n",
1812 intel_dp->pps.panel_power_cycle_delay);
1813 seq_printf(m, "Backlight on delay: %d\n",
1814 intel_dp->pps.backlight_on_delay);
1815 seq_printf(m, "Backlight off delay: %d\n",
1816 intel_dp->pps.backlight_off_delay);
1817
1818 return 0;
1819 }
1820 DEFINE_SHOW_ATTRIBUTE(intel_pps);
1821
intel_pps_connector_debugfs_add(struct intel_connector * connector)1822 void intel_pps_connector_debugfs_add(struct intel_connector *connector)
1823 {
1824 struct dentry *root = connector->base.debugfs_entry;
1825 int connector_type = connector->base.connector_type;
1826
1827 if (connector_type == DRM_MODE_CONNECTOR_eDP)
1828 debugfs_create_file("i915_panel_timings", 0444, root,
1829 connector, &intel_pps_fops);
1830 }
1831
assert_pps_unlocked(struct intel_display * display,enum pipe pipe)1832 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
1833 {
1834 i915_reg_t pp_reg;
1835 u32 val;
1836 enum pipe panel_pipe = INVALID_PIPE;
1837 bool locked = true;
1838
1839 if (drm_WARN_ON(display->drm, HAS_DDI(display)))
1840 return;
1841
1842 if (HAS_PCH_SPLIT(display)) {
1843 u32 port_sel;
1844
1845 pp_reg = PP_CONTROL(display, 0);
1846 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
1847 PANEL_PORT_SELECT_MASK;
1848
1849 switch (port_sel) {
1850 case PANEL_PORT_SELECT_LVDS:
1851 intel_lvds_port_enabled(display, PCH_LVDS, &panel_pipe);
1852 break;
1853 case PANEL_PORT_SELECT_DPA:
1854 g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);
1855 break;
1856 case PANEL_PORT_SELECT_DPC:
1857 g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);
1858 break;
1859 case PANEL_PORT_SELECT_DPD:
1860 g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);
1861 break;
1862 default:
1863 MISSING_CASE(port_sel);
1864 break;
1865 }
1866 } else if (display->platform.valleyview || display->platform.cherryview) {
1867 /* presumably write lock depends on pipe, not port select */
1868 pp_reg = PP_CONTROL(display, pipe);
1869 panel_pipe = pipe;
1870 } else {
1871 u32 port_sel;
1872
1873 pp_reg = PP_CONTROL(display, 0);
1874 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
1875 PANEL_PORT_SELECT_MASK;
1876
1877 drm_WARN_ON(display->drm,
1878 port_sel != PANEL_PORT_SELECT_LVDS);
1879 intel_lvds_port_enabled(display, LVDS, &panel_pipe);
1880 }
1881
1882 val = intel_de_read(display, pp_reg);
1883 if (!(val & PANEL_POWER_ON) ||
1884 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1885 locked = false;
1886
1887 INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,
1888 "panel assertion failure, pipe %c regs locked\n",
1889 pipe_name(pipe));
1890 }
1891