1 /*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 */
13
14 #include "qemu/osdep.h"
15
16 #include "hw/virtio/virtio-gpu.h"
17 #include "migration/blocker.h"
18 #include "qapi/error.h"
19 #include "qemu/error-report.h"
20 #include "hw/display/edid.h"
21 #include "trace.h"
22
23 void
virtio_gpu_base_reset(VirtIOGPUBase * g)24 virtio_gpu_base_reset(VirtIOGPUBase *g)
25 {
26 int i;
27
28 g->enable = 0;
29
30 for (i = 0; i < g->conf.max_outputs; i++) {
31 g->scanout[i].resource_id = 0;
32 g->scanout[i].width = 0;
33 g->scanout[i].height = 0;
34 g->scanout[i].x = 0;
35 g->scanout[i].y = 0;
36 g->scanout[i].ds = NULL;
37 }
38 }
39
40 void
virtio_gpu_base_fill_display_info(VirtIOGPUBase * g,struct virtio_gpu_resp_display_info * dpy_info)41 virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
42 struct virtio_gpu_resp_display_info *dpy_info)
43 {
44 int i;
45
46 for (i = 0; i < g->conf.max_outputs; i++) {
47 if (g->enabled_output_bitmask & (1 << i)) {
48 dpy_info->pmodes[i].enabled = 1;
49 dpy_info->pmodes[i].r.width = cpu_to_le32(g->req_state[i].width);
50 dpy_info->pmodes[i].r.height = cpu_to_le32(g->req_state[i].height);
51 }
52 }
53 }
54
55 void
virtio_gpu_base_generate_edid(VirtIOGPUBase * g,int scanout,struct virtio_gpu_resp_edid * edid)56 virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout,
57 struct virtio_gpu_resp_edid *edid)
58 {
59 qemu_edid_info info = {
60 .width_mm = g->req_state[scanout].width_mm,
61 .height_mm = g->req_state[scanout].height_mm,
62 .prefx = g->req_state[scanout].width,
63 .prefy = g->req_state[scanout].height,
64 .refresh_rate = g->req_state[scanout].refresh_rate,
65 };
66
67 edid->size = cpu_to_le32(sizeof(edid->edid));
68 qemu_edid_generate(edid->edid, sizeof(edid->edid), &info);
69 }
70
virtio_gpu_invalidate_display(void * opaque)71 static void virtio_gpu_invalidate_display(void *opaque)
72 {
73 }
74
virtio_gpu_update_display(void * opaque)75 static void virtio_gpu_update_display(void *opaque)
76 {
77 }
78
virtio_gpu_text_update(void * opaque,console_ch_t * chardata)79 static void virtio_gpu_text_update(void *opaque, console_ch_t *chardata)
80 {
81 }
82
virtio_gpu_notify_event(VirtIOGPUBase * g,uint32_t event_type)83 static void virtio_gpu_notify_event(VirtIOGPUBase *g, uint32_t event_type)
84 {
85 g->virtio_config.events_read |= event_type;
86 virtio_notify_config(&g->parent_obj);
87 }
88
virtio_gpu_ui_info(void * opaque,uint32_t idx,QemuUIInfo * info)89 static void virtio_gpu_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
90 {
91 VirtIOGPUBase *g = opaque;
92
93 if (idx >= g->conf.max_outputs) {
94 return;
95 }
96
97 g->req_state[idx].x = info->xoff;
98 g->req_state[idx].y = info->yoff;
99 g->req_state[idx].refresh_rate = info->refresh_rate;
100 g->req_state[idx].width = info->width;
101 g->req_state[idx].height = info->height;
102 g->req_state[idx].width_mm = info->width_mm;
103 g->req_state[idx].height_mm = info->height_mm;
104
105 if (info->width && info->height) {
106 g->enabled_output_bitmask |= (1 << idx);
107 } else {
108 g->enabled_output_bitmask &= ~(1 << idx);
109 }
110
111 /* send event to guest */
112 virtio_gpu_notify_event(g, VIRTIO_GPU_EVENT_DISPLAY);
113 }
114
115 static void
virtio_gpu_gl_flushed(void * opaque)116 virtio_gpu_gl_flushed(void *opaque)
117 {
118 VirtIOGPUBase *g = opaque;
119 VirtIOGPUBaseClass *vgc = VIRTIO_GPU_BASE_GET_CLASS(g);
120
121 if (vgc->gl_flushed) {
122 vgc->gl_flushed(g);
123 }
124 }
125
126 static void
virtio_gpu_gl_block(void * opaque,bool block)127 virtio_gpu_gl_block(void *opaque, bool block)
128 {
129 VirtIOGPUBase *g = opaque;
130
131 if (block) {
132 g->renderer_blocked++;
133 } else {
134 g->renderer_blocked--;
135 }
136 assert(g->renderer_blocked >= 0);
137
138 if (!block && g->renderer_blocked == 0) {
139 virtio_gpu_gl_flushed(g);
140 }
141 }
142
143 static int
virtio_gpu_get_flags(void * opaque)144 virtio_gpu_get_flags(void *opaque)
145 {
146 VirtIOGPUBase *g = opaque;
147 int flags = GRAPHIC_FLAGS_NONE;
148
149 if (virtio_gpu_virgl_enabled(g->conf)) {
150 flags |= GRAPHIC_FLAGS_GL;
151 }
152
153 if (virtio_gpu_dmabuf_enabled(g->conf)) {
154 flags |= GRAPHIC_FLAGS_DMABUF;
155 }
156
157 return flags;
158 }
159
160 static const GraphicHwOps virtio_gpu_ops = {
161 .get_flags = virtio_gpu_get_flags,
162 .invalidate = virtio_gpu_invalidate_display,
163 .gfx_update = virtio_gpu_update_display,
164 .text_update = virtio_gpu_text_update,
165 .ui_info = virtio_gpu_ui_info,
166 .gl_block = virtio_gpu_gl_block,
167 };
168
169 bool
virtio_gpu_base_device_realize(DeviceState * qdev,VirtIOHandleOutput ctrl_cb,VirtIOHandleOutput cursor_cb,Error ** errp)170 virtio_gpu_base_device_realize(DeviceState *qdev,
171 VirtIOHandleOutput ctrl_cb,
172 VirtIOHandleOutput cursor_cb,
173 Error **errp)
174 {
175 VirtIODevice *vdev = VIRTIO_DEVICE(qdev);
176 VirtIOGPUBase *g = VIRTIO_GPU_BASE(qdev);
177 int i;
178
179 if (g->conf.max_outputs > VIRTIO_GPU_MAX_SCANOUTS) {
180 error_setg(errp, "invalid max_outputs > %d", VIRTIO_GPU_MAX_SCANOUTS);
181 return false;
182 }
183
184 if (virtio_gpu_virgl_enabled(g->conf)) {
185 error_setg(&g->migration_blocker, "virgl is not yet migratable");
186 if (migrate_add_blocker(&g->migration_blocker, errp) < 0) {
187 return false;
188 }
189 }
190
191 g->virtio_config.num_scanouts = cpu_to_le32(g->conf.max_outputs);
192 virtio_init(VIRTIO_DEVICE(g), VIRTIO_ID_GPU,
193 sizeof(struct virtio_gpu_config));
194
195 if (virtio_gpu_virgl_enabled(g->conf)) {
196 /* use larger control queue in 3d mode */
197 virtio_add_queue(vdev, 256, ctrl_cb);
198 virtio_add_queue(vdev, 16, cursor_cb);
199 } else {
200 virtio_add_queue(vdev, 64, ctrl_cb);
201 virtio_add_queue(vdev, 16, cursor_cb);
202 }
203
204 g->enabled_output_bitmask = 1;
205
206 g->req_state[0].width = g->conf.xres;
207 g->req_state[0].height = g->conf.yres;
208
209 g->hw_ops = &virtio_gpu_ops;
210 for (i = 0; i < g->conf.max_outputs; i++) {
211 g->scanout[i].con =
212 graphic_console_init(DEVICE(g), i, &virtio_gpu_ops, g);
213 }
214
215 return true;
216 }
217
218 static uint64_t
virtio_gpu_base_get_features(VirtIODevice * vdev,uint64_t features,Error ** errp)219 virtio_gpu_base_get_features(VirtIODevice *vdev, uint64_t features,
220 Error **errp)
221 {
222 VirtIOGPUBase *g = VIRTIO_GPU_BASE(vdev);
223
224 if (virtio_gpu_virgl_enabled(g->conf) ||
225 virtio_gpu_rutabaga_enabled(g->conf)) {
226 features |= (1 << VIRTIO_GPU_F_VIRGL);
227 }
228 if (virtio_gpu_edid_enabled(g->conf)) {
229 features |= (1 << VIRTIO_GPU_F_EDID);
230 }
231 if (virtio_gpu_blob_enabled(g->conf)) {
232 features |= (1 << VIRTIO_GPU_F_RESOURCE_BLOB);
233 }
234 if (virtio_gpu_context_init_enabled(g->conf)) {
235 features |= (1 << VIRTIO_GPU_F_CONTEXT_INIT);
236 }
237 if (virtio_gpu_resource_uuid_enabled(g->conf)) {
238 features |= (1 << VIRTIO_GPU_F_RESOURCE_UUID);
239 }
240
241 return features;
242 }
243
244 static void
virtio_gpu_base_set_features(VirtIODevice * vdev,uint64_t features)245 virtio_gpu_base_set_features(VirtIODevice *vdev, uint64_t features)
246 {
247 static const uint32_t virgl = (1 << VIRTIO_GPU_F_VIRGL);
248
249 trace_virtio_gpu_features(((features & virgl) == virgl));
250 }
251
252 void
virtio_gpu_base_device_unrealize(DeviceState * qdev)253 virtio_gpu_base_device_unrealize(DeviceState *qdev)
254 {
255 VirtIOGPUBase *g = VIRTIO_GPU_BASE(qdev);
256 VirtIODevice *vdev = VIRTIO_DEVICE(qdev);
257
258 virtio_del_queue(vdev, 0);
259 virtio_del_queue(vdev, 1);
260 virtio_cleanup(vdev);
261 migrate_del_blocker(&g->migration_blocker);
262 }
263
264 static void
virtio_gpu_base_class_init(ObjectClass * klass,const void * data)265 virtio_gpu_base_class_init(ObjectClass *klass, const void *data)
266 {
267 DeviceClass *dc = DEVICE_CLASS(klass);
268 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
269
270 vdc->unrealize = virtio_gpu_base_device_unrealize;
271 vdc->get_features = virtio_gpu_base_get_features;
272 vdc->set_features = virtio_gpu_base_set_features;
273
274 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
275 dc->hotpluggable = false;
276 }
277
278 static const TypeInfo virtio_gpu_base_info = {
279 .name = TYPE_VIRTIO_GPU_BASE,
280 .parent = TYPE_VIRTIO_DEVICE,
281 .instance_size = sizeof(VirtIOGPUBase),
282 .class_size = sizeof(VirtIOGPUBaseClass),
283 .class_init = virtio_gpu_base_class_init,
284 .abstract = true
285 };
286 module_obj(TYPE_VIRTIO_GPU_BASE);
287 module_kconfig(VIRTIO_GPU);
288
289 static void
virtio_register_types(void)290 virtio_register_types(void)
291 {
292 type_register_static(&virtio_gpu_base_info);
293 }
294
295 type_init(virtio_register_types)
296
297 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctrl_hdr) != 24);
298 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_update_cursor) != 56);
299 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_unref) != 32);
300 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_2d) != 40);
301 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_set_scanout) != 48);
302 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_flush) != 48);
303 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_to_host_2d) != 56);
304 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_mem_entry) != 16);
305 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_attach_backing) != 32);
306 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_detach_backing) != 32);
307 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_display_info) != 408);
308
309 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_host_3d) != 72);
310 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_3d) != 72);
311 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_create) != 96);
312 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_destroy) != 24);
313 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_resource) != 32);
314 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_cmd_submit) != 32);
315 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset_info) != 32);
316 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset_info) != 40);
317 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset) != 32);
318 QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset) != 24);
319