1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DSI_PHY_H__ 7 #define __DSI_PHY_H__ 8 9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/regulator/consumer.h> 13 14 #include "dsi.h" 15 16 struct msm_dsi_phy_ops { 17 int (*pll_init)(struct msm_dsi_phy *phy); 18 int (*enable)(struct msm_dsi_phy *phy, 19 struct msm_dsi_phy_clk_request *clk_req); 20 void (*disable)(struct msm_dsi_phy *phy); 21 void (*save_pll_state)(struct msm_dsi_phy *phy); 22 int (*restore_pll_state)(struct msm_dsi_phy *phy); 23 bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable); 24 int (*parse_dt_properties)(struct msm_dsi_phy *phy); 25 }; 26 27 struct msm_dsi_phy_cfg { 28 const struct regulator_bulk_data *regulator_data; 29 int num_regulators; 30 struct msm_dsi_phy_ops ops; 31 32 unsigned long min_pll_rate; 33 unsigned long max_pll_rate; 34 35 const resource_size_t io_start[DSI_MAX]; 36 const int num_dsi_phy; 37 const int quirks; 38 bool has_phy_regulator; 39 bool has_phy_lane; 40 }; 41 42 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; 43 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; 44 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; 45 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; 46 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs; 47 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; 48 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; 49 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; 50 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs; 51 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; 52 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; 53 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; 54 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; 55 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; 56 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; 57 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs; 58 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; 59 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; 60 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; 61 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; 62 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; 63 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; 64 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; 65 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; 66 extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; 67 68 struct msm_dsi_dphy_timing { 69 u32 clk_zero; 70 u32 clk_trail; 71 u32 clk_prepare; 72 u32 hs_exit; 73 u32 hs_zero; 74 u32 hs_prepare; 75 u32 hs_trail; 76 u32 hs_rqst; 77 u32 ta_go; 78 u32 ta_sure; 79 u32 ta_get; 80 81 struct msm_dsi_phy_shared_timings shared_timings; 82 83 /* For PHY v2 only */ 84 u32 hs_rqst_ckln; 85 u32 hs_prep_dly; 86 u32 hs_prep_dly_ckln; 87 u8 hs_halfbyte_en; 88 u8 hs_halfbyte_en_ckln; 89 }; 90 91 #define NUM_PROVIDED_CLKS (DSI_PIXEL_PLL_CLK + 1) 92 93 #define DSI_LANE_MAX 5 94 95 struct msm_dsi_phy { 96 struct platform_device *pdev; 97 void __iomem *base; 98 void __iomem *pll_base; 99 void __iomem *reg_base; 100 void __iomem *lane_base; 101 phys_addr_t base_size; 102 phys_addr_t pll_size; 103 phys_addr_t reg_size; 104 phys_addr_t lane_size; 105 int id; 106 107 struct clk *ahb_clk; 108 struct regulator_bulk_data *supplies; 109 110 struct msm_dsi_dphy_timing timing; 111 const struct msm_dsi_phy_cfg *cfg; 112 void *tuning_cfg; 113 114 enum msm_dsi_phy_usecase usecase; 115 bool regulator_ldo_mode; 116 bool cphy_mode; 117 118 struct clk_hw *vco_hw; 119 bool pll_on; 120 121 struct clk_hw_onecell_data *provided_clocks; 122 123 bool state_saved; 124 }; 125 126 /* 127 * PHY internal functions 128 */ 129 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 130 struct msm_dsi_phy_clk_request *clk_req); 131 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 132 struct msm_dsi_phy_clk_request *clk_req); 133 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 134 struct msm_dsi_phy_clk_request *clk_req); 135 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 136 struct msm_dsi_phy_clk_request *clk_req); 137 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 138 struct msm_dsi_phy_clk_request *clk_req); 139 140 #endif /* __DSI_PHY_H__ */ 141