1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_vcn.h"
28 #include "amdgpu_pm.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "soc15_common.h"
32
33 #include "vcn/vcn_1_0_offset.h"
34 #include "vcn/vcn_1_0_sh_mask.h"
35 #include "hdp/hdp_4_0_offset.h"
36 #include "mmhub/mmhub_9_1_offset.h"
37 #include "mmhub/mmhub_9_1_sh_mask.h"
38
39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
40 #include "jpeg_v1_0.h"
41 #include "vcn_v1_0.h"
42
43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab
44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1
45 #define mmUVD_REG_XX_MASK_1_0 0x05ac
46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1
47
48 static int vcn_v1_0_stop(struct amdgpu_device *adev);
49 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
50 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
51 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
52 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
53 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
54 int inst_idx, struct dpg_pause_state *new_state);
55
56 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
57 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
58
59 /**
60 * vcn_v1_0_early_init - set function pointers
61 *
62 * @handle: amdgpu_device pointer
63 *
64 * Set ring and irq function pointers
65 */
vcn_v1_0_early_init(void * handle)66 static int vcn_v1_0_early_init(void *handle)
67 {
68 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
69
70 adev->vcn.num_vcn_inst = 1;
71 adev->vcn.num_enc_rings = 2;
72
73 vcn_v1_0_set_dec_ring_funcs(adev);
74 vcn_v1_0_set_enc_ring_funcs(adev);
75 vcn_v1_0_set_irq_funcs(adev);
76
77 jpeg_v1_0_early_init(handle);
78
79 return 0;
80 }
81
82 /**
83 * vcn_v1_0_sw_init - sw init for VCN block
84 *
85 * @handle: amdgpu_device pointer
86 *
87 * Load firmware and sw initialization
88 */
vcn_v1_0_sw_init(void * handle)89 static int vcn_v1_0_sw_init(void *handle)
90 {
91 struct amdgpu_ring *ring;
92 int i, r;
93 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
94
95 /* VCN DEC TRAP */
96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
97 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
98 if (r)
99 return r;
100
101 /* VCN ENC TRAP */
102 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
104 &adev->vcn.inst->irq);
105 if (r)
106 return r;
107 }
108
109 r = amdgpu_vcn_sw_init(adev);
110 if (r)
111 return r;
112
113 /* Override the work func */
114 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
115
116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
117 const struct common_firmware_header *hdr;
118 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
119 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
120 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
121 adev->firmware.fw_size +=
122 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
123 DRM_INFO("PSP loading VCN firmware\n");
124 }
125
126 r = amdgpu_vcn_resume(adev);
127 if (r)
128 return r;
129
130 ring = &adev->vcn.inst->ring_dec;
131 sprintf(ring->name, "vcn_dec");
132 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
133 AMDGPU_RING_PRIO_DEFAULT);
134 if (r)
135 return r;
136
137 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
138 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
139 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
140 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
141 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
142 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
143 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
144 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
145 adev->vcn.internal.nop = adev->vcn.inst->external.nop =
146 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
147
148 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
149 ring = &adev->vcn.inst->ring_enc[i];
150 sprintf(ring->name, "vcn_enc%d", i);
151 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
152 AMDGPU_RING_PRIO_DEFAULT);
153 if (r)
154 return r;
155 }
156
157 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
158
159 r = jpeg_v1_0_sw_init(handle);
160
161 return r;
162 }
163
164 /**
165 * vcn_v1_0_sw_fini - sw fini for VCN block
166 *
167 * @handle: amdgpu_device pointer
168 *
169 * VCN suspend and free up sw allocation
170 */
vcn_v1_0_sw_fini(void * handle)171 static int vcn_v1_0_sw_fini(void *handle)
172 {
173 int r;
174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175
176 r = amdgpu_vcn_suspend(adev);
177 if (r)
178 return r;
179
180 jpeg_v1_0_sw_fini(handle);
181
182 r = amdgpu_vcn_sw_fini(adev);
183
184 return r;
185 }
186
187 /**
188 * vcn_v1_0_hw_init - start and test VCN block
189 *
190 * @handle: amdgpu_device pointer
191 *
192 * Initialize the hardware, boot up the VCPU and do some testing
193 */
vcn_v1_0_hw_init(void * handle)194 static int vcn_v1_0_hw_init(void *handle)
195 {
196 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
198 int i, r;
199
200 r = amdgpu_ring_test_helper(ring);
201 if (r)
202 goto done;
203
204 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
205 ring = &adev->vcn.inst->ring_enc[i];
206 r = amdgpu_ring_test_helper(ring);
207 if (r)
208 goto done;
209 }
210
211 ring = &adev->jpeg.inst->ring_dec;
212 r = amdgpu_ring_test_helper(ring);
213 if (r)
214 goto done;
215
216 done:
217 if (!r)
218 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
219 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
220
221 return r;
222 }
223
224 /**
225 * vcn_v1_0_hw_fini - stop the hardware block
226 *
227 * @handle: amdgpu_device pointer
228 *
229 * Stop the VCN block, mark ring as not ready any more
230 */
vcn_v1_0_hw_fini(void * handle)231 static int vcn_v1_0_hw_fini(void *handle)
232 {
233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234
235 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
236 RREG32_SOC15(VCN, 0, mmUVD_STATUS))
237 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
238
239 return 0;
240 }
241
242 /**
243 * vcn_v1_0_suspend - suspend VCN block
244 *
245 * @handle: amdgpu_device pointer
246 *
247 * HW fini and suspend VCN block
248 */
vcn_v1_0_suspend(void * handle)249 static int vcn_v1_0_suspend(void *handle)
250 {
251 int r;
252 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
253
254 r = vcn_v1_0_hw_fini(adev);
255 if (r)
256 return r;
257
258 r = amdgpu_vcn_suspend(adev);
259
260 return r;
261 }
262
263 /**
264 * vcn_v1_0_resume - resume VCN block
265 *
266 * @handle: amdgpu_device pointer
267 *
268 * Resume firmware and hw init VCN block
269 */
vcn_v1_0_resume(void * handle)270 static int vcn_v1_0_resume(void *handle)
271 {
272 int r;
273 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
274
275 r = amdgpu_vcn_resume(adev);
276 if (r)
277 return r;
278
279 r = vcn_v1_0_hw_init(adev);
280
281 return r;
282 }
283
284 /**
285 * vcn_v1_0_mc_resume_spg_mode - memory controller programming
286 *
287 * @adev: amdgpu_device pointer
288 *
289 * Let the VCN memory controller know it's offsets
290 */
vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device * adev)291 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
292 {
293 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
294 uint32_t offset;
295
296 /* cache window 0: fw */
297 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
298 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
299 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
300 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
301 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
302 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
303 offset = 0;
304 } else {
305 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
306 lower_32_bits(adev->vcn.inst->gpu_addr));
307 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
308 upper_32_bits(adev->vcn.inst->gpu_addr));
309 offset = size;
310 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
311 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
312 }
313
314 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
315
316 /* cache window 1: stack */
317 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
318 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
319 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
320 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
321 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
322 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
323
324 /* cache window 2: context */
325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
326 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
327 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
328 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
329 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
330 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
331
332 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
333 adev->gfx.config.gb_addr_config);
334 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
335 adev->gfx.config.gb_addr_config);
336 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
337 adev->gfx.config.gb_addr_config);
338 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
339 adev->gfx.config.gb_addr_config);
340 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
341 adev->gfx.config.gb_addr_config);
342 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
343 adev->gfx.config.gb_addr_config);
344 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
345 adev->gfx.config.gb_addr_config);
346 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
347 adev->gfx.config.gb_addr_config);
348 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
349 adev->gfx.config.gb_addr_config);
350 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
351 adev->gfx.config.gb_addr_config);
352 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
353 adev->gfx.config.gb_addr_config);
354 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
355 adev->gfx.config.gb_addr_config);
356 }
357
vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device * adev)358 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
359 {
360 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
361 uint32_t offset;
362
363 /* cache window 0: fw */
364 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
365 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
366 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
367 0xFFFFFFFF, 0);
368 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
369 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
370 0xFFFFFFFF, 0);
371 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
372 0xFFFFFFFF, 0);
373 offset = 0;
374 } else {
375 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
376 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
377 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
378 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
379 offset = size;
380 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
381 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
382 }
383
384 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
385
386 /* cache window 1: stack */
387 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
388 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
389 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
390 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
391 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
392 0xFFFFFFFF, 0);
393 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
394 0xFFFFFFFF, 0);
395
396 /* cache window 2: context */
397 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
398 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
399 0xFFFFFFFF, 0);
400 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
401 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
402 0xFFFFFFFF, 0);
403 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
404 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
405 0xFFFFFFFF, 0);
406
407 /* VCN global tiling registers */
408 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
409 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
410 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
411 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
412 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
413 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
414 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
415 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
416 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
417 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
418 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
419 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
420 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
421 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
422 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
423 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
424 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
425 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
426 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
427 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
428 }
429
430 /**
431 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
432 *
433 * @adev: amdgpu_device pointer
434 * @sw: enable SW clock gating
435 *
436 * Disable clock gating for VCN block
437 */
vcn_v1_0_disable_clock_gating(struct amdgpu_device * adev)438 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
439 {
440 uint32_t data;
441
442 /* JPEG disable CGC */
443 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
444
445 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
446 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
447 else
448 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
449
450 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
451 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
452 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
453
454 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
455 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
456 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
457
458 /* UVD disable CGC */
459 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
460 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
461 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
462 else
463 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
464
465 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
466 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
467 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
468
469 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
470 data &= ~(UVD_CGC_GATE__SYS_MASK
471 | UVD_CGC_GATE__UDEC_MASK
472 | UVD_CGC_GATE__MPEG2_MASK
473 | UVD_CGC_GATE__REGS_MASK
474 | UVD_CGC_GATE__RBC_MASK
475 | UVD_CGC_GATE__LMI_MC_MASK
476 | UVD_CGC_GATE__LMI_UMC_MASK
477 | UVD_CGC_GATE__IDCT_MASK
478 | UVD_CGC_GATE__MPRD_MASK
479 | UVD_CGC_GATE__MPC_MASK
480 | UVD_CGC_GATE__LBSI_MASK
481 | UVD_CGC_GATE__LRBBM_MASK
482 | UVD_CGC_GATE__UDEC_RE_MASK
483 | UVD_CGC_GATE__UDEC_CM_MASK
484 | UVD_CGC_GATE__UDEC_IT_MASK
485 | UVD_CGC_GATE__UDEC_DB_MASK
486 | UVD_CGC_GATE__UDEC_MP_MASK
487 | UVD_CGC_GATE__WCB_MASK
488 | UVD_CGC_GATE__VCPU_MASK
489 | UVD_CGC_GATE__SCPU_MASK);
490 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
491
492 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
493 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
494 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
495 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
496 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
497 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
498 | UVD_CGC_CTRL__SYS_MODE_MASK
499 | UVD_CGC_CTRL__UDEC_MODE_MASK
500 | UVD_CGC_CTRL__MPEG2_MODE_MASK
501 | UVD_CGC_CTRL__REGS_MODE_MASK
502 | UVD_CGC_CTRL__RBC_MODE_MASK
503 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
504 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
505 | UVD_CGC_CTRL__IDCT_MODE_MASK
506 | UVD_CGC_CTRL__MPRD_MODE_MASK
507 | UVD_CGC_CTRL__MPC_MODE_MASK
508 | UVD_CGC_CTRL__LBSI_MODE_MASK
509 | UVD_CGC_CTRL__LRBBM_MODE_MASK
510 | UVD_CGC_CTRL__WCB_MODE_MASK
511 | UVD_CGC_CTRL__VCPU_MODE_MASK
512 | UVD_CGC_CTRL__SCPU_MODE_MASK);
513 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
514
515 /* turn on */
516 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
517 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
518 | UVD_SUVD_CGC_GATE__SIT_MASK
519 | UVD_SUVD_CGC_GATE__SMP_MASK
520 | UVD_SUVD_CGC_GATE__SCM_MASK
521 | UVD_SUVD_CGC_GATE__SDB_MASK
522 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
523 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
524 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
525 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
526 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
527 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
528 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
529 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
530 | UVD_SUVD_CGC_GATE__SCLR_MASK
531 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
532 | UVD_SUVD_CGC_GATE__ENT_MASK
533 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
534 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
535 | UVD_SUVD_CGC_GATE__SITE_MASK
536 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
537 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
538 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
539 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
540 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
541 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
542
543 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
544 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
545 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
546 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
547 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
548 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
549 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
550 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
551 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
552 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
553 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
554 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
555 }
556
557 /**
558 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
559 *
560 * @adev: amdgpu_device pointer
561 * @sw: enable SW clock gating
562 *
563 * Enable clock gating for VCN block
564 */
vcn_v1_0_enable_clock_gating(struct amdgpu_device * adev)565 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
566 {
567 uint32_t data = 0;
568
569 /* enable JPEG CGC */
570 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
571 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
572 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
573 else
574 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
575 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
576 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
577 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
578
579 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
580 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
581 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
582
583 /* enable UVD CGC */
584 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
585 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
586 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
587 else
588 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
589 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
590 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
591 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
592
593 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
594 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
595 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
596 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
597 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
598 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
599 | UVD_CGC_CTRL__SYS_MODE_MASK
600 | UVD_CGC_CTRL__UDEC_MODE_MASK
601 | UVD_CGC_CTRL__MPEG2_MODE_MASK
602 | UVD_CGC_CTRL__REGS_MODE_MASK
603 | UVD_CGC_CTRL__RBC_MODE_MASK
604 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
605 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
606 | UVD_CGC_CTRL__IDCT_MODE_MASK
607 | UVD_CGC_CTRL__MPRD_MODE_MASK
608 | UVD_CGC_CTRL__MPC_MODE_MASK
609 | UVD_CGC_CTRL__LBSI_MODE_MASK
610 | UVD_CGC_CTRL__LRBBM_MODE_MASK
611 | UVD_CGC_CTRL__WCB_MODE_MASK
612 | UVD_CGC_CTRL__VCPU_MODE_MASK
613 | UVD_CGC_CTRL__SCPU_MODE_MASK);
614 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
615
616 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
617 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
618 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
619 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
620 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
621 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
622 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
623 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
624 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
625 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
626 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
627 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
628 }
629
vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel)630 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
631 {
632 uint32_t reg_data = 0;
633
634 /* disable JPEG CGC */
635 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
636 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
637 else
638 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
639 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
640 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
641 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
642
643 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
644
645 /* enable sw clock gating control */
646 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
647 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
648 else
649 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
650 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
651 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
652 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
653 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
654 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
655 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
656 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
657 UVD_CGC_CTRL__SYS_MODE_MASK |
658 UVD_CGC_CTRL__UDEC_MODE_MASK |
659 UVD_CGC_CTRL__MPEG2_MODE_MASK |
660 UVD_CGC_CTRL__REGS_MODE_MASK |
661 UVD_CGC_CTRL__RBC_MODE_MASK |
662 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
663 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
664 UVD_CGC_CTRL__IDCT_MODE_MASK |
665 UVD_CGC_CTRL__MPRD_MODE_MASK |
666 UVD_CGC_CTRL__MPC_MODE_MASK |
667 UVD_CGC_CTRL__LBSI_MODE_MASK |
668 UVD_CGC_CTRL__LRBBM_MODE_MASK |
669 UVD_CGC_CTRL__WCB_MODE_MASK |
670 UVD_CGC_CTRL__VCPU_MODE_MASK |
671 UVD_CGC_CTRL__SCPU_MODE_MASK);
672 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
673
674 /* turn off clock gating */
675 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
676
677 /* turn on SUVD clock gating */
678 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
679
680 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
681 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
682 }
683
vcn_1_0_disable_static_power_gating(struct amdgpu_device * adev)684 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
685 {
686 uint32_t data = 0;
687
688 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
689 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
690 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
691 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
692 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
693 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
694 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
695 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
696 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
697 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
698 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
699 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
700
701 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
702 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
703 } else {
704 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
705 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
706 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
707 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
708 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
709 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
710 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
711 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
712 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
713 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
714 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
715 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
716 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
717 }
718
719 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
720
721 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
722 data &= ~0x103;
723 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
724 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
725
726 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
727 }
728
vcn_1_0_enable_static_power_gating(struct amdgpu_device * adev)729 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
730 {
731 uint32_t data = 0;
732
733 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
734 /* Before power off, this indicator has to be turned on */
735 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
736 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
737 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
738 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
739
740
741 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
742 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
743 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
744 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
745 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
746 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
747 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
748 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
749 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
750 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
751 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
752
753 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
754
755 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
756 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
757 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
758 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
759 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
760 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
761 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
762 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
763 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
764 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
765 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
766 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
767 }
768 }
769
770 /**
771 * vcn_v1_0_start - start VCN block
772 *
773 * @adev: amdgpu_device pointer
774 *
775 * Setup and start the VCN block
776 */
vcn_v1_0_start_spg_mode(struct amdgpu_device * adev)777 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
778 {
779 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
780 uint32_t rb_bufsz, tmp;
781 uint32_t lmi_swap_cntl;
782 int i, j, r;
783
784 /* disable byte swapping */
785 lmi_swap_cntl = 0;
786
787 vcn_1_0_disable_static_power_gating(adev);
788
789 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
790 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
791
792 /* disable clock gating */
793 vcn_v1_0_disable_clock_gating(adev);
794
795 /* disable interupt */
796 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
797 ~UVD_MASTINT_EN__VCPU_EN_MASK);
798
799 /* initialize VCN memory controller */
800 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
801 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
802 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
803 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
804 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
805 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
806
807 #ifdef __BIG_ENDIAN
808 /* swap (8 in 32) RB and IB */
809 lmi_swap_cntl = 0xa;
810 #endif
811 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
812
813 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
814 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
815 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
816 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
817
818 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
819 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
820 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
821 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
822 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
823
824 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
825 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
826 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
827 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
828 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
829
830 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
831 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
832 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
833 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
834
835 vcn_v1_0_mc_resume_spg_mode(adev);
836
837 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
838 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
839 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
840
841 /* enable VCPU clock */
842 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
843
844 /* boot up the VCPU */
845 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
846 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
847
848 /* enable UMC */
849 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
850 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
851
852 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
853 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
854 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
855 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
856
857 for (i = 0; i < 10; ++i) {
858 uint32_t status;
859
860 for (j = 0; j < 100; ++j) {
861 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
862 if (status & UVD_STATUS__IDLE)
863 break;
864 mdelay(10);
865 }
866 r = 0;
867 if (status & UVD_STATUS__IDLE)
868 break;
869
870 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
871 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
872 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
873 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
874 mdelay(10);
875 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
876 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
877 mdelay(10);
878 r = -1;
879 }
880
881 if (r) {
882 DRM_ERROR("VCN decode not responding, giving up!!!\n");
883 return r;
884 }
885 /* enable master interrupt */
886 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
887 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
888
889 /* enable system interrupt for JRBC, TODO: move to set interrupt*/
890 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
891 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
892 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
893
894 /* clear the busy bit of UVD_STATUS */
895 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
896 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
897
898 /* force RBC into idle state */
899 rb_bufsz = order_base_2(ring->ring_size);
900 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
901 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
902 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
903 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
904 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
905 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
906
907 /* set the write pointer delay */
908 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
909
910 /* set the wb address */
911 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
912 (upper_32_bits(ring->gpu_addr) >> 2));
913
914 /* program the RB_BASE for ring buffer */
915 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
916 lower_32_bits(ring->gpu_addr));
917 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
918 upper_32_bits(ring->gpu_addr));
919
920 /* Initialize the ring buffer's read and write pointers */
921 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
922
923 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
924
925 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
926 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
927 lower_32_bits(ring->wptr));
928
929 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
930 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
931
932 ring = &adev->vcn.inst->ring_enc[0];
933 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
934 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
935 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
936 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
937 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
938
939 ring = &adev->vcn.inst->ring_enc[1];
940 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
941 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
942 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
943 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
944 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
945
946 jpeg_v1_0_start(adev, 0);
947
948 return 0;
949 }
950
vcn_v1_0_start_dpg_mode(struct amdgpu_device * adev)951 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
952 {
953 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
954 uint32_t rb_bufsz, tmp;
955 uint32_t lmi_swap_cntl;
956
957 /* disable byte swapping */
958 lmi_swap_cntl = 0;
959
960 vcn_1_0_enable_static_power_gating(adev);
961
962 /* enable dynamic power gating mode */
963 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
964 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
965 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
966 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
967
968 /* enable clock gating */
969 vcn_v1_0_clock_gating_dpg_mode(adev, 0);
970
971 /* enable VCPU clock */
972 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
973 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
974 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
975 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
976
977 /* disable interupt */
978 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
979 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
980
981 /* initialize VCN memory controller */
982 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
983 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
984 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
985 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
986 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
987 UVD_LMI_CTRL__REQ_MODE_MASK |
988 UVD_LMI_CTRL__CRC_RESET_MASK |
989 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
990 0x00100000L, 0xFFFFFFFF, 0);
991
992 #ifdef __BIG_ENDIAN
993 /* swap (8 in 32) RB and IB */
994 lmi_swap_cntl = 0xa;
995 #endif
996 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
997
998 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
999 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1000
1001 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1002 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1003 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1004 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1005 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1006
1007 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1008 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1009 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1010 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1011 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1012
1013 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1014 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1015 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1016 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1017
1018 vcn_v1_0_mc_resume_dpg_mode(adev);
1019
1020 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1021 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1022
1023 /* boot up the VCPU */
1024 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1025
1026 /* enable UMC */
1027 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1028 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1029 0xFFFFFFFF, 0);
1030
1031 /* enable master interrupt */
1032 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1033 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1034
1035 vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1036 /* setup mmUVD_LMI_CTRL */
1037 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1038 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1039 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1040 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1041 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1042 UVD_LMI_CTRL__REQ_MODE_MASK |
1043 UVD_LMI_CTRL__CRC_RESET_MASK |
1044 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1045 0x00100000L, 0xFFFFFFFF, 1);
1046
1047 tmp = adev->gfx.config.gb_addr_config;
1048 /* setup VCN global tiling registers */
1049 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1050 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1051
1052 /* enable System Interrupt for JRBC */
1053 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1054 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1055
1056 /* force RBC into idle state */
1057 rb_bufsz = order_base_2(ring->ring_size);
1058 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1063 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1064
1065 /* set the write pointer delay */
1066 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1067
1068 /* set the wb address */
1069 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1070 (upper_32_bits(ring->gpu_addr) >> 2));
1071
1072 /* program the RB_BASE for ring buffer */
1073 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1074 lower_32_bits(ring->gpu_addr));
1075 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1076 upper_32_bits(ring->gpu_addr));
1077
1078 /* Initialize the ring buffer's read and write pointers */
1079 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1080
1081 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1082
1083 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1084 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1085 lower_32_bits(ring->wptr));
1086
1087 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1088 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1089
1090 jpeg_v1_0_start(adev, 1);
1091
1092 return 0;
1093 }
1094
vcn_v1_0_start(struct amdgpu_device * adev)1095 static int vcn_v1_0_start(struct amdgpu_device *adev)
1096 {
1097 int r;
1098
1099 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1100 r = vcn_v1_0_start_dpg_mode(adev);
1101 else
1102 r = vcn_v1_0_start_spg_mode(adev);
1103 return r;
1104 }
1105
1106 /**
1107 * vcn_v1_0_stop - stop VCN block
1108 *
1109 * @adev: amdgpu_device pointer
1110 *
1111 * stop the VCN block
1112 */
vcn_v1_0_stop_spg_mode(struct amdgpu_device * adev)1113 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1114 {
1115 int tmp;
1116
1117 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1118
1119 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1120 UVD_LMI_STATUS__READ_CLEAN_MASK |
1121 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1122 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1123 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1124
1125 /* put VCPU into reset */
1126 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1127 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1128 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1129
1130 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1131 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1132 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1133
1134 /* disable VCPU clock */
1135 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1136 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1137
1138 /* reset LMI UMC/LMI */
1139 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1140 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1141 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1142
1143 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1144 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1145 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1146
1147 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1148
1149 vcn_v1_0_enable_clock_gating(adev);
1150 vcn_1_0_enable_static_power_gating(adev);
1151 return 0;
1152 }
1153
vcn_v1_0_stop_dpg_mode(struct amdgpu_device * adev)1154 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1155 {
1156 uint32_t tmp;
1157
1158 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1159 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1160 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1161 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1162
1163 /* wait for read ptr to be equal to write ptr */
1164 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1166
1167 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1168 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1169
1170 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1172
1173 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1175
1176 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1177 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1178 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1179
1180 /* disable dynamic power gating mode */
1181 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1182 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1183
1184 return 0;
1185 }
1186
vcn_v1_0_stop(struct amdgpu_device * adev)1187 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1188 {
1189 int r;
1190
1191 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1192 r = vcn_v1_0_stop_dpg_mode(adev);
1193 else
1194 r = vcn_v1_0_stop_spg_mode(adev);
1195
1196 return r;
1197 }
1198
vcn_v1_0_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1199 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1200 int inst_idx, struct dpg_pause_state *new_state)
1201 {
1202 int ret_code;
1203 uint32_t reg_data = 0;
1204 uint32_t reg_data2 = 0;
1205 struct amdgpu_ring *ring;
1206
1207 /* pause/unpause if state is changed */
1208 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1209 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1210 adev->vcn.inst[inst_idx].pause_state.fw_based,
1211 adev->vcn.inst[inst_idx].pause_state.jpeg,
1212 new_state->fw_based, new_state->jpeg);
1213
1214 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1215 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1216
1217 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1218 ret_code = 0;
1219
1220 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1221 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1222 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1223 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1224
1225 if (!ret_code) {
1226 /* pause DPG non-jpeg */
1227 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1228 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1229 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1230 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1231 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1232
1233 /* Restore */
1234 ring = &adev->vcn.inst->ring_enc[0];
1235 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1236 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1238 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1239 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1240
1241 ring = &adev->vcn.inst->ring_enc[1];
1242 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1243 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1244 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1245 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1246 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1247
1248 ring = &adev->vcn.inst->ring_dec;
1249 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1250 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1251 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1252 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1253 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1254 }
1255 } else {
1256 /* unpause dpg non-jpeg, no need to wait */
1257 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1258 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1259 }
1260 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1261 }
1262
1263 /* pause/unpause if state is changed */
1264 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1265 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1266 adev->vcn.inst[inst_idx].pause_state.fw_based,
1267 adev->vcn.inst[inst_idx].pause_state.jpeg,
1268 new_state->fw_based, new_state->jpeg);
1269
1270 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1271 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1272
1273 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1274 ret_code = 0;
1275
1276 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1277 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1278 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1279 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1280
1281 if (!ret_code) {
1282 /* Make sure JPRG Snoop is disabled before sending the pause */
1283 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1284 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1285 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1286
1287 /* pause DPG jpeg */
1288 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1289 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1290 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1291 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1292 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1293
1294 /* Restore */
1295 ring = &adev->jpeg.inst->ring_dec;
1296 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1297 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1298 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1299 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1300 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1301 lower_32_bits(ring->gpu_addr));
1302 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1303 upper_32_bits(ring->gpu_addr));
1304 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1305 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1306 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1307 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1308
1309 ring = &adev->vcn.inst->ring_dec;
1310 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1311 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1312 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1313 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1314 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1315 }
1316 } else {
1317 /* unpause dpg jpeg, no need to wait */
1318 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1319 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1320 }
1321 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1322 }
1323
1324 return 0;
1325 }
1326
vcn_v1_0_is_idle(void * handle)1327 static bool vcn_v1_0_is_idle(void *handle)
1328 {
1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330
1331 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1332 }
1333
vcn_v1_0_wait_for_idle(void * handle)1334 static int vcn_v1_0_wait_for_idle(void *handle)
1335 {
1336 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1337 int ret;
1338
1339 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1340 UVD_STATUS__IDLE);
1341
1342 return ret;
1343 }
1344
vcn_v1_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1345 static int vcn_v1_0_set_clockgating_state(void *handle,
1346 enum amd_clockgating_state state)
1347 {
1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349 bool enable = (state == AMD_CG_STATE_GATE);
1350
1351 if (enable) {
1352 /* wait for STATUS to clear */
1353 if (!vcn_v1_0_is_idle(handle))
1354 return -EBUSY;
1355 vcn_v1_0_enable_clock_gating(adev);
1356 } else {
1357 /* disable HW gating and enable Sw gating */
1358 vcn_v1_0_disable_clock_gating(adev);
1359 }
1360 return 0;
1361 }
1362
1363 /**
1364 * vcn_v1_0_dec_ring_get_rptr - get read pointer
1365 *
1366 * @ring: amdgpu_ring pointer
1367 *
1368 * Returns the current hardware read pointer
1369 */
vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1370 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1371 {
1372 struct amdgpu_device *adev = ring->adev;
1373
1374 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1375 }
1376
1377 /**
1378 * vcn_v1_0_dec_ring_get_wptr - get write pointer
1379 *
1380 * @ring: amdgpu_ring pointer
1381 *
1382 * Returns the current hardware write pointer
1383 */
vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1384 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1385 {
1386 struct amdgpu_device *adev = ring->adev;
1387
1388 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1389 }
1390
1391 /**
1392 * vcn_v1_0_dec_ring_set_wptr - set write pointer
1393 *
1394 * @ring: amdgpu_ring pointer
1395 *
1396 * Commits the write pointer to the hardware
1397 */
vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1398 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1399 {
1400 struct amdgpu_device *adev = ring->adev;
1401
1402 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1403 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1404 lower_32_bits(ring->wptr) | 0x80000000);
1405
1406 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1407 }
1408
1409 /**
1410 * vcn_v1_0_dec_ring_insert_start - insert a start command
1411 *
1412 * @ring: amdgpu_ring pointer
1413 *
1414 * Write a start command to the ring.
1415 */
vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring * ring)1416 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1417 {
1418 struct amdgpu_device *adev = ring->adev;
1419
1420 amdgpu_ring_write(ring,
1421 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1422 amdgpu_ring_write(ring, 0);
1423 amdgpu_ring_write(ring,
1424 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1425 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1426 }
1427
1428 /**
1429 * vcn_v1_0_dec_ring_insert_end - insert a end command
1430 *
1431 * @ring: amdgpu_ring pointer
1432 *
1433 * Write a end command to the ring.
1434 */
vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring * ring)1435 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1436 {
1437 struct amdgpu_device *adev = ring->adev;
1438
1439 amdgpu_ring_write(ring,
1440 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1441 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1442 }
1443
1444 /**
1445 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1446 *
1447 * @ring: amdgpu_ring pointer
1448 * @fence: fence to emit
1449 *
1450 * Write a fence and a trap command to the ring.
1451 */
vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1452 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1453 unsigned flags)
1454 {
1455 struct amdgpu_device *adev = ring->adev;
1456
1457 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1458
1459 amdgpu_ring_write(ring,
1460 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1461 amdgpu_ring_write(ring, seq);
1462 amdgpu_ring_write(ring,
1463 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1464 amdgpu_ring_write(ring, addr & 0xffffffff);
1465 amdgpu_ring_write(ring,
1466 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1467 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1468 amdgpu_ring_write(ring,
1469 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1470 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1471
1472 amdgpu_ring_write(ring,
1473 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1474 amdgpu_ring_write(ring, 0);
1475 amdgpu_ring_write(ring,
1476 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1477 amdgpu_ring_write(ring, 0);
1478 amdgpu_ring_write(ring,
1479 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1480 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1481 }
1482
1483 /**
1484 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1485 *
1486 * @ring: amdgpu_ring pointer
1487 * @ib: indirect buffer to execute
1488 *
1489 * Write ring commands to execute the indirect buffer
1490 */
vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1491 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1492 struct amdgpu_job *job,
1493 struct amdgpu_ib *ib,
1494 uint32_t flags)
1495 {
1496 struct amdgpu_device *adev = ring->adev;
1497 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1498
1499 amdgpu_ring_write(ring,
1500 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1501 amdgpu_ring_write(ring, vmid);
1502
1503 amdgpu_ring_write(ring,
1504 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1505 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1506 amdgpu_ring_write(ring,
1507 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1508 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1509 amdgpu_ring_write(ring,
1510 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1511 amdgpu_ring_write(ring, ib->length_dw);
1512 }
1513
vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1514 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1515 uint32_t reg, uint32_t val,
1516 uint32_t mask)
1517 {
1518 struct amdgpu_device *adev = ring->adev;
1519
1520 amdgpu_ring_write(ring,
1521 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1522 amdgpu_ring_write(ring, reg << 2);
1523 amdgpu_ring_write(ring,
1524 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1525 amdgpu_ring_write(ring, val);
1526 amdgpu_ring_write(ring,
1527 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1528 amdgpu_ring_write(ring, mask);
1529 amdgpu_ring_write(ring,
1530 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1531 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1532 }
1533
vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1534 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1535 unsigned vmid, uint64_t pd_addr)
1536 {
1537 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1538 uint32_t data0, data1, mask;
1539
1540 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1541
1542 /* wait for register write */
1543 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1544 data1 = lower_32_bits(pd_addr);
1545 mask = 0xffffffff;
1546 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1547 }
1548
vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1549 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1550 uint32_t reg, uint32_t val)
1551 {
1552 struct amdgpu_device *adev = ring->adev;
1553
1554 amdgpu_ring_write(ring,
1555 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1556 amdgpu_ring_write(ring, reg << 2);
1557 amdgpu_ring_write(ring,
1558 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1559 amdgpu_ring_write(ring, val);
1560 amdgpu_ring_write(ring,
1561 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1562 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1563 }
1564
1565 /**
1566 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1567 *
1568 * @ring: amdgpu_ring pointer
1569 *
1570 * Returns the current hardware enc read pointer
1571 */
vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1572 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1573 {
1574 struct amdgpu_device *adev = ring->adev;
1575
1576 if (ring == &adev->vcn.inst->ring_enc[0])
1577 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1578 else
1579 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1580 }
1581
1582 /**
1583 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1584 *
1585 * @ring: amdgpu_ring pointer
1586 *
1587 * Returns the current hardware enc write pointer
1588 */
vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1589 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1590 {
1591 struct amdgpu_device *adev = ring->adev;
1592
1593 if (ring == &adev->vcn.inst->ring_enc[0])
1594 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1595 else
1596 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1597 }
1598
1599 /**
1600 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1601 *
1602 * @ring: amdgpu_ring pointer
1603 *
1604 * Commits the enc write pointer to the hardware
1605 */
vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1606 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1607 {
1608 struct amdgpu_device *adev = ring->adev;
1609
1610 if (ring == &adev->vcn.inst->ring_enc[0])
1611 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1612 lower_32_bits(ring->wptr));
1613 else
1614 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1615 lower_32_bits(ring->wptr));
1616 }
1617
1618 /**
1619 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1620 *
1621 * @ring: amdgpu_ring pointer
1622 * @fence: fence to emit
1623 *
1624 * Write enc a fence and a trap command to the ring.
1625 */
vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1626 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1627 u64 seq, unsigned flags)
1628 {
1629 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1630
1631 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1632 amdgpu_ring_write(ring, addr);
1633 amdgpu_ring_write(ring, upper_32_bits(addr));
1634 amdgpu_ring_write(ring, seq);
1635 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1636 }
1637
vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring * ring)1638 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1639 {
1640 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1641 }
1642
1643 /**
1644 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1645 *
1646 * @ring: amdgpu_ring pointer
1647 * @ib: indirect buffer to execute
1648 *
1649 * Write enc ring commands to execute the indirect buffer
1650 */
vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1651 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1652 struct amdgpu_job *job,
1653 struct amdgpu_ib *ib,
1654 uint32_t flags)
1655 {
1656 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1657
1658 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1659 amdgpu_ring_write(ring, vmid);
1660 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1661 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1662 amdgpu_ring_write(ring, ib->length_dw);
1663 }
1664
vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1665 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1666 uint32_t reg, uint32_t val,
1667 uint32_t mask)
1668 {
1669 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1670 amdgpu_ring_write(ring, reg << 2);
1671 amdgpu_ring_write(ring, mask);
1672 amdgpu_ring_write(ring, val);
1673 }
1674
vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1675 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1676 unsigned int vmid, uint64_t pd_addr)
1677 {
1678 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1679
1680 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1681
1682 /* wait for reg writes */
1683 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1684 vmid * hub->ctx_addr_distance,
1685 lower_32_bits(pd_addr), 0xffffffff);
1686 }
1687
vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1688 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1689 uint32_t reg, uint32_t val)
1690 {
1691 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1692 amdgpu_ring_write(ring, reg << 2);
1693 amdgpu_ring_write(ring, val);
1694 }
1695
vcn_v1_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1696 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1697 struct amdgpu_irq_src *source,
1698 unsigned type,
1699 enum amdgpu_interrupt_state state)
1700 {
1701 return 0;
1702 }
1703
vcn_v1_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1704 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1705 struct amdgpu_irq_src *source,
1706 struct amdgpu_iv_entry *entry)
1707 {
1708 DRM_DEBUG("IH: VCN TRAP\n");
1709
1710 switch (entry->src_id) {
1711 case 124:
1712 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1713 break;
1714 case 119:
1715 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1716 break;
1717 case 120:
1718 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1719 break;
1720 default:
1721 DRM_ERROR("Unhandled interrupt: %d %d\n",
1722 entry->src_id, entry->src_data[0]);
1723 break;
1724 }
1725
1726 return 0;
1727 }
1728
vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1729 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1730 {
1731 struct amdgpu_device *adev = ring->adev;
1732 int i;
1733
1734 WARN_ON(ring->wptr % 2 || count % 2);
1735
1736 for (i = 0; i < count / 2; i++) {
1737 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1738 amdgpu_ring_write(ring, 0);
1739 }
1740 }
1741
vcn_v1_0_set_powergating_state(void * handle,enum amd_powergating_state state)1742 static int vcn_v1_0_set_powergating_state(void *handle,
1743 enum amd_powergating_state state)
1744 {
1745 /* This doesn't actually powergate the VCN block.
1746 * That's done in the dpm code via the SMC. This
1747 * just re-inits the block as necessary. The actual
1748 * gating still happens in the dpm code. We should
1749 * revisit this when there is a cleaner line between
1750 * the smc and the hw blocks
1751 */
1752 int ret;
1753 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1754
1755 if(state == adev->vcn.cur_state)
1756 return 0;
1757
1758 if (state == AMD_PG_STATE_GATE)
1759 ret = vcn_v1_0_stop(adev);
1760 else
1761 ret = vcn_v1_0_start(adev);
1762
1763 if(!ret)
1764 adev->vcn.cur_state = state;
1765 return ret;
1766 }
1767
vcn_v1_0_idle_work_handler(struct work_struct * work)1768 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1769 {
1770 struct amdgpu_device *adev =
1771 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1772 unsigned int fences = 0, i;
1773
1774 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1775 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1776
1777 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1778 struct dpg_pause_state new_state;
1779
1780 if (fences)
1781 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1782 else
1783 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1784
1785 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1786 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1787 else
1788 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1789
1790 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1791 }
1792
1793 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec);
1794 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1795
1796 if (fences == 0) {
1797 amdgpu_gfx_off_ctrl(adev, true);
1798 if (adev->pm.dpm_enabled)
1799 amdgpu_dpm_enable_uvd(adev, false);
1800 else
1801 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1802 AMD_PG_STATE_GATE);
1803 } else {
1804 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1805 }
1806 }
1807
vcn_v1_0_ring_begin_use(struct amdgpu_ring * ring)1808 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1809 {
1810 struct amdgpu_device *adev = ring->adev;
1811 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1812
1813 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1814
1815 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
1816 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1817
1818 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1819
1820 }
1821
vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring * ring,bool set_clocks)1822 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1823 {
1824 struct amdgpu_device *adev = ring->adev;
1825
1826 if (set_clocks) {
1827 amdgpu_gfx_off_ctrl(adev, false);
1828 if (adev->pm.dpm_enabled)
1829 amdgpu_dpm_enable_uvd(adev, true);
1830 else
1831 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1832 AMD_PG_STATE_UNGATE);
1833 }
1834
1835 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1836 struct dpg_pause_state new_state;
1837 unsigned int fences = 0, i;
1838
1839 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1840 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1841
1842 if (fences)
1843 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1844 else
1845 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1846
1847 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1848 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1849 else
1850 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1851
1852 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1853 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1854 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1855 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1856
1857 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1858 }
1859 }
1860
vcn_v1_0_ring_end_use(struct amdgpu_ring * ring)1861 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1862 {
1863 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1864 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1865 }
1866
1867 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1868 .name = "vcn_v1_0",
1869 .early_init = vcn_v1_0_early_init,
1870 .late_init = NULL,
1871 .sw_init = vcn_v1_0_sw_init,
1872 .sw_fini = vcn_v1_0_sw_fini,
1873 .hw_init = vcn_v1_0_hw_init,
1874 .hw_fini = vcn_v1_0_hw_fini,
1875 .suspend = vcn_v1_0_suspend,
1876 .resume = vcn_v1_0_resume,
1877 .is_idle = vcn_v1_0_is_idle,
1878 .wait_for_idle = vcn_v1_0_wait_for_idle,
1879 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
1880 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
1881 .soft_reset = NULL /* vcn_v1_0_soft_reset */,
1882 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
1883 .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1884 .set_powergating_state = vcn_v1_0_set_powergating_state,
1885 };
1886
1887 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
1888 .type = AMDGPU_RING_TYPE_VCN_DEC,
1889 .align_mask = 0xf,
1890 .support_64bit_ptrs = false,
1891 .no_user_fence = true,
1892 .vmhub = AMDGPU_MMHUB_0,
1893 .get_rptr = vcn_v1_0_dec_ring_get_rptr,
1894 .get_wptr = vcn_v1_0_dec_ring_get_wptr,
1895 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1896 .emit_frame_size =
1897 6 + 6 + /* hdp invalidate / flush */
1898 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1899 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1900 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1901 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1902 6,
1903 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
1904 .emit_ib = vcn_v1_0_dec_ring_emit_ib,
1905 .emit_fence = vcn_v1_0_dec_ring_emit_fence,
1906 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
1907 .test_ring = amdgpu_vcn_dec_ring_test_ring,
1908 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1909 .insert_nop = vcn_v1_0_dec_ring_insert_nop,
1910 .insert_start = vcn_v1_0_dec_ring_insert_start,
1911 .insert_end = vcn_v1_0_dec_ring_insert_end,
1912 .pad_ib = amdgpu_ring_generic_pad_ib,
1913 .begin_use = vcn_v1_0_ring_begin_use,
1914 .end_use = vcn_v1_0_ring_end_use,
1915 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1916 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1917 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1918 };
1919
1920 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
1921 .type = AMDGPU_RING_TYPE_VCN_ENC,
1922 .align_mask = 0x3f,
1923 .nop = VCN_ENC_CMD_NO_OP,
1924 .support_64bit_ptrs = false,
1925 .no_user_fence = true,
1926 .vmhub = AMDGPU_MMHUB_0,
1927 .get_rptr = vcn_v1_0_enc_ring_get_rptr,
1928 .get_wptr = vcn_v1_0_enc_ring_get_wptr,
1929 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1930 .emit_frame_size =
1931 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1932 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1933 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
1934 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1935 1, /* vcn_v1_0_enc_ring_insert_end */
1936 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
1937 .emit_ib = vcn_v1_0_enc_ring_emit_ib,
1938 .emit_fence = vcn_v1_0_enc_ring_emit_fence,
1939 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
1940 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1941 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1942 .insert_nop = amdgpu_ring_insert_nop,
1943 .insert_end = vcn_v1_0_enc_ring_insert_end,
1944 .pad_ib = amdgpu_ring_generic_pad_ib,
1945 .begin_use = vcn_v1_0_ring_begin_use,
1946 .end_use = vcn_v1_0_ring_end_use,
1947 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1948 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1949 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1950 };
1951
vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device * adev)1952 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1953 {
1954 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1955 DRM_INFO("VCN decode is enabled in VM mode\n");
1956 }
1957
vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device * adev)1958 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1959 {
1960 int i;
1961
1962 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1963 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1964
1965 DRM_INFO("VCN encode is enabled in VM mode\n");
1966 }
1967
1968 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
1969 .set = vcn_v1_0_set_interrupt_state,
1970 .process = vcn_v1_0_process_interrupt,
1971 };
1972
vcn_v1_0_set_irq_funcs(struct amdgpu_device * adev)1973 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1974 {
1975 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
1976 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
1977 }
1978
1979 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
1980 {
1981 .type = AMD_IP_BLOCK_TYPE_VCN,
1982 .major = 1,
1983 .minor = 0,
1984 .rev = 0,
1985 .funcs = &vcn_v1_0_ip_funcs,
1986 };
1987