1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 }; 244 245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 246 do { \ 247 tables[table_id].size = s; \ 248 tables[table_id].align = a; \ 249 tables[table_id].domain = d; \ 250 } while (0) 251 252 struct smu_table { 253 uint64_t size; 254 uint32_t align; 255 uint8_t domain; 256 uint64_t mc_address; 257 void *cpu_addr; 258 struct amdgpu_bo *bo; 259 uint32_t version; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values { 286 uint32_t revision; 287 uint32_t gfxclk; 288 uint32_t uclk; 289 uint32_t socclk; 290 uint32_t dcefclk; 291 uint32_t eclk; 292 uint32_t vclk; 293 uint32_t dclk; 294 uint16_t vddc; 295 uint16_t vddci; 296 uint16_t mvddc; 297 uint16_t vdd_gfx; 298 uint8_t cooling_id; 299 uint32_t pp_table_id; 300 uint32_t format_revision; 301 uint32_t content_revision; 302 uint32_t fclk; 303 uint32_t lclk; 304 uint32_t firmware_caps; 305 }; 306 307 enum smu_table_id { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COMBO_PPTABLE, 324 SMU_TABLE_WIFIBAND, 325 SMU_TABLE_COUNT, 326 }; 327 328 struct smu_table_context { 329 void *power_play_table; 330 uint32_t power_play_table_size; 331 void *hardcode_pptable; 332 unsigned long metrics_time; 333 void *metrics_table; 334 void *clocks_table; 335 void *watermarks_table; 336 337 void *max_sustainable_clocks; 338 struct smu_bios_boot_up_values boot_values; 339 void *driver_pptable; 340 void *combo_pptable; 341 void *ecc_table; 342 void *driver_smu_config_table; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_context; 366 struct smu_dpm_policy; 367 368 struct smu_dpm_policy_desc { 369 const char *name; 370 char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level); 371 }; 372 373 struct smu_dpm_policy { 374 struct smu_dpm_policy_desc *desc; 375 enum pp_pm_policy policy_type; 376 unsigned long level_mask; 377 int current_level; 378 int (*set_policy)(struct smu_context *ctxt, int level); 379 }; 380 381 struct smu_dpm_policy_ctxt { 382 struct smu_dpm_policy policies[PP_PM_POLICY_NUM]; 383 unsigned long policy_mask; 384 }; 385 386 struct smu_dpm_context { 387 uint32_t dpm_context_size; 388 void *dpm_context; 389 void *golden_dpm_context; 390 enum amd_dpm_forced_level dpm_level; 391 enum amd_dpm_forced_level saved_dpm_level; 392 enum amd_dpm_forced_level requested_dpm_level; 393 struct smu_power_state *dpm_request_power_state; 394 struct smu_power_state *dpm_current_power_state; 395 struct mclock_latency_table *mclk_latency_table; 396 struct smu_dpm_policy_ctxt *dpm_policies; 397 }; 398 399 struct smu_power_gate { 400 bool uvd_gated; 401 bool vce_gated; 402 atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES]; 403 atomic_t jpeg_gated; 404 atomic_t vpe_gated; 405 atomic_t umsch_mm_gated; 406 }; 407 408 struct smu_power_context { 409 void *power_context; 410 uint32_t power_context_size; 411 struct smu_power_gate power_gate; 412 }; 413 414 #define SMU_FEATURE_MAX (64) 415 struct smu_feature { 416 uint32_t feature_num; 417 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 418 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 419 }; 420 421 struct smu_clocks { 422 uint32_t engine_clock; 423 uint32_t memory_clock; 424 uint32_t bus_bandwidth; 425 uint32_t engine_clock_in_sr; 426 uint32_t dcef_clock; 427 uint32_t dcef_clock_in_sr; 428 }; 429 430 #define MAX_REGULAR_DPM_NUM 16 431 struct mclk_latency_entries { 432 uint32_t frequency; 433 uint32_t latency; 434 }; 435 struct mclock_latency_table { 436 uint32_t count; 437 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 438 }; 439 440 enum smu_reset_mode { 441 SMU_RESET_MODE_0, 442 SMU_RESET_MODE_1, 443 SMU_RESET_MODE_2, 444 }; 445 446 enum smu_baco_state { 447 SMU_BACO_STATE_ENTER = 0, 448 SMU_BACO_STATE_EXIT, 449 SMU_BACO_STATE_NONE, 450 }; 451 452 struct smu_baco_context { 453 uint32_t state; 454 bool platform_support; 455 bool maco_support; 456 }; 457 458 struct smu_freq_info { 459 uint32_t min; 460 uint32_t max; 461 uint32_t freq_level; 462 }; 463 464 struct pstates_clk_freq { 465 uint32_t min; 466 uint32_t standard; 467 uint32_t peak; 468 struct smu_freq_info custom; 469 struct smu_freq_info curr; 470 }; 471 472 struct smu_umd_pstate_table { 473 struct pstates_clk_freq gfxclk_pstate; 474 struct pstates_clk_freq socclk_pstate; 475 struct pstates_clk_freq uclk_pstate; 476 struct pstates_clk_freq vclk_pstate; 477 struct pstates_clk_freq dclk_pstate; 478 struct pstates_clk_freq fclk_pstate; 479 }; 480 481 struct cmn2asic_msg_mapping { 482 int valid_mapping; 483 int map_to; 484 uint32_t flags; 485 }; 486 487 struct cmn2asic_mapping { 488 int valid_mapping; 489 int map_to; 490 }; 491 492 struct stb_context { 493 uint32_t stb_buf_size; 494 bool enabled; 495 spinlock_t lock; 496 }; 497 498 enum smu_fw_status { 499 SMU_FW_INIT = 0, 500 SMU_FW_RUNTIME, 501 SMU_FW_HANG, 502 }; 503 504 #define WORKLOAD_POLICY_MAX 7 505 506 /* 507 * Configure wbrf event handling pace as there can be only one 508 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 509 */ 510 #define SMU_WBRF_EVENT_HANDLING_PACE 10 511 512 struct smu_context { 513 struct amdgpu_device *adev; 514 struct amdgpu_irq_src irq_source; 515 516 const struct pptable_funcs *ppt_funcs; 517 const struct cmn2asic_msg_mapping *message_map; 518 const struct cmn2asic_mapping *clock_map; 519 const struct cmn2asic_mapping *feature_map; 520 const struct cmn2asic_mapping *table_map; 521 const struct cmn2asic_mapping *pwr_src_map; 522 const struct cmn2asic_mapping *workload_map; 523 struct mutex message_lock; 524 uint64_t pool_size; 525 526 struct smu_table_context smu_table; 527 struct smu_dpm_context smu_dpm; 528 struct smu_power_context smu_power; 529 struct smu_feature smu_feature; 530 struct amd_pp_display_configuration *display_config; 531 struct smu_baco_context smu_baco; 532 struct smu_temperature_range thermal_range; 533 void *od_settings; 534 535 struct smu_umd_pstate_table pstate_table; 536 uint32_t pstate_sclk; 537 uint32_t pstate_mclk; 538 539 bool od_enabled; 540 uint32_t current_power_limit; 541 uint32_t default_power_limit; 542 uint32_t max_power_limit; 543 uint32_t min_power_limit; 544 545 /* soft pptable */ 546 uint32_t ppt_offset_bytes; 547 uint32_t ppt_size_bytes; 548 uint8_t *ppt_start_addr; 549 550 bool support_power_containment; 551 bool disable_watermark; 552 553 #define WATERMARKS_EXIST (1 << 0) 554 #define WATERMARKS_LOADED (1 << 1) 555 uint32_t watermarks_bitmap; 556 uint32_t hard_min_uclk_req_from_dal; 557 bool disable_uclk_switch; 558 559 /* asic agnostic workload mask */ 560 uint32_t workload_mask; 561 bool pause_workload; 562 /* default/user workload preference */ 563 uint32_t power_profile_mode; 564 uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT]; 565 /* backend specific custom workload settings */ 566 long *custom_profile_params; 567 bool pm_enabled; 568 bool is_apu; 569 570 uint32_t smc_driver_if_version; 571 uint32_t smc_fw_if_version; 572 uint32_t smc_fw_version; 573 uint32_t smc_fw_caps; 574 uint8_t smc_fw_state; 575 576 bool uploading_custom_pp_table; 577 bool dc_controlled_by_gpio; 578 579 struct work_struct throttling_logging_work; 580 atomic64_t throttle_int_counter; 581 struct work_struct interrupt_work; 582 583 unsigned fan_max_rpm; 584 unsigned manual_fan_speed_pwm; 585 586 uint32_t gfx_default_hard_min_freq; 587 uint32_t gfx_default_soft_max_freq; 588 uint32_t gfx_actual_hard_min_freq; 589 uint32_t gfx_actual_soft_max_freq; 590 591 /* APU only */ 592 uint32_t cpu_default_soft_min_freq; 593 uint32_t cpu_default_soft_max_freq; 594 uint32_t cpu_actual_soft_min_freq; 595 uint32_t cpu_actual_soft_max_freq; 596 uint32_t cpu_core_id_select; 597 uint16_t cpu_core_num; 598 599 struct smu_user_dpm_profile user_dpm_profile; 600 601 struct stb_context stb_context; 602 603 struct firmware pptable_firmware; 604 605 u32 param_reg; 606 u32 msg_reg; 607 u32 resp_reg; 608 609 u32 debug_param_reg; 610 u32 debug_msg_reg; 611 u32 debug_resp_reg; 612 613 struct delayed_work swctf_delayed_work; 614 615 /* data structures for wbrf feature support */ 616 bool wbrf_supported; 617 struct notifier_block wbrf_notifier; 618 struct delayed_work wbrf_delayed_work; 619 }; 620 621 struct i2c_adapter; 622 623 /** 624 * struct pptable_funcs - Callbacks used to interact with the SMU. 625 */ 626 struct pptable_funcs { 627 /** 628 * @run_btc: Calibrate voltage/frequency curve to fit the system's 629 * power delivery and voltage margins. Required for adaptive 630 * voltage frequency scaling (AVFS). 631 */ 632 int (*run_btc)(struct smu_context *smu); 633 634 /** 635 * @get_allowed_feature_mask: Get allowed feature mask. 636 * &feature_mask: Array to store feature mask. 637 * &num: Elements in &feature_mask. 638 */ 639 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 640 641 /** 642 * @get_current_power_state: Get the current power state. 643 * 644 * Return: Current power state on success, negative errno on failure. 645 */ 646 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 647 648 /** 649 * @set_default_dpm_table: Retrieve the default overdrive settings from 650 * the SMU. 651 */ 652 int (*set_default_dpm_table)(struct smu_context *smu); 653 654 int (*set_power_state)(struct smu_context *smu); 655 656 /** 657 * @populate_umd_state_clk: Populate the UMD power state table with 658 * defaults. 659 */ 660 int (*populate_umd_state_clk)(struct smu_context *smu); 661 662 /** 663 * @print_clk_levels: Print DPM clock levels for a clock domain 664 * to buffer. Star current level. 665 * 666 * Used for sysfs interfaces. 667 * Return: Number of characters written to the buffer 668 */ 669 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 670 671 /** 672 * @emit_clk_levels: Print DPM clock levels for a clock domain 673 * to buffer using sysfs_emit_at. Star current level. 674 * 675 * Used for sysfs interfaces. 676 * &buf: sysfs buffer 677 * &offset: offset within buffer to start printing, which is updated by the 678 * function. 679 * 680 * Return: 0 on Success or Negative to indicate an error occurred. 681 */ 682 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 683 684 /** 685 * @force_clk_levels: Set a range of allowed DPM levels for a clock 686 * domain. 687 * &clk_type: Clock domain. 688 * &mask: Range of allowed DPM levels. 689 */ 690 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 691 692 /** 693 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 694 * &type: Type of edit. 695 * &input: Edit parameters. 696 * &size: Size of &input. 697 */ 698 int (*od_edit_dpm_table)(struct smu_context *smu, 699 enum PP_OD_DPM_TABLE_COMMAND type, 700 long *input, uint32_t size); 701 702 /** 703 * @restore_user_od_settings: Restore the user customized 704 * OD settings on S3/S4/Runpm resume. 705 */ 706 int (*restore_user_od_settings)(struct smu_context *smu); 707 708 /** 709 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 710 * domain. 711 */ 712 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 713 enum smu_clk_type clk_type, 714 struct 715 pp_clock_levels_with_latency 716 *clocks); 717 /** 718 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 719 * domain. 720 */ 721 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 722 enum amd_pp_clock_type type, 723 struct 724 pp_clock_levels_with_voltage 725 *clocks); 726 727 /** 728 * @get_power_profile_mode: Print all power profile modes to 729 * buffer. Star current mode. 730 */ 731 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 732 733 /** 734 * @set_power_profile_mode: Set a power profile mode. Also used to 735 * create/set custom power profile modes. 736 * &input: Power profile mode parameters. 737 * &workload_mask: mask of workloads to enable 738 * &custom_params: custom profile parameters 739 * &custom_params_max_idx: max valid idx into custom_params 740 */ 741 int (*set_power_profile_mode)(struct smu_context *smu, u32 workload_mask, 742 long *custom_params, u32 custom_params_max_idx); 743 744 /** 745 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 746 * management. 747 */ 748 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst); 749 750 /** 751 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 752 * management. 753 */ 754 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 755 756 /** 757 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 758 */ 759 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 760 761 /** 762 * @read_sensor: Read data from a sensor. 763 * &sensor: Sensor to read data from. 764 * &data: Sensor reading. 765 * &size: Size of &data. 766 */ 767 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 768 void *data, uint32_t *size); 769 770 /** 771 * @get_apu_thermal_limit: get apu core limit from smu 772 * &limit: current limit temperature in millidegrees Celsius 773 */ 774 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 775 776 /** 777 * @set_apu_thermal_limit: update all controllers with new limit 778 * &limit: limit temperature to be setted, in millidegrees Celsius 779 */ 780 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 781 782 /** 783 * @pre_display_config_changed: Prepare GPU for a display configuration 784 * change. 785 * 786 * Disable display tracking and pin memory clock speed to maximum. Used 787 * in display component synchronization. 788 */ 789 int (*pre_display_config_changed)(struct smu_context *smu); 790 791 /** 792 * @display_config_changed: Notify the SMU of the current display 793 * configuration. 794 * 795 * Allows SMU to properly track blanking periods for memory clock 796 * adjustment. Used in display component synchronization. 797 */ 798 int (*display_config_changed)(struct smu_context *smu); 799 800 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 801 802 /** 803 * @notify_smc_display_config: Applies display requirements to the 804 * current power state. 805 * 806 * Optimize deep sleep DCEFclk and mclk for the current display 807 * configuration. Used in display component synchronization. 808 */ 809 int (*notify_smc_display_config)(struct smu_context *smu); 810 811 /** 812 * @is_dpm_running: Check if DPM is running. 813 * 814 * Return: True if DPM is running, false otherwise. 815 */ 816 bool (*is_dpm_running)(struct smu_context *smu); 817 818 /** 819 * @get_fan_speed_pwm: Get the current fan speed in PWM. 820 */ 821 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 822 823 /** 824 * @get_fan_speed_rpm: Get the current fan speed in rpm. 825 */ 826 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 827 828 /** 829 * @set_watermarks_table: Configure and upload the watermarks tables to 830 * the SMU. 831 */ 832 int (*set_watermarks_table)(struct smu_context *smu, 833 struct pp_smu_wm_range_sets *clock_ranges); 834 835 /** 836 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 837 */ 838 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 839 840 /** 841 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 842 * &clocks_in_khz: Array of DPM levels. 843 * &num_states: Elements in &clocks_in_khz. 844 */ 845 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 846 847 /** 848 * @set_default_od_settings: Set the overdrive tables to defaults. 849 */ 850 int (*set_default_od_settings)(struct smu_context *smu); 851 852 /** 853 * @set_performance_level: Set a performance level. 854 */ 855 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 856 857 /** 858 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 859 * clock switching. 860 * 861 * Disabling this feature forces memory clock speed to maximum. 862 * Enabling sets the minimum memory clock capable of driving the 863 * current display configuration. 864 */ 865 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 866 867 /** 868 * @get_power_limit: Get the device's power limits. 869 */ 870 int (*get_power_limit)(struct smu_context *smu, 871 uint32_t *current_power_limit, 872 uint32_t *default_power_limit, 873 uint32_t *max_power_limit, 874 uint32_t *min_power_limit); 875 876 /** 877 * @get_ppt_limit: Get the device's ppt limits. 878 */ 879 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 880 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 881 882 /** 883 * @set_df_cstate: Set data fabric cstate. 884 */ 885 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 886 887 /** 888 * @update_pcie_parameters: Update and upload the system's PCIe 889 * capabilites to the SMU. 890 * &pcie_gen_cap: Maximum allowed PCIe generation. 891 * &pcie_width_cap: Maximum allowed PCIe width. 892 */ 893 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 894 895 /** 896 * @i2c_init: Initialize i2c. 897 * 898 * The i2c bus is used internally by the SMU voltage regulators and 899 * other devices. The i2c's EEPROM also stores bad page tables on boards 900 * with ECC. 901 */ 902 int (*i2c_init)(struct smu_context *smu); 903 904 /** 905 * @i2c_fini: Tear down i2c. 906 */ 907 void (*i2c_fini)(struct smu_context *smu); 908 909 /** 910 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 911 */ 912 void (*get_unique_id)(struct smu_context *smu); 913 914 /** 915 * @get_dpm_clock_table: Get a copy of the DPM clock table. 916 * 917 * Used by display component in bandwidth and watermark calculations. 918 */ 919 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 920 921 /** 922 * @init_microcode: Request the SMU's firmware from the kernel. 923 */ 924 int (*init_microcode)(struct smu_context *smu); 925 926 /** 927 * @load_microcode: Load firmware onto the SMU. 928 */ 929 int (*load_microcode)(struct smu_context *smu); 930 931 /** 932 * @fini_microcode: Release the SMU's firmware. 933 */ 934 void (*fini_microcode)(struct smu_context *smu); 935 936 /** 937 * @init_smc_tables: Initialize the SMU tables. 938 */ 939 int (*init_smc_tables)(struct smu_context *smu); 940 941 /** 942 * @fini_smc_tables: Release the SMU tables. 943 */ 944 int (*fini_smc_tables)(struct smu_context *smu); 945 946 /** 947 * @init_power: Initialize the power gate table context. 948 */ 949 int (*init_power)(struct smu_context *smu); 950 951 /** 952 * @fini_power: Release the power gate table context. 953 */ 954 int (*fini_power)(struct smu_context *smu); 955 956 /** 957 * @check_fw_status: Check the SMU's firmware status. 958 * 959 * Return: Zero if check passes, negative errno on failure. 960 */ 961 int (*check_fw_status)(struct smu_context *smu); 962 963 /** 964 * @set_mp1_state: put SMU into a correct state for comming 965 * resume from runpm or gpu reset. 966 */ 967 int (*set_mp1_state)(struct smu_context *smu, 968 enum pp_mp1_state mp1_state); 969 970 /** 971 * @setup_pptable: Initialize the power play table and populate it with 972 * default values. 973 */ 974 int (*setup_pptable)(struct smu_context *smu); 975 976 /** 977 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 978 */ 979 int (*get_vbios_bootup_values)(struct smu_context *smu); 980 981 /** 982 * @check_fw_version: Print driver and SMU interface versions to the 983 * system log. 984 * 985 * Interface mismatch is not a critical failure. 986 */ 987 int (*check_fw_version)(struct smu_context *smu); 988 989 /** 990 * @powergate_sdma: Power up/down system direct memory access. 991 */ 992 int (*powergate_sdma)(struct smu_context *smu, bool gate); 993 994 /** 995 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 996 * gating. 997 */ 998 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 999 1000 /** 1001 * @write_pptable: Write the power play table to the SMU. 1002 */ 1003 int (*write_pptable)(struct smu_context *smu); 1004 1005 /** 1006 * @set_driver_table_location: Send the location of the driver table to 1007 * the SMU. 1008 */ 1009 int (*set_driver_table_location)(struct smu_context *smu); 1010 1011 /** 1012 * @set_tool_table_location: Send the location of the tool table to the 1013 * SMU. 1014 */ 1015 int (*set_tool_table_location)(struct smu_context *smu); 1016 1017 /** 1018 * @notify_memory_pool_location: Send the location of the memory pool to 1019 * the SMU. 1020 */ 1021 int (*notify_memory_pool_location)(struct smu_context *smu); 1022 1023 /** 1024 * @system_features_control: Enable/disable all SMU features. 1025 */ 1026 int (*system_features_control)(struct smu_context *smu, bool en); 1027 1028 /** 1029 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1030 * &msg: Type of message. 1031 * ¶m: Message parameter. 1032 * &read_arg: SMU response (optional). 1033 */ 1034 int (*send_smc_msg_with_param)(struct smu_context *smu, 1035 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1036 1037 /** 1038 * @send_smc_msg: Send a message to the SMU. 1039 * &msg: Type of message. 1040 * &read_arg: SMU response (optional). 1041 */ 1042 int (*send_smc_msg)(struct smu_context *smu, 1043 enum smu_message_type msg, 1044 uint32_t *read_arg); 1045 1046 /** 1047 * @init_display_count: Notify the SMU of the number of display 1048 * components in current display configuration. 1049 */ 1050 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1051 1052 /** 1053 * @set_allowed_mask: Notify the SMU of the features currently allowed 1054 * by the driver. 1055 */ 1056 int (*set_allowed_mask)(struct smu_context *smu); 1057 1058 /** 1059 * @get_enabled_mask: Get a mask of features that are currently enabled 1060 * on the SMU. 1061 * &feature_mask: Enabled feature mask. 1062 */ 1063 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1064 1065 /** 1066 * @feature_is_enabled: Test if a feature is enabled. 1067 * 1068 * Return: One if enabled, zero if disabled. 1069 */ 1070 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1071 1072 /** 1073 * @disable_all_features_with_exception: Disable all features with 1074 * exception to those in &mask. 1075 */ 1076 int (*disable_all_features_with_exception)(struct smu_context *smu, 1077 enum smu_feature_mask mask); 1078 1079 /** 1080 * @notify_display_change: General interface call to let SMU know about DC change 1081 */ 1082 int (*notify_display_change)(struct smu_context *smu); 1083 1084 /** 1085 * @set_power_limit: Set power limit in watts. 1086 */ 1087 int (*set_power_limit)(struct smu_context *smu, 1088 enum smu_ppt_limit_type limit_type, 1089 uint32_t limit); 1090 1091 /** 1092 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1093 * table with values from the SMU. 1094 */ 1095 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1096 1097 /** 1098 * @enable_thermal_alert: Enable thermal alert interrupts. 1099 */ 1100 int (*enable_thermal_alert)(struct smu_context *smu); 1101 1102 /** 1103 * @disable_thermal_alert: Disable thermal alert interrupts. 1104 */ 1105 int (*disable_thermal_alert)(struct smu_context *smu); 1106 1107 /** 1108 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1109 * clock speed in MHz. 1110 */ 1111 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1112 1113 /** 1114 * @display_clock_voltage_request: Set a hard minimum frequency 1115 * for a clock domain. 1116 */ 1117 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1118 pp_display_clock_request 1119 *clock_req); 1120 1121 /** 1122 * @get_fan_control_mode: Get the current fan control mode. 1123 */ 1124 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1125 1126 /** 1127 * @set_fan_control_mode: Set the fan control mode. 1128 */ 1129 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1130 1131 /** 1132 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1133 */ 1134 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1135 1136 /** 1137 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1138 */ 1139 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1140 1141 /** 1142 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1143 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1144 */ 1145 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1146 1147 /** 1148 * @gfx_off_control: Enable/disable graphics engine poweroff. 1149 */ 1150 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1151 1152 1153 /** 1154 * @get_gfx_off_status: Get graphics engine poweroff status. 1155 * 1156 * Return: 1157 * 0 - GFXOFF(default). 1158 * 1 - Transition out of GFX State. 1159 * 2 - Not in GFXOFF. 1160 * 3 - Transition into GFXOFF. 1161 */ 1162 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1163 1164 /** 1165 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1166 * query since system power-up 1167 */ 1168 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1169 1170 /** 1171 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1172 */ 1173 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1174 1175 /** 1176 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1177 */ 1178 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1179 1180 /** 1181 * @register_irq_handler: Register interupt request handlers. 1182 */ 1183 int (*register_irq_handler)(struct smu_context *smu); 1184 1185 /** 1186 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1187 */ 1188 int (*set_azalia_d3_pme)(struct smu_context *smu); 1189 1190 /** 1191 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1192 * clock speeds table. 1193 * 1194 * Provides a way for the display component (DC) to get the max 1195 * sustainable clocks from the SMU. 1196 */ 1197 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1198 1199 /** 1200 * @get_bamaco_support: Check if GPU supports BACO/MACO 1201 * BACO: Bus Active, Chip Off 1202 * MACO: Memory Active, Chip Off 1203 */ 1204 int (*get_bamaco_support)(struct smu_context *smu); 1205 1206 /** 1207 * @baco_get_state: Get the current BACO state. 1208 * 1209 * Return: Current BACO state. 1210 */ 1211 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1212 1213 /** 1214 * @baco_set_state: Enter/exit BACO. 1215 */ 1216 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1217 1218 /** 1219 * @baco_enter: Enter BACO. 1220 */ 1221 int (*baco_enter)(struct smu_context *smu); 1222 1223 /** 1224 * @baco_exit: Exit Baco. 1225 */ 1226 int (*baco_exit)(struct smu_context *smu); 1227 1228 /** 1229 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1230 */ 1231 bool (*mode1_reset_is_support)(struct smu_context *smu); 1232 /** 1233 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1234 */ 1235 bool (*mode2_reset_is_support)(struct smu_context *smu); 1236 1237 /** 1238 * @mode1_reset: Perform mode1 reset. 1239 * 1240 * Complete GPU reset. 1241 */ 1242 int (*mode1_reset)(struct smu_context *smu); 1243 1244 /** 1245 * @mode2_reset: Perform mode2 reset. 1246 * 1247 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1248 * IPs reset varies by asic. 1249 */ 1250 int (*mode2_reset)(struct smu_context *smu); 1251 /* for gfx feature enablement after mode2 reset */ 1252 int (*enable_gfx_features)(struct smu_context *smu); 1253 1254 /** 1255 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1256 * domain in MHz. 1257 */ 1258 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1259 1260 /** 1261 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1262 * domain in MHz. 1263 */ 1264 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max, 1265 bool automatic); 1266 1267 /** 1268 * @set_power_source: Notify the SMU of the current power source. 1269 */ 1270 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1271 1272 /** 1273 * @log_thermal_throttling_event: Print a thermal throttling warning to 1274 * the system's log. 1275 */ 1276 void (*log_thermal_throttling_event)(struct smu_context *smu); 1277 1278 /** 1279 * @get_pp_feature_mask: Print a human readable table of enabled 1280 * features to buffer. 1281 */ 1282 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1283 1284 /** 1285 * @set_pp_feature_mask: Request the SMU enable/disable features to 1286 * match those enabled in &new_mask. 1287 */ 1288 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1289 1290 /** 1291 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1292 * 1293 * Return: Size of &table 1294 */ 1295 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1296 1297 /** 1298 * @get_pm_metrics: Get one snapshot of power management metrics from 1299 * PMFW. 1300 * 1301 * Return: Size of the metrics sample 1302 */ 1303 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1304 size_t size); 1305 1306 /** 1307 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1308 */ 1309 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1310 1311 /** 1312 * @gfx_ulv_control: Enable/disable ultra low voltage. 1313 */ 1314 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1315 1316 /** 1317 * @deep_sleep_control: Enable/disable deep sleep. 1318 */ 1319 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1320 1321 /** 1322 * @get_fan_parameters: Get fan parameters. 1323 * 1324 * Get maximum fan speed from the power play table. 1325 */ 1326 int (*get_fan_parameters)(struct smu_context *smu); 1327 1328 /** 1329 * @post_init: Helper function for asic specific workarounds. 1330 */ 1331 int (*post_init)(struct smu_context *smu); 1332 1333 /** 1334 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1335 */ 1336 void (*interrupt_work)(struct smu_context *smu); 1337 1338 /** 1339 * @gpo_control: Enable/disable graphics power optimization if supported. 1340 */ 1341 int (*gpo_control)(struct smu_context *smu, bool enablement); 1342 1343 /** 1344 * @gfx_state_change_set: Send the current graphics state to the SMU. 1345 */ 1346 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1347 1348 /** 1349 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1350 * parameters to defaults. 1351 */ 1352 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1353 1354 /** 1355 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1356 */ 1357 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1358 1359 /** 1360 * @wait_for_event: Wait for events from SMU. 1361 */ 1362 int (*wait_for_event)(struct smu_context *smu, 1363 enum smu_event_type event, uint64_t event_arg); 1364 1365 /** 1366 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1367 * of SMUBUS table. 1368 */ 1369 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1370 1371 /** 1372 * @send_rma_reason: message rma reason event to SMU. 1373 */ 1374 int (*send_rma_reason)(struct smu_context *smu); 1375 1376 /** 1377 * @reset_sdma: message SMU to soft reset sdma instance. 1378 */ 1379 int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask); 1380 /** 1381 * @reset_sdma_is_supported: Check if support resets the SDMA engine. 1382 */ 1383 bool (*reset_sdma_is_supported)(struct smu_context *smu); 1384 1385 /** 1386 * @get_ecc_table: message SMU to get ECC INFO table. 1387 */ 1388 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1389 1390 1391 /** 1392 * @stb_collect_info: Collects Smart Trace Buffers data. 1393 */ 1394 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1395 1396 /** 1397 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1398 */ 1399 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1400 1401 /** 1402 * @set_config_table: Apply the input DriverSmuConfig table settings. 1403 */ 1404 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1405 1406 /** 1407 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1408 * of SMUBUS table. 1409 */ 1410 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1411 1412 /** 1413 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1414 */ 1415 int (*init_pptable_microcode)(struct smu_context *smu); 1416 1417 /** 1418 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1419 * management. 1420 */ 1421 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1422 1423 /** 1424 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1425 * management. 1426 */ 1427 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1428 1429 /** 1430 * @set_mall_enable: Init MALL power gating control. 1431 */ 1432 int (*set_mall_enable)(struct smu_context *smu); 1433 1434 /** 1435 * @notify_rlc_state: Notify RLC power state to SMU. 1436 */ 1437 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1438 1439 /** 1440 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1441 */ 1442 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1443 1444 /** 1445 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1446 */ 1447 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1448 1449 /** 1450 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1451 */ 1452 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1453 struct freq_band_range *exclusion_ranges); 1454 }; 1455 1456 typedef enum { 1457 METRICS_CURR_GFXCLK, 1458 METRICS_CURR_SOCCLK, 1459 METRICS_CURR_UCLK, 1460 METRICS_CURR_VCLK, 1461 METRICS_CURR_VCLK1, 1462 METRICS_CURR_DCLK, 1463 METRICS_CURR_DCLK1, 1464 METRICS_CURR_FCLK, 1465 METRICS_CURR_DCEFCLK, 1466 METRICS_AVERAGE_CPUCLK, 1467 METRICS_AVERAGE_GFXCLK, 1468 METRICS_AVERAGE_SOCCLK, 1469 METRICS_AVERAGE_FCLK, 1470 METRICS_AVERAGE_UCLK, 1471 METRICS_AVERAGE_VCLK, 1472 METRICS_AVERAGE_DCLK, 1473 METRICS_AVERAGE_VCLK1, 1474 METRICS_AVERAGE_DCLK1, 1475 METRICS_AVERAGE_GFXACTIVITY, 1476 METRICS_AVERAGE_MEMACTIVITY, 1477 METRICS_AVERAGE_VCNACTIVITY, 1478 METRICS_AVERAGE_SOCKETPOWER, 1479 METRICS_TEMPERATURE_EDGE, 1480 METRICS_TEMPERATURE_HOTSPOT, 1481 METRICS_TEMPERATURE_MEM, 1482 METRICS_TEMPERATURE_VRGFX, 1483 METRICS_TEMPERATURE_VRSOC, 1484 METRICS_TEMPERATURE_VRMEM, 1485 METRICS_THROTTLER_STATUS, 1486 METRICS_CURR_FANSPEED, 1487 METRICS_VOLTAGE_VDDSOC, 1488 METRICS_VOLTAGE_VDDGFX, 1489 METRICS_SS_APU_SHARE, 1490 METRICS_SS_DGPU_SHARE, 1491 METRICS_UNIQUE_ID_UPPER32, 1492 METRICS_UNIQUE_ID_LOWER32, 1493 METRICS_PCIE_RATE, 1494 METRICS_PCIE_WIDTH, 1495 METRICS_CURR_FANPWM, 1496 METRICS_CURR_SOCKETPOWER, 1497 METRICS_AVERAGE_VPECLK, 1498 METRICS_AVERAGE_IPUCLK, 1499 METRICS_AVERAGE_MPIPUCLK, 1500 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1501 METRICS_THROTTLER_RESIDENCY_SPL, 1502 METRICS_THROTTLER_RESIDENCY_FPPT, 1503 METRICS_THROTTLER_RESIDENCY_SPPT, 1504 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1505 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1506 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1507 } MetricsMember_t; 1508 1509 enum smu_cmn2asic_mapping_type { 1510 CMN2ASIC_MAPPING_MSG, 1511 CMN2ASIC_MAPPING_CLK, 1512 CMN2ASIC_MAPPING_FEATURE, 1513 CMN2ASIC_MAPPING_TABLE, 1514 CMN2ASIC_MAPPING_PWR, 1515 CMN2ASIC_MAPPING_WORKLOAD, 1516 }; 1517 1518 enum smu_baco_seq { 1519 BACO_SEQ_BACO = 0, 1520 BACO_SEQ_MSR, 1521 BACO_SEQ_BAMACO, 1522 BACO_SEQ_ULPS, 1523 BACO_SEQ_COUNT, 1524 }; 1525 1526 #define MSG_MAP(msg, index, flags) \ 1527 [SMU_MSG_##msg] = {1, (index), (flags)} 1528 1529 #define CLK_MAP(clk, index) \ 1530 [SMU_##clk] = {1, (index)} 1531 1532 #define FEA_MAP(fea) \ 1533 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1534 1535 #define FEA_MAP_REVERSE(fea) \ 1536 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1537 1538 #define FEA_MAP_HALF_REVERSE(fea) \ 1539 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1540 1541 #define TAB_MAP(tab) \ 1542 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1543 1544 #define TAB_MAP_VALID(tab) \ 1545 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1546 1547 #define TAB_MAP_INVALID(tab) \ 1548 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1549 1550 #define PWR_MAP(tab) \ 1551 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1552 1553 #define WORKLOAD_MAP(profile, workload) \ 1554 [profile] = {1, (workload)} 1555 1556 /** 1557 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1558 * 1559 * @dst: Pointer to destination struct 1560 * @first_dst_member: The member name in @dst where the overwrite begins 1561 * @last_dst_member: The member name in @dst where the overwrite ends after 1562 * @src: Pointer to the source struct 1563 * @first_src_member: The member name in @src where the copy begins 1564 * 1565 */ 1566 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1567 src, first_src_member) \ 1568 ({ \ 1569 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1570 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1571 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1572 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1573 __dst_offset; \ 1574 BUILD_BUG_ON(__src_size != __dst_size); \ 1575 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1576 (u8 *)(src) + __src_offset, \ 1577 __dst_size); \ 1578 }) 1579 1580 typedef struct { 1581 uint16_t LowFreq; 1582 uint16_t HighFreq; 1583 } WifiOneBand_t; 1584 1585 typedef struct { 1586 uint32_t WifiBandEntryNum; 1587 WifiOneBand_t WifiBandEntry[11]; 1588 uint32_t MmHubPadding[8]; 1589 } WifiBandEntryTable_t; 1590 1591 #define STR_SOC_PSTATE_POLICY "soc_pstate" 1592 #define STR_XGMI_PLPD_POLICY "xgmi_plpd" 1593 1594 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 1595 enum pp_pm_policy p_type); 1596 1597 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1598 int smu_get_power_limit(void *handle, 1599 uint32_t *limit, 1600 enum pp_power_limit_level pp_limit_level, 1601 enum pp_power_type pp_power_type); 1602 1603 bool smu_mode1_reset_is_support(struct smu_context *smu); 1604 bool smu_mode2_reset_is_support(struct smu_context *smu); 1605 int smu_mode1_reset(struct smu_context *smu); 1606 1607 extern const struct amd_ip_funcs smu_ip_funcs; 1608 1609 bool is_support_sw_smu(struct amdgpu_device *adev); 1610 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1611 int smu_write_watermarks_table(struct smu_context *smu); 1612 1613 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1614 uint32_t *min, uint32_t *max); 1615 1616 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1617 uint32_t min, uint32_t max); 1618 1619 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1620 1621 int smu_set_ac_dc(struct smu_context *smu); 1622 1623 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1624 enum pp_xgmi_plpd_mode mode); 1625 1626 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1627 1628 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1629 1630 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1631 1632 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1633 1634 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1635 1636 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1637 uint64_t event_arg); 1638 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1639 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1640 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1641 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1642 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1643 int smu_send_rma_reason(struct smu_context *smu); 1644 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask); 1645 bool smu_reset_sdma_is_supported(struct smu_context *smu); 1646 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 1647 int level); 1648 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1649 enum pp_pm_policy p_type, char *sysbuf); 1650 1651 #endif 1652 #endif 1653