1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 }; 244 245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 246 do { \ 247 tables[table_id].size = s; \ 248 tables[table_id].align = a; \ 249 tables[table_id].domain = d; \ 250 } while (0) 251 252 struct smu_table { 253 uint64_t size; 254 uint32_t align; 255 uint8_t domain; 256 uint64_t mc_address; 257 void *cpu_addr; 258 struct amdgpu_bo *bo; 259 uint32_t version; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values { 286 uint32_t revision; 287 uint32_t gfxclk; 288 uint32_t uclk; 289 uint32_t socclk; 290 uint32_t dcefclk; 291 uint32_t eclk; 292 uint32_t vclk; 293 uint32_t dclk; 294 uint16_t vddc; 295 uint16_t vddci; 296 uint16_t mvddc; 297 uint16_t vdd_gfx; 298 uint8_t cooling_id; 299 uint32_t pp_table_id; 300 uint32_t format_revision; 301 uint32_t content_revision; 302 uint32_t fclk; 303 uint32_t lclk; 304 uint32_t firmware_caps; 305 }; 306 307 enum smu_table_id { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COMBO_PPTABLE, 324 SMU_TABLE_WIFIBAND, 325 SMU_TABLE_COUNT, 326 }; 327 328 struct smu_table_context { 329 void *power_play_table; 330 uint32_t power_play_table_size; 331 void *hardcode_pptable; 332 unsigned long metrics_time; 333 void *metrics_table; 334 void *clocks_table; 335 void *watermarks_table; 336 337 void *max_sustainable_clocks; 338 struct smu_bios_boot_up_values boot_values; 339 void *driver_pptable; 340 void *combo_pptable; 341 void *ecc_table; 342 void *driver_smu_config_table; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_dpm_context { 366 uint32_t dpm_context_size; 367 void *dpm_context; 368 void *golden_dpm_context; 369 enum amd_dpm_forced_level dpm_level; 370 enum amd_dpm_forced_level saved_dpm_level; 371 enum amd_dpm_forced_level requested_dpm_level; 372 struct smu_power_state *dpm_request_power_state; 373 struct smu_power_state *dpm_current_power_state; 374 struct mclock_latency_table *mclk_latency_table; 375 }; 376 377 struct smu_power_gate { 378 bool uvd_gated; 379 bool vce_gated; 380 atomic_t vcn_gated; 381 atomic_t jpeg_gated; 382 atomic_t vpe_gated; 383 atomic_t umsch_mm_gated; 384 }; 385 386 struct smu_power_context { 387 void *power_context; 388 uint32_t power_context_size; 389 struct smu_power_gate power_gate; 390 }; 391 392 #define SMU_FEATURE_MAX (64) 393 struct smu_feature { 394 uint32_t feature_num; 395 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 396 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 397 }; 398 399 struct smu_clocks { 400 uint32_t engine_clock; 401 uint32_t memory_clock; 402 uint32_t bus_bandwidth; 403 uint32_t engine_clock_in_sr; 404 uint32_t dcef_clock; 405 uint32_t dcef_clock_in_sr; 406 }; 407 408 #define MAX_REGULAR_DPM_NUM 16 409 struct mclk_latency_entries { 410 uint32_t frequency; 411 uint32_t latency; 412 }; 413 struct mclock_latency_table { 414 uint32_t count; 415 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 416 }; 417 418 enum smu_reset_mode { 419 SMU_RESET_MODE_0, 420 SMU_RESET_MODE_1, 421 SMU_RESET_MODE_2, 422 }; 423 424 enum smu_baco_state { 425 SMU_BACO_STATE_ENTER = 0, 426 SMU_BACO_STATE_EXIT, 427 }; 428 429 struct smu_baco_context { 430 uint32_t state; 431 bool platform_support; 432 bool maco_support; 433 }; 434 435 struct smu_freq_info { 436 uint32_t min; 437 uint32_t max; 438 uint32_t freq_level; 439 }; 440 441 struct pstates_clk_freq { 442 uint32_t min; 443 uint32_t standard; 444 uint32_t peak; 445 struct smu_freq_info custom; 446 struct smu_freq_info curr; 447 }; 448 449 struct smu_umd_pstate_table { 450 struct pstates_clk_freq gfxclk_pstate; 451 struct pstates_clk_freq socclk_pstate; 452 struct pstates_clk_freq uclk_pstate; 453 struct pstates_clk_freq vclk_pstate; 454 struct pstates_clk_freq dclk_pstate; 455 struct pstates_clk_freq fclk_pstate; 456 }; 457 458 struct cmn2asic_msg_mapping { 459 int valid_mapping; 460 int map_to; 461 int valid_in_vf; 462 }; 463 464 struct cmn2asic_mapping { 465 int valid_mapping; 466 int map_to; 467 }; 468 469 struct stb_context { 470 uint32_t stb_buf_size; 471 bool enabled; 472 spinlock_t lock; 473 }; 474 475 #define WORKLOAD_POLICY_MAX 7 476 477 /* 478 * Configure wbrf event handling pace as there can be only one 479 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 480 */ 481 #define SMU_WBRF_EVENT_HANDLING_PACE 10 482 483 struct smu_context { 484 struct amdgpu_device *adev; 485 struct amdgpu_irq_src irq_source; 486 487 const struct pptable_funcs *ppt_funcs; 488 const struct cmn2asic_msg_mapping *message_map; 489 const struct cmn2asic_mapping *clock_map; 490 const struct cmn2asic_mapping *feature_map; 491 const struct cmn2asic_mapping *table_map; 492 const struct cmn2asic_mapping *pwr_src_map; 493 const struct cmn2asic_mapping *workload_map; 494 struct mutex message_lock; 495 uint64_t pool_size; 496 497 struct smu_table_context smu_table; 498 struct smu_dpm_context smu_dpm; 499 struct smu_power_context smu_power; 500 struct smu_feature smu_feature; 501 struct amd_pp_display_configuration *display_config; 502 struct smu_baco_context smu_baco; 503 struct smu_temperature_range thermal_range; 504 void *od_settings; 505 506 struct smu_umd_pstate_table pstate_table; 507 uint32_t pstate_sclk; 508 uint32_t pstate_mclk; 509 510 bool od_enabled; 511 uint32_t current_power_limit; 512 uint32_t default_power_limit; 513 uint32_t max_power_limit; 514 uint32_t min_power_limit; 515 516 /* soft pptable */ 517 uint32_t ppt_offset_bytes; 518 uint32_t ppt_size_bytes; 519 uint8_t *ppt_start_addr; 520 521 bool support_power_containment; 522 bool disable_watermark; 523 524 #define WATERMARKS_EXIST (1 << 0) 525 #define WATERMARKS_LOADED (1 << 1) 526 uint32_t watermarks_bitmap; 527 uint32_t hard_min_uclk_req_from_dal; 528 bool disable_uclk_switch; 529 530 uint32_t workload_mask; 531 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 532 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 533 uint32_t power_profile_mode; 534 uint32_t default_power_profile_mode; 535 bool pm_enabled; 536 bool is_apu; 537 538 uint32_t smc_driver_if_version; 539 uint32_t smc_fw_if_version; 540 uint32_t smc_fw_version; 541 542 bool uploading_custom_pp_table; 543 bool dc_controlled_by_gpio; 544 545 struct work_struct throttling_logging_work; 546 atomic64_t throttle_int_counter; 547 struct work_struct interrupt_work; 548 549 unsigned fan_max_rpm; 550 unsigned manual_fan_speed_pwm; 551 552 uint32_t gfx_default_hard_min_freq; 553 uint32_t gfx_default_soft_max_freq; 554 uint32_t gfx_actual_hard_min_freq; 555 uint32_t gfx_actual_soft_max_freq; 556 557 /* APU only */ 558 uint32_t cpu_default_soft_min_freq; 559 uint32_t cpu_default_soft_max_freq; 560 uint32_t cpu_actual_soft_min_freq; 561 uint32_t cpu_actual_soft_max_freq; 562 uint32_t cpu_core_id_select; 563 uint16_t cpu_core_num; 564 565 struct smu_user_dpm_profile user_dpm_profile; 566 567 struct stb_context stb_context; 568 569 struct firmware pptable_firmware; 570 571 u32 param_reg; 572 u32 msg_reg; 573 u32 resp_reg; 574 575 u32 debug_param_reg; 576 u32 debug_msg_reg; 577 u32 debug_resp_reg; 578 579 struct delayed_work swctf_delayed_work; 580 581 enum pp_xgmi_plpd_mode plpd_mode; 582 583 /* data structures for wbrf feature support */ 584 bool wbrf_supported; 585 struct notifier_block wbrf_notifier; 586 struct delayed_work wbrf_delayed_work; 587 }; 588 589 struct i2c_adapter; 590 591 /** 592 * struct pptable_funcs - Callbacks used to interact with the SMU. 593 */ 594 struct pptable_funcs { 595 /** 596 * @run_btc: Calibrate voltage/frequency curve to fit the system's 597 * power delivery and voltage margins. Required for adaptive 598 * voltage frequency scaling (AVFS). 599 */ 600 int (*run_btc)(struct smu_context *smu); 601 602 /** 603 * @get_allowed_feature_mask: Get allowed feature mask. 604 * &feature_mask: Array to store feature mask. 605 * &num: Elements in &feature_mask. 606 */ 607 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 608 609 /** 610 * @get_current_power_state: Get the current power state. 611 * 612 * Return: Current power state on success, negative errno on failure. 613 */ 614 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 615 616 /** 617 * @set_default_dpm_table: Retrieve the default overdrive settings from 618 * the SMU. 619 */ 620 int (*set_default_dpm_table)(struct smu_context *smu); 621 622 int (*set_power_state)(struct smu_context *smu); 623 624 /** 625 * @populate_umd_state_clk: Populate the UMD power state table with 626 * defaults. 627 */ 628 int (*populate_umd_state_clk)(struct smu_context *smu); 629 630 /** 631 * @print_clk_levels: Print DPM clock levels for a clock domain 632 * to buffer. Star current level. 633 * 634 * Used for sysfs interfaces. 635 * Return: Number of characters written to the buffer 636 */ 637 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 638 639 /** 640 * @emit_clk_levels: Print DPM clock levels for a clock domain 641 * to buffer using sysfs_emit_at. Star current level. 642 * 643 * Used for sysfs interfaces. 644 * &buf: sysfs buffer 645 * &offset: offset within buffer to start printing, which is updated by the 646 * function. 647 * 648 * Return: 0 on Success or Negative to indicate an error occurred. 649 */ 650 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 651 652 /** 653 * @force_clk_levels: Set a range of allowed DPM levels for a clock 654 * domain. 655 * &clk_type: Clock domain. 656 * &mask: Range of allowed DPM levels. 657 */ 658 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 659 660 /** 661 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 662 * &type: Type of edit. 663 * &input: Edit parameters. 664 * &size: Size of &input. 665 */ 666 int (*od_edit_dpm_table)(struct smu_context *smu, 667 enum PP_OD_DPM_TABLE_COMMAND type, 668 long *input, uint32_t size); 669 670 /** 671 * @restore_user_od_settings: Restore the user customized 672 * OD settings on S3/S4/Runpm resume. 673 */ 674 int (*restore_user_od_settings)(struct smu_context *smu); 675 676 /** 677 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 678 * domain. 679 */ 680 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 681 enum smu_clk_type clk_type, 682 struct 683 pp_clock_levels_with_latency 684 *clocks); 685 /** 686 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 687 * domain. 688 */ 689 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 690 enum amd_pp_clock_type type, 691 struct 692 pp_clock_levels_with_voltage 693 *clocks); 694 695 /** 696 * @get_power_profile_mode: Print all power profile modes to 697 * buffer. Star current mode. 698 */ 699 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 700 701 /** 702 * @set_power_profile_mode: Set a power profile mode. Also used to 703 * create/set custom power profile modes. 704 * &input: Power profile mode parameters. 705 * &size: Size of &input. 706 */ 707 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 708 709 /** 710 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 711 * management. 712 */ 713 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 714 715 /** 716 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 717 * management. 718 */ 719 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 720 721 /** 722 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 723 */ 724 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 725 726 /** 727 * @read_sensor: Read data from a sensor. 728 * &sensor: Sensor to read data from. 729 * &data: Sensor reading. 730 * &size: Size of &data. 731 */ 732 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 733 void *data, uint32_t *size); 734 735 /** 736 * @get_apu_thermal_limit: get apu core limit from smu 737 * &limit: current limit temperature in millidegrees Celsius 738 */ 739 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 740 741 /** 742 * @set_apu_thermal_limit: update all controllers with new limit 743 * &limit: limit temperature to be setted, in millidegrees Celsius 744 */ 745 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 746 747 /** 748 * @pre_display_config_changed: Prepare GPU for a display configuration 749 * change. 750 * 751 * Disable display tracking and pin memory clock speed to maximum. Used 752 * in display component synchronization. 753 */ 754 int (*pre_display_config_changed)(struct smu_context *smu); 755 756 /** 757 * @display_config_changed: Notify the SMU of the current display 758 * configuration. 759 * 760 * Allows SMU to properly track blanking periods for memory clock 761 * adjustment. Used in display component synchronization. 762 */ 763 int (*display_config_changed)(struct smu_context *smu); 764 765 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 766 767 /** 768 * @notify_smc_display_config: Applies display requirements to the 769 * current power state. 770 * 771 * Optimize deep sleep DCEFclk and mclk for the current display 772 * configuration. Used in display component synchronization. 773 */ 774 int (*notify_smc_display_config)(struct smu_context *smu); 775 776 /** 777 * @is_dpm_running: Check if DPM is running. 778 * 779 * Return: True if DPM is running, false otherwise. 780 */ 781 bool (*is_dpm_running)(struct smu_context *smu); 782 783 /** 784 * @get_fan_speed_pwm: Get the current fan speed in PWM. 785 */ 786 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 787 788 /** 789 * @get_fan_speed_rpm: Get the current fan speed in rpm. 790 */ 791 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 792 793 /** 794 * @set_watermarks_table: Configure and upload the watermarks tables to 795 * the SMU. 796 */ 797 int (*set_watermarks_table)(struct smu_context *smu, 798 struct pp_smu_wm_range_sets *clock_ranges); 799 800 /** 801 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 802 */ 803 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 804 805 /** 806 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 807 * &clocks_in_khz: Array of DPM levels. 808 * &num_states: Elements in &clocks_in_khz. 809 */ 810 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 811 812 /** 813 * @set_default_od_settings: Set the overdrive tables to defaults. 814 */ 815 int (*set_default_od_settings)(struct smu_context *smu); 816 817 /** 818 * @set_performance_level: Set a performance level. 819 */ 820 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 821 822 /** 823 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 824 * clock switching. 825 * 826 * Disabling this feature forces memory clock speed to maximum. 827 * Enabling sets the minimum memory clock capable of driving the 828 * current display configuration. 829 */ 830 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 831 832 /** 833 * @dump_pptable: Print the power play table to the system log. 834 */ 835 void (*dump_pptable)(struct smu_context *smu); 836 837 /** 838 * @get_power_limit: Get the device's power limits. 839 */ 840 int (*get_power_limit)(struct smu_context *smu, 841 uint32_t *current_power_limit, 842 uint32_t *default_power_limit, 843 uint32_t *max_power_limit, 844 uint32_t *min_power_limit); 845 846 /** 847 * @get_ppt_limit: Get the device's ppt limits. 848 */ 849 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 850 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 851 852 /** 853 * @set_df_cstate: Set data fabric cstate. 854 */ 855 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 856 857 /** 858 * @select_xgmi_plpd_policy: Select xgmi per-link power down policy. 859 */ 860 int (*select_xgmi_plpd_policy)(struct smu_context *smu, 861 enum pp_xgmi_plpd_mode mode); 862 863 /** 864 * @update_pcie_parameters: Update and upload the system's PCIe 865 * capabilites to the SMU. 866 * &pcie_gen_cap: Maximum allowed PCIe generation. 867 * &pcie_width_cap: Maximum allowed PCIe width. 868 */ 869 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 870 871 /** 872 * @i2c_init: Initialize i2c. 873 * 874 * The i2c bus is used internally by the SMU voltage regulators and 875 * other devices. The i2c's EEPROM also stores bad page tables on boards 876 * with ECC. 877 */ 878 int (*i2c_init)(struct smu_context *smu); 879 880 /** 881 * @i2c_fini: Tear down i2c. 882 */ 883 void (*i2c_fini)(struct smu_context *smu); 884 885 /** 886 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 887 */ 888 void (*get_unique_id)(struct smu_context *smu); 889 890 /** 891 * @get_dpm_clock_table: Get a copy of the DPM clock table. 892 * 893 * Used by display component in bandwidth and watermark calculations. 894 */ 895 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 896 897 /** 898 * @init_microcode: Request the SMU's firmware from the kernel. 899 */ 900 int (*init_microcode)(struct smu_context *smu); 901 902 /** 903 * @load_microcode: Load firmware onto the SMU. 904 */ 905 int (*load_microcode)(struct smu_context *smu); 906 907 /** 908 * @fini_microcode: Release the SMU's firmware. 909 */ 910 void (*fini_microcode)(struct smu_context *smu); 911 912 /** 913 * @init_smc_tables: Initialize the SMU tables. 914 */ 915 int (*init_smc_tables)(struct smu_context *smu); 916 917 /** 918 * @fini_smc_tables: Release the SMU tables. 919 */ 920 int (*fini_smc_tables)(struct smu_context *smu); 921 922 /** 923 * @init_power: Initialize the power gate table context. 924 */ 925 int (*init_power)(struct smu_context *smu); 926 927 /** 928 * @fini_power: Release the power gate table context. 929 */ 930 int (*fini_power)(struct smu_context *smu); 931 932 /** 933 * @check_fw_status: Check the SMU's firmware status. 934 * 935 * Return: Zero if check passes, negative errno on failure. 936 */ 937 int (*check_fw_status)(struct smu_context *smu); 938 939 /** 940 * @set_mp1_state: put SMU into a correct state for comming 941 * resume from runpm or gpu reset. 942 */ 943 int (*set_mp1_state)(struct smu_context *smu, 944 enum pp_mp1_state mp1_state); 945 946 /** 947 * @setup_pptable: Initialize the power play table and populate it with 948 * default values. 949 */ 950 int (*setup_pptable)(struct smu_context *smu); 951 952 /** 953 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 954 */ 955 int (*get_vbios_bootup_values)(struct smu_context *smu); 956 957 /** 958 * @check_fw_version: Print driver and SMU interface versions to the 959 * system log. 960 * 961 * Interface mismatch is not a critical failure. 962 */ 963 int (*check_fw_version)(struct smu_context *smu); 964 965 /** 966 * @powergate_sdma: Power up/down system direct memory access. 967 */ 968 int (*powergate_sdma)(struct smu_context *smu, bool gate); 969 970 /** 971 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 972 * gating. 973 */ 974 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 975 976 /** 977 * @write_pptable: Write the power play table to the SMU. 978 */ 979 int (*write_pptable)(struct smu_context *smu); 980 981 /** 982 * @set_driver_table_location: Send the location of the driver table to 983 * the SMU. 984 */ 985 int (*set_driver_table_location)(struct smu_context *smu); 986 987 /** 988 * @set_tool_table_location: Send the location of the tool table to the 989 * SMU. 990 */ 991 int (*set_tool_table_location)(struct smu_context *smu); 992 993 /** 994 * @notify_memory_pool_location: Send the location of the memory pool to 995 * the SMU. 996 */ 997 int (*notify_memory_pool_location)(struct smu_context *smu); 998 999 /** 1000 * @system_features_control: Enable/disable all SMU features. 1001 */ 1002 int (*system_features_control)(struct smu_context *smu, bool en); 1003 1004 /** 1005 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1006 * &msg: Type of message. 1007 * ¶m: Message parameter. 1008 * &read_arg: SMU response (optional). 1009 */ 1010 int (*send_smc_msg_with_param)(struct smu_context *smu, 1011 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1012 1013 /** 1014 * @send_smc_msg: Send a message to the SMU. 1015 * &msg: Type of message. 1016 * &read_arg: SMU response (optional). 1017 */ 1018 int (*send_smc_msg)(struct smu_context *smu, 1019 enum smu_message_type msg, 1020 uint32_t *read_arg); 1021 1022 /** 1023 * @init_display_count: Notify the SMU of the number of display 1024 * components in current display configuration. 1025 */ 1026 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1027 1028 /** 1029 * @set_allowed_mask: Notify the SMU of the features currently allowed 1030 * by the driver. 1031 */ 1032 int (*set_allowed_mask)(struct smu_context *smu); 1033 1034 /** 1035 * @get_enabled_mask: Get a mask of features that are currently enabled 1036 * on the SMU. 1037 * &feature_mask: Enabled feature mask. 1038 */ 1039 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1040 1041 /** 1042 * @feature_is_enabled: Test if a feature is enabled. 1043 * 1044 * Return: One if enabled, zero if disabled. 1045 */ 1046 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1047 1048 /** 1049 * @disable_all_features_with_exception: Disable all features with 1050 * exception to those in &mask. 1051 */ 1052 int (*disable_all_features_with_exception)(struct smu_context *smu, 1053 enum smu_feature_mask mask); 1054 1055 /** 1056 * @notify_display_change: General interface call to let SMU know about DC change 1057 */ 1058 int (*notify_display_change)(struct smu_context *smu); 1059 1060 /** 1061 * @set_power_limit: Set power limit in watts. 1062 */ 1063 int (*set_power_limit)(struct smu_context *smu, 1064 enum smu_ppt_limit_type limit_type, 1065 uint32_t limit); 1066 1067 /** 1068 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1069 * table with values from the SMU. 1070 */ 1071 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1072 1073 /** 1074 * @enable_thermal_alert: Enable thermal alert interrupts. 1075 */ 1076 int (*enable_thermal_alert)(struct smu_context *smu); 1077 1078 /** 1079 * @disable_thermal_alert: Disable thermal alert interrupts. 1080 */ 1081 int (*disable_thermal_alert)(struct smu_context *smu); 1082 1083 /** 1084 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1085 * clock speed in MHz. 1086 */ 1087 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1088 1089 /** 1090 * @display_clock_voltage_request: Set a hard minimum frequency 1091 * for a clock domain. 1092 */ 1093 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1094 pp_display_clock_request 1095 *clock_req); 1096 1097 /** 1098 * @get_fan_control_mode: Get the current fan control mode. 1099 */ 1100 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1101 1102 /** 1103 * @set_fan_control_mode: Set the fan control mode. 1104 */ 1105 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1106 1107 /** 1108 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1109 */ 1110 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1111 1112 /** 1113 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1114 */ 1115 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1116 1117 /** 1118 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1119 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1120 */ 1121 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1122 1123 /** 1124 * @gfx_off_control: Enable/disable graphics engine poweroff. 1125 */ 1126 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1127 1128 1129 /** 1130 * @get_gfx_off_status: Get graphics engine poweroff status. 1131 * 1132 * Return: 1133 * 0 - GFXOFF(default). 1134 * 1 - Transition out of GFX State. 1135 * 2 - Not in GFXOFF. 1136 * 3 - Transition into GFXOFF. 1137 */ 1138 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1139 1140 /** 1141 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1142 * query since system power-up 1143 */ 1144 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1145 1146 /** 1147 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1148 */ 1149 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1150 1151 /** 1152 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1153 */ 1154 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1155 1156 /** 1157 * @register_irq_handler: Register interupt request handlers. 1158 */ 1159 int (*register_irq_handler)(struct smu_context *smu); 1160 1161 /** 1162 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1163 */ 1164 int (*set_azalia_d3_pme)(struct smu_context *smu); 1165 1166 /** 1167 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1168 * clock speeds table. 1169 * 1170 * Provides a way for the display component (DC) to get the max 1171 * sustainable clocks from the SMU. 1172 */ 1173 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1174 1175 /** 1176 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1177 */ 1178 bool (*baco_is_support)(struct smu_context *smu); 1179 1180 /** 1181 * @baco_get_state: Get the current BACO state. 1182 * 1183 * Return: Current BACO state. 1184 */ 1185 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1186 1187 /** 1188 * @baco_set_state: Enter/exit BACO. 1189 */ 1190 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1191 1192 /** 1193 * @baco_enter: Enter BACO. 1194 */ 1195 int (*baco_enter)(struct smu_context *smu); 1196 1197 /** 1198 * @baco_exit: Exit Baco. 1199 */ 1200 int (*baco_exit)(struct smu_context *smu); 1201 1202 /** 1203 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1204 */ 1205 bool (*mode1_reset_is_support)(struct smu_context *smu); 1206 /** 1207 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1208 */ 1209 bool (*mode2_reset_is_support)(struct smu_context *smu); 1210 1211 /** 1212 * @mode1_reset: Perform mode1 reset. 1213 * 1214 * Complete GPU reset. 1215 */ 1216 int (*mode1_reset)(struct smu_context *smu); 1217 1218 /** 1219 * @mode2_reset: Perform mode2 reset. 1220 * 1221 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1222 * IPs reset varies by asic. 1223 */ 1224 int (*mode2_reset)(struct smu_context *smu); 1225 /* for gfx feature enablement after mode2 reset */ 1226 int (*enable_gfx_features)(struct smu_context *smu); 1227 1228 /** 1229 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1230 * domain in MHz. 1231 */ 1232 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1233 1234 /** 1235 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1236 * domain in MHz. 1237 */ 1238 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1239 1240 /** 1241 * @set_power_source: Notify the SMU of the current power source. 1242 */ 1243 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1244 1245 /** 1246 * @log_thermal_throttling_event: Print a thermal throttling warning to 1247 * the system's log. 1248 */ 1249 void (*log_thermal_throttling_event)(struct smu_context *smu); 1250 1251 /** 1252 * @get_pp_feature_mask: Print a human readable table of enabled 1253 * features to buffer. 1254 */ 1255 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1256 1257 /** 1258 * @set_pp_feature_mask: Request the SMU enable/disable features to 1259 * match those enabled in &new_mask. 1260 */ 1261 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1262 1263 /** 1264 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1265 * 1266 * Return: Size of &table 1267 */ 1268 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1269 1270 /** 1271 * @get_pm_metrics: Get one snapshot of power management metrics from 1272 * PMFW. 1273 * 1274 * Return: Size of the metrics sample 1275 */ 1276 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1277 size_t size); 1278 1279 /** 1280 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1281 */ 1282 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1283 1284 /** 1285 * @gfx_ulv_control: Enable/disable ultra low voltage. 1286 */ 1287 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1288 1289 /** 1290 * @deep_sleep_control: Enable/disable deep sleep. 1291 */ 1292 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1293 1294 /** 1295 * @get_fan_parameters: Get fan parameters. 1296 * 1297 * Get maximum fan speed from the power play table. 1298 */ 1299 int (*get_fan_parameters)(struct smu_context *smu); 1300 1301 /** 1302 * @post_init: Helper function for asic specific workarounds. 1303 */ 1304 int (*post_init)(struct smu_context *smu); 1305 1306 /** 1307 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1308 */ 1309 void (*interrupt_work)(struct smu_context *smu); 1310 1311 /** 1312 * @gpo_control: Enable/disable graphics power optimization if supported. 1313 */ 1314 int (*gpo_control)(struct smu_context *smu, bool enablement); 1315 1316 /** 1317 * @gfx_state_change_set: Send the current graphics state to the SMU. 1318 */ 1319 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1320 1321 /** 1322 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1323 * parameters to defaults. 1324 */ 1325 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1326 1327 /** 1328 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1329 */ 1330 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1331 1332 /** 1333 * @wait_for_event: Wait for events from SMU. 1334 */ 1335 int (*wait_for_event)(struct smu_context *smu, 1336 enum smu_event_type event, uint64_t event_arg); 1337 1338 /** 1339 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1340 * of SMUBUS table. 1341 */ 1342 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1343 1344 /** 1345 * @get_ecc_table: message SMU to get ECC INFO table. 1346 */ 1347 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1348 1349 1350 /** 1351 * @stb_collect_info: Collects Smart Trace Buffers data. 1352 */ 1353 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1354 1355 /** 1356 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1357 */ 1358 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1359 1360 /** 1361 * @set_config_table: Apply the input DriverSmuConfig table settings. 1362 */ 1363 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1364 1365 /** 1366 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1367 * of SMUBUS table. 1368 */ 1369 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1370 1371 /** 1372 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1373 */ 1374 int (*init_pptable_microcode)(struct smu_context *smu); 1375 1376 /** 1377 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1378 * management. 1379 */ 1380 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1381 1382 /** 1383 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1384 * management. 1385 */ 1386 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1387 1388 /** 1389 * @notify_rlc_state: Notify RLC power state to SMU. 1390 */ 1391 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1392 1393 /** 1394 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1395 */ 1396 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1397 1398 /** 1399 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1400 */ 1401 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1402 1403 /** 1404 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1405 */ 1406 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1407 struct freq_band_range *exclusion_ranges); 1408 }; 1409 1410 typedef enum { 1411 METRICS_CURR_GFXCLK, 1412 METRICS_CURR_SOCCLK, 1413 METRICS_CURR_UCLK, 1414 METRICS_CURR_VCLK, 1415 METRICS_CURR_VCLK1, 1416 METRICS_CURR_DCLK, 1417 METRICS_CURR_DCLK1, 1418 METRICS_CURR_FCLK, 1419 METRICS_CURR_DCEFCLK, 1420 METRICS_AVERAGE_CPUCLK, 1421 METRICS_AVERAGE_GFXCLK, 1422 METRICS_AVERAGE_SOCCLK, 1423 METRICS_AVERAGE_FCLK, 1424 METRICS_AVERAGE_UCLK, 1425 METRICS_AVERAGE_VCLK, 1426 METRICS_AVERAGE_DCLK, 1427 METRICS_AVERAGE_VCLK1, 1428 METRICS_AVERAGE_DCLK1, 1429 METRICS_AVERAGE_GFXACTIVITY, 1430 METRICS_AVERAGE_MEMACTIVITY, 1431 METRICS_AVERAGE_VCNACTIVITY, 1432 METRICS_AVERAGE_SOCKETPOWER, 1433 METRICS_TEMPERATURE_EDGE, 1434 METRICS_TEMPERATURE_HOTSPOT, 1435 METRICS_TEMPERATURE_MEM, 1436 METRICS_TEMPERATURE_VRGFX, 1437 METRICS_TEMPERATURE_VRSOC, 1438 METRICS_TEMPERATURE_VRMEM, 1439 METRICS_THROTTLER_STATUS, 1440 METRICS_CURR_FANSPEED, 1441 METRICS_VOLTAGE_VDDSOC, 1442 METRICS_VOLTAGE_VDDGFX, 1443 METRICS_SS_APU_SHARE, 1444 METRICS_SS_DGPU_SHARE, 1445 METRICS_UNIQUE_ID_UPPER32, 1446 METRICS_UNIQUE_ID_LOWER32, 1447 METRICS_PCIE_RATE, 1448 METRICS_PCIE_WIDTH, 1449 METRICS_CURR_FANPWM, 1450 METRICS_CURR_SOCKETPOWER, 1451 METRICS_AVERAGE_VPECLK, 1452 METRICS_AVERAGE_IPUCLK, 1453 METRICS_AVERAGE_MPIPUCLK, 1454 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1455 METRICS_THROTTLER_RESIDENCY_SPL, 1456 METRICS_THROTTLER_RESIDENCY_FPPT, 1457 METRICS_THROTTLER_RESIDENCY_SPPT, 1458 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1459 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1460 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1461 } MetricsMember_t; 1462 1463 enum smu_cmn2asic_mapping_type { 1464 CMN2ASIC_MAPPING_MSG, 1465 CMN2ASIC_MAPPING_CLK, 1466 CMN2ASIC_MAPPING_FEATURE, 1467 CMN2ASIC_MAPPING_TABLE, 1468 CMN2ASIC_MAPPING_PWR, 1469 CMN2ASIC_MAPPING_WORKLOAD, 1470 }; 1471 1472 enum smu_baco_seq { 1473 BACO_SEQ_BACO = 0, 1474 BACO_SEQ_MSR, 1475 BACO_SEQ_BAMACO, 1476 BACO_SEQ_ULPS, 1477 BACO_SEQ_COUNT, 1478 }; 1479 1480 #define MSG_MAP(msg, index, valid_in_vf) \ 1481 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1482 1483 #define CLK_MAP(clk, index) \ 1484 [SMU_##clk] = {1, (index)} 1485 1486 #define FEA_MAP(fea) \ 1487 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1488 1489 #define FEA_MAP_REVERSE(fea) \ 1490 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1491 1492 #define FEA_MAP_HALF_REVERSE(fea) \ 1493 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1494 1495 #define TAB_MAP(tab) \ 1496 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1497 1498 #define TAB_MAP_VALID(tab) \ 1499 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1500 1501 #define TAB_MAP_INVALID(tab) \ 1502 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1503 1504 #define PWR_MAP(tab) \ 1505 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1506 1507 #define WORKLOAD_MAP(profile, workload) \ 1508 [profile] = {1, (workload)} 1509 1510 /** 1511 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1512 * 1513 * @dst: Pointer to destination struct 1514 * @first_dst_member: The member name in @dst where the overwrite begins 1515 * @last_dst_member: The member name in @dst where the overwrite ends after 1516 * @src: Pointer to the source struct 1517 * @first_src_member: The member name in @src where the copy begins 1518 * 1519 */ 1520 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1521 src, first_src_member) \ 1522 ({ \ 1523 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1524 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1525 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1526 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1527 __dst_offset; \ 1528 BUILD_BUG_ON(__src_size != __dst_size); \ 1529 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1530 (u8 *)(src) + __src_offset, \ 1531 __dst_size); \ 1532 }) 1533 1534 typedef struct { 1535 uint16_t LowFreq; 1536 uint16_t HighFreq; 1537 } WifiOneBand_t; 1538 1539 typedef struct { 1540 uint32_t WifiBandEntryNum; 1541 WifiOneBand_t WifiBandEntry[11]; 1542 uint32_t MmHubPadding[8]; 1543 } WifiBandEntryTable_t; 1544 1545 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1546 int smu_get_power_limit(void *handle, 1547 uint32_t *limit, 1548 enum pp_power_limit_level pp_limit_level, 1549 enum pp_power_type pp_power_type); 1550 1551 bool smu_mode1_reset_is_support(struct smu_context *smu); 1552 bool smu_mode2_reset_is_support(struct smu_context *smu); 1553 int smu_mode1_reset(struct smu_context *smu); 1554 1555 extern const struct amd_ip_funcs smu_ip_funcs; 1556 1557 bool is_support_sw_smu(struct amdgpu_device *adev); 1558 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1559 int smu_write_watermarks_table(struct smu_context *smu); 1560 1561 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1562 uint32_t *min, uint32_t *max); 1563 1564 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1565 uint32_t min, uint32_t max); 1566 1567 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1568 1569 int smu_set_ac_dc(struct smu_context *smu); 1570 1571 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1572 enum pp_xgmi_plpd_mode mode); 1573 1574 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1575 1576 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1577 1578 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1579 1580 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1581 1582 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1583 1584 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1585 uint64_t event_arg); 1586 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1587 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1588 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1589 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1590 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1591 #endif 1592 #endif 1593