1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/scatterlist.h> 25 #include <linux/sched.h> 26 #include <linux/slab.h> 27 #include <linux/units.h> 28 29 #define I2C_RS_TRANSFER (1 << 4) 30 #define I2C_ARB_LOST (1 << 3) 31 #define I2C_HS_NACKERR (1 << 2) 32 #define I2C_ACKERR (1 << 1) 33 #define I2C_TRANSAC_COMP (1 << 0) 34 #define I2C_TRANSAC_START (1 << 0) 35 #define I2C_RS_MUL_CNFG (1 << 15) 36 #define I2C_RS_MUL_TRIG (1 << 14) 37 #define I2C_DCM_DISABLE 0x0000 38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 40 #define I2C_SOFT_RST 0x0001 41 #define I2C_HANDSHAKE_RST 0x0020 42 #define I2C_FIFO_ADDR_CLR 0x0001 43 #define I2C_DELAY_LEN 0x0002 44 #define I2C_ST_START_CON 0x8001 45 #define I2C_FS_START_CON 0x1800 46 #define I2C_TIME_CLR_VALUE 0x0000 47 #define I2C_TIME_DEFAULT_VALUE 0x0003 48 #define I2C_WRRD_TRANAC_VALUE 0x0002 49 #define I2C_RD_TRANAC_VALUE 0x0001 50 #define I2C_SCL_MIS_COMP_VALUE 0x0000 51 #define I2C_CHN_CLR_FLAG 0x0000 52 #define I2C_RELIABILITY 0x0010 53 #define I2C_DMAACK_ENABLE 0x0008 54 55 #define I2C_DMA_CON_TX 0x0000 56 #define I2C_DMA_CON_RX 0x0001 57 #define I2C_DMA_ASYNC_MODE 0x0004 58 #define I2C_DMA_SKIP_CONFIG 0x0010 59 #define I2C_DMA_DIR_CHANGE 0x0200 60 #define I2C_DMA_START_EN 0x0001 61 #define I2C_DMA_INT_FLAG_NONE 0x0000 62 #define I2C_DMA_CLR_FLAG 0x0000 63 #define I2C_DMA_WARM_RST 0x0001 64 #define I2C_DMA_HARD_RST 0x0002 65 #define I2C_DMA_HANDSHAKE_RST 0x0004 66 67 #define MAX_SAMPLE_CNT_DIV 8 68 #define MAX_STEP_CNT_DIV 64 69 #define MAX_CLOCK_DIV_8BITS 256 70 #define MAX_CLOCK_DIV_5BITS 32 71 #define MAX_HS_STEP_CNT_DIV 8 72 #define I2C_STANDARD_MODE_BUFFER (1000 / 3) 73 #define I2C_FAST_MODE_BUFFER (300 / 3) 74 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) 75 76 #define I2C_CONTROL_RS (0x1 << 1) 77 #define I2C_CONTROL_DMA_EN (0x1 << 2) 78 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 79 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 80 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 81 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 82 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 83 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 84 #define I2C_CONTROL_WRAPPER (0x1 << 0) 85 86 #define I2C_DRV_NAME "i2c-mt65xx" 87 88 /** 89 * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C 90 * 91 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus 92 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA 93 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC 94 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c 95 * @I2C_MT65XX_CLK_MAX: Number of supported clocks 96 */ 97 enum i2c_mt65xx_clks { 98 I2C_MT65XX_CLK_MAIN = 0, 99 I2C_MT65XX_CLK_DMA, 100 I2C_MT65XX_CLK_PMIC, 101 I2C_MT65XX_CLK_ARB, 102 I2C_MT65XX_CLK_MAX 103 }; 104 105 static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = { 106 "main", "dma", "pmic", "arb" 107 }; 108 109 enum DMA_REGS_OFFSET { 110 OFFSET_INT_FLAG = 0x0, 111 OFFSET_INT_EN = 0x04, 112 OFFSET_EN = 0x08, 113 OFFSET_RST = 0x0c, 114 OFFSET_CON = 0x18, 115 OFFSET_TX_MEM_ADDR = 0x1c, 116 OFFSET_RX_MEM_ADDR = 0x20, 117 OFFSET_TX_LEN = 0x24, 118 OFFSET_RX_LEN = 0x28, 119 OFFSET_TX_4G_MODE = 0x54, 120 OFFSET_RX_4G_MODE = 0x58, 121 }; 122 123 enum i2c_trans_st_rs { 124 I2C_TRANS_STOP = 0, 125 I2C_TRANS_REPEATED_START, 126 }; 127 128 enum mtk_trans_op { 129 I2C_MASTER_WR = 1, 130 I2C_MASTER_RD, 131 I2C_MASTER_WRRD, 132 }; 133 134 enum I2C_REGS_OFFSET { 135 OFFSET_DATA_PORT, 136 OFFSET_SLAVE_ADDR, 137 OFFSET_INTR_MASK, 138 OFFSET_INTR_STAT, 139 OFFSET_CONTROL, 140 OFFSET_TRANSFER_LEN, 141 OFFSET_TRANSAC_LEN, 142 OFFSET_DELAY_LEN, 143 OFFSET_TIMING, 144 OFFSET_START, 145 OFFSET_EXT_CONF, 146 OFFSET_FIFO_STAT, 147 OFFSET_FIFO_THRESH, 148 OFFSET_FIFO_ADDR_CLR, 149 OFFSET_IO_CONFIG, 150 OFFSET_RSV_DEBUG, 151 OFFSET_HS, 152 OFFSET_SOFTRESET, 153 OFFSET_DCM_EN, 154 OFFSET_MULTI_DMA, 155 OFFSET_PATH_DIR, 156 OFFSET_DEBUGSTAT, 157 OFFSET_DEBUGCTRL, 158 OFFSET_TRANSFER_LEN_AUX, 159 OFFSET_CLOCK_DIV, 160 OFFSET_LTIMING, 161 OFFSET_SCL_HIGH_LOW_RATIO, 162 OFFSET_HS_SCL_HIGH_LOW_RATIO, 163 OFFSET_SCL_MIS_COMP_POINT, 164 OFFSET_STA_STO_AC_TIMING, 165 OFFSET_HS_STA_STO_AC_TIMING, 166 OFFSET_SDA_TIMING, 167 }; 168 169 static const u16 mt_i2c_regs_v1[] = { 170 [OFFSET_DATA_PORT] = 0x0, 171 [OFFSET_SLAVE_ADDR] = 0x4, 172 [OFFSET_INTR_MASK] = 0x8, 173 [OFFSET_INTR_STAT] = 0xc, 174 [OFFSET_CONTROL] = 0x10, 175 [OFFSET_TRANSFER_LEN] = 0x14, 176 [OFFSET_TRANSAC_LEN] = 0x18, 177 [OFFSET_DELAY_LEN] = 0x1c, 178 [OFFSET_TIMING] = 0x20, 179 [OFFSET_START] = 0x24, 180 [OFFSET_EXT_CONF] = 0x28, 181 [OFFSET_FIFO_STAT] = 0x30, 182 [OFFSET_FIFO_THRESH] = 0x34, 183 [OFFSET_FIFO_ADDR_CLR] = 0x38, 184 [OFFSET_IO_CONFIG] = 0x40, 185 [OFFSET_RSV_DEBUG] = 0x44, 186 [OFFSET_HS] = 0x48, 187 [OFFSET_SOFTRESET] = 0x50, 188 [OFFSET_DCM_EN] = 0x54, 189 [OFFSET_PATH_DIR] = 0x60, 190 [OFFSET_DEBUGSTAT] = 0x64, 191 [OFFSET_DEBUGCTRL] = 0x68, 192 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 193 [OFFSET_CLOCK_DIV] = 0x70, 194 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 195 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 196 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 197 [OFFSET_STA_STO_AC_TIMING] = 0x80, 198 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 199 [OFFSET_SDA_TIMING] = 0x88, 200 }; 201 202 static const u16 mt_i2c_regs_v2[] = { 203 [OFFSET_DATA_PORT] = 0x0, 204 [OFFSET_SLAVE_ADDR] = 0x4, 205 [OFFSET_INTR_MASK] = 0x8, 206 [OFFSET_INTR_STAT] = 0xc, 207 [OFFSET_CONTROL] = 0x10, 208 [OFFSET_TRANSFER_LEN] = 0x14, 209 [OFFSET_TRANSAC_LEN] = 0x18, 210 [OFFSET_DELAY_LEN] = 0x1c, 211 [OFFSET_TIMING] = 0x20, 212 [OFFSET_START] = 0x24, 213 [OFFSET_EXT_CONF] = 0x28, 214 [OFFSET_LTIMING] = 0x2c, 215 [OFFSET_HS] = 0x30, 216 [OFFSET_IO_CONFIG] = 0x34, 217 [OFFSET_FIFO_ADDR_CLR] = 0x38, 218 [OFFSET_SDA_TIMING] = 0x3c, 219 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 220 [OFFSET_CLOCK_DIV] = 0x48, 221 [OFFSET_SOFTRESET] = 0x50, 222 [OFFSET_MULTI_DMA] = 0x8c, 223 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 224 [OFFSET_DEBUGSTAT] = 0xe4, 225 [OFFSET_DEBUGCTRL] = 0xe8, 226 [OFFSET_FIFO_STAT] = 0xf4, 227 [OFFSET_FIFO_THRESH] = 0xf8, 228 [OFFSET_DCM_EN] = 0xf88, 229 }; 230 231 static const u16 mt_i2c_regs_v3[] = { 232 [OFFSET_DATA_PORT] = 0x0, 233 [OFFSET_INTR_MASK] = 0x8, 234 [OFFSET_INTR_STAT] = 0xc, 235 [OFFSET_CONTROL] = 0x10, 236 [OFFSET_TRANSFER_LEN] = 0x14, 237 [OFFSET_TRANSAC_LEN] = 0x18, 238 [OFFSET_DELAY_LEN] = 0x1c, 239 [OFFSET_TIMING] = 0x20, 240 [OFFSET_START] = 0x24, 241 [OFFSET_EXT_CONF] = 0x28, 242 [OFFSET_LTIMING] = 0x2c, 243 [OFFSET_HS] = 0x30, 244 [OFFSET_IO_CONFIG] = 0x34, 245 [OFFSET_FIFO_ADDR_CLR] = 0x38, 246 [OFFSET_SDA_TIMING] = 0x3c, 247 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 248 [OFFSET_CLOCK_DIV] = 0x48, 249 [OFFSET_SOFTRESET] = 0x50, 250 [OFFSET_MULTI_DMA] = 0x8c, 251 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 252 [OFFSET_SLAVE_ADDR] = 0x94, 253 [OFFSET_DEBUGSTAT] = 0xe4, 254 [OFFSET_DEBUGCTRL] = 0xe8, 255 [OFFSET_FIFO_STAT] = 0xf4, 256 [OFFSET_FIFO_THRESH] = 0xf8, 257 [OFFSET_DCM_EN] = 0xf88, 258 }; 259 260 struct mtk_i2c_compatible { 261 const struct i2c_adapter_quirks *quirks; 262 const u16 *regs; 263 unsigned char pmic_i2c: 1; 264 unsigned char dcm: 1; 265 unsigned char auto_restart: 1; 266 unsigned char aux_len_reg: 1; 267 unsigned char timing_adjust: 1; 268 unsigned char dma_sync: 1; 269 unsigned char ltiming_adjust: 1; 270 unsigned char apdma_sync: 1; 271 unsigned char max_dma_support; 272 }; 273 274 struct mtk_i2c_ac_timing { 275 u16 htiming; 276 u16 ltiming; 277 u16 hs; 278 u16 ext; 279 u16 inter_clk_div; 280 u16 scl_hl_ratio; 281 u16 hs_scl_hl_ratio; 282 u16 sta_stop; 283 u16 hs_sta_stop; 284 u16 sda_timing; 285 }; 286 287 struct mtk_i2c { 288 struct i2c_adapter adap; /* i2c host adapter */ 289 struct device *dev; 290 struct completion msg_complete; 291 struct i2c_timings timing_info; 292 293 /* set in i2c probe */ 294 void __iomem *base; /* i2c base addr */ 295 void __iomem *pdmabase; /* dma base address*/ 296 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ 297 bool have_pmic; /* can use i2c pins from PMIC */ 298 bool use_push_pull; /* IO config push-pull mode */ 299 300 u16 irq_stat; /* interrupt status */ 301 unsigned int clk_src_div; 302 unsigned int speed_hz; /* The speed in transfer */ 303 enum mtk_trans_op op; 304 u16 timing_reg; 305 u16 high_speed_reg; 306 u16 ltiming_reg; 307 unsigned char auto_restart; 308 bool ignore_restart_irq; 309 struct mtk_i2c_ac_timing ac_timing; 310 const struct mtk_i2c_compatible *dev_comp; 311 }; 312 313 /** 314 * struct i2c_spec_values: 315 * @min_low_ns: min LOW period of the SCL clock 316 * @min_su_sta_ns: min set-up time for a repeated START condition 317 * @max_hd_dat_ns: max data hold time 318 * @min_su_dat_ns: min data set-up time 319 */ 320 struct i2c_spec_values { 321 unsigned int min_low_ns; 322 unsigned int min_su_sta_ns; 323 unsigned int max_hd_dat_ns; 324 unsigned int min_su_dat_ns; 325 }; 326 327 static const struct i2c_spec_values standard_mode_spec = { 328 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 329 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 330 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 331 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 332 }; 333 334 static const struct i2c_spec_values fast_mode_spec = { 335 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 336 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 337 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 338 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 339 }; 340 341 static const struct i2c_spec_values fast_mode_plus_spec = { 342 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 343 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 344 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 345 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 346 }; 347 348 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 349 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 350 .max_num_msgs = 1, 351 .max_write_len = 255, 352 .max_read_len = 255, 353 .max_comb_1st_msg_len = 255, 354 .max_comb_2nd_msg_len = 31, 355 }; 356 357 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 358 .max_num_msgs = 255, 359 }; 360 361 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 362 .flags = I2C_AQ_NO_ZERO_LEN, 363 }; 364 365 static const struct mtk_i2c_compatible mt2712_compat = { 366 .regs = mt_i2c_regs_v1, 367 .pmic_i2c = 0, 368 .dcm = 1, 369 .auto_restart = 1, 370 .aux_len_reg = 1, 371 .timing_adjust = 1, 372 .dma_sync = 0, 373 .ltiming_adjust = 0, 374 .apdma_sync = 0, 375 .max_dma_support = 33, 376 }; 377 378 static const struct mtk_i2c_compatible mt6577_compat = { 379 .quirks = &mt6577_i2c_quirks, 380 .regs = mt_i2c_regs_v1, 381 .pmic_i2c = 0, 382 .dcm = 1, 383 .auto_restart = 0, 384 .aux_len_reg = 0, 385 .timing_adjust = 0, 386 .dma_sync = 0, 387 .ltiming_adjust = 0, 388 .apdma_sync = 0, 389 .max_dma_support = 32, 390 }; 391 392 static const struct mtk_i2c_compatible mt6589_compat = { 393 .quirks = &mt6577_i2c_quirks, 394 .regs = mt_i2c_regs_v1, 395 .pmic_i2c = 1, 396 .dcm = 0, 397 .auto_restart = 0, 398 .aux_len_reg = 0, 399 .timing_adjust = 0, 400 .dma_sync = 0, 401 .ltiming_adjust = 0, 402 .apdma_sync = 0, 403 .max_dma_support = 32, 404 }; 405 406 static const struct mtk_i2c_compatible mt7622_compat = { 407 .quirks = &mt7622_i2c_quirks, 408 .regs = mt_i2c_regs_v1, 409 .pmic_i2c = 0, 410 .dcm = 1, 411 .auto_restart = 1, 412 .aux_len_reg = 1, 413 .timing_adjust = 0, 414 .dma_sync = 0, 415 .ltiming_adjust = 0, 416 .apdma_sync = 0, 417 .max_dma_support = 32, 418 }; 419 420 static const struct mtk_i2c_compatible mt8168_compat = { 421 .regs = mt_i2c_regs_v1, 422 .pmic_i2c = 0, 423 .dcm = 1, 424 .auto_restart = 1, 425 .aux_len_reg = 1, 426 .timing_adjust = 1, 427 .dma_sync = 1, 428 .ltiming_adjust = 0, 429 .apdma_sync = 0, 430 .max_dma_support = 33, 431 }; 432 433 static const struct mtk_i2c_compatible mt7981_compat = { 434 .regs = mt_i2c_regs_v3, 435 .pmic_i2c = 0, 436 .dcm = 0, 437 .auto_restart = 1, 438 .aux_len_reg = 1, 439 .timing_adjust = 1, 440 .dma_sync = 1, 441 .ltiming_adjust = 1, 442 .max_dma_support = 33 443 }; 444 445 static const struct mtk_i2c_compatible mt7986_compat = { 446 .quirks = &mt7622_i2c_quirks, 447 .regs = mt_i2c_regs_v1, 448 .pmic_i2c = 0, 449 .dcm = 1, 450 .auto_restart = 1, 451 .aux_len_reg = 1, 452 .timing_adjust = 0, 453 .dma_sync = 1, 454 .ltiming_adjust = 0, 455 .max_dma_support = 32, 456 }; 457 458 static const struct mtk_i2c_compatible mt8173_compat = { 459 .regs = mt_i2c_regs_v1, 460 .pmic_i2c = 0, 461 .dcm = 1, 462 .auto_restart = 1, 463 .aux_len_reg = 1, 464 .timing_adjust = 0, 465 .dma_sync = 0, 466 .ltiming_adjust = 0, 467 .apdma_sync = 0, 468 .max_dma_support = 33, 469 }; 470 471 static const struct mtk_i2c_compatible mt8183_compat = { 472 .quirks = &mt8183_i2c_quirks, 473 .regs = mt_i2c_regs_v2, 474 .pmic_i2c = 0, 475 .dcm = 0, 476 .auto_restart = 1, 477 .aux_len_reg = 1, 478 .timing_adjust = 1, 479 .dma_sync = 1, 480 .ltiming_adjust = 1, 481 .apdma_sync = 0, 482 .max_dma_support = 33, 483 }; 484 485 static const struct mtk_i2c_compatible mt8186_compat = { 486 .regs = mt_i2c_regs_v2, 487 .pmic_i2c = 0, 488 .dcm = 0, 489 .auto_restart = 1, 490 .aux_len_reg = 1, 491 .timing_adjust = 1, 492 .dma_sync = 0, 493 .ltiming_adjust = 1, 494 .apdma_sync = 0, 495 .max_dma_support = 36, 496 }; 497 498 static const struct mtk_i2c_compatible mt8188_compat = { 499 .regs = mt_i2c_regs_v3, 500 .pmic_i2c = 0, 501 .dcm = 0, 502 .auto_restart = 1, 503 .aux_len_reg = 1, 504 .timing_adjust = 1, 505 .dma_sync = 0, 506 .ltiming_adjust = 1, 507 .apdma_sync = 1, 508 .max_dma_support = 36, 509 }; 510 511 static const struct mtk_i2c_compatible mt8192_compat = { 512 .quirks = &mt8183_i2c_quirks, 513 .regs = mt_i2c_regs_v2, 514 .pmic_i2c = 0, 515 .dcm = 0, 516 .auto_restart = 1, 517 .aux_len_reg = 1, 518 .timing_adjust = 1, 519 .dma_sync = 1, 520 .ltiming_adjust = 1, 521 .apdma_sync = 1, 522 .max_dma_support = 36, 523 }; 524 525 static const struct of_device_id mtk_i2c_of_match[] = { 526 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 527 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 528 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 529 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 530 { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat }, 531 { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, 532 { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, 533 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 534 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 535 { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, 536 { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat }, 537 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, 538 {} 539 }; 540 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 541 542 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 543 { 544 return readw(i2c->base + i2c->dev_comp->regs[reg]); 545 } 546 547 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 548 enum I2C_REGS_OFFSET reg) 549 { 550 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 551 } 552 553 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 554 { 555 u16 control_reg; 556 u16 intr_stat_reg; 557 u16 ext_conf_val; 558 559 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); 560 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 561 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); 562 563 if (i2c->dev_comp->apdma_sync) { 564 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); 565 udelay(10); 566 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 567 udelay(10); 568 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, 569 i2c->pdmabase + OFFSET_RST); 570 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, 571 OFFSET_SOFTRESET); 572 udelay(10); 573 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 574 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 575 } else { 576 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 577 udelay(50); 578 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 579 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 580 } 581 582 /* Set ioconfig */ 583 if (i2c->use_push_pull) 584 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 585 else 586 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 587 588 if (i2c->dev_comp->dcm) 589 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 590 591 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 592 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 593 if (i2c->dev_comp->ltiming_adjust) 594 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 595 596 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) 597 ext_conf_val = I2C_ST_START_CON; 598 else 599 ext_conf_val = I2C_FS_START_CON; 600 601 if (i2c->dev_comp->timing_adjust) { 602 ext_conf_val = i2c->ac_timing.ext; 603 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 604 OFFSET_CLOCK_DIV); 605 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 606 OFFSET_SCL_MIS_COMP_POINT); 607 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 608 OFFSET_SDA_TIMING); 609 610 if (i2c->dev_comp->ltiming_adjust) { 611 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 612 OFFSET_TIMING); 613 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 614 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 615 OFFSET_LTIMING); 616 } else { 617 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 618 OFFSET_SCL_HIGH_LOW_RATIO); 619 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 620 OFFSET_HS_SCL_HIGH_LOW_RATIO); 621 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 622 OFFSET_STA_STO_AC_TIMING); 623 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 624 OFFSET_HS_STA_STO_AC_TIMING); 625 } 626 } 627 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); 628 629 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 630 if (i2c->have_pmic) 631 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 632 633 control_reg = I2C_CONTROL_ACKERR_DET_EN | 634 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 635 if (i2c->dev_comp->dma_sync) 636 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 637 638 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 639 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 640 } 641 642 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 643 { 644 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 645 return &standard_mode_spec; 646 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 647 return &fast_mode_spec; 648 else 649 return &fast_mode_plus_spec; 650 } 651 652 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 653 { 654 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 655 return MAX_HS_STEP_CNT_DIV; 656 else 657 return MAX_STEP_CNT_DIV; 658 } 659 660 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, 661 unsigned int sample_cnt) 662 { 663 int clk_div_restri = 0; 664 665 if (i2c->dev_comp->ltiming_adjust == 0) 666 return 0; 667 668 if (sample_cnt == 1) { 669 if (i2c->ac_timing.inter_clk_div == 0) 670 clk_div_restri = 0; 671 else 672 clk_div_restri = 1; 673 } else { 674 if (i2c->ac_timing.inter_clk_div == 0) 675 clk_div_restri = -1; 676 else if (i2c->ac_timing.inter_clk_div == 1) 677 clk_div_restri = 0; 678 else 679 clk_div_restri = 1; 680 } 681 682 return clk_div_restri; 683 } 684 685 /* 686 * Check and Calculate i2c ac-timing 687 * 688 * Hardware design: 689 * sample_ns = (HZ_PER_GHZ * (sample_cnt + 1)) / clk_src 690 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 691 * 692 * Sample_ns is rounded down for xxx_cnt_div would be greater 693 * than the smallest spec. 694 * The sda_timing is chosen as the middle value between 695 * the largest and smallest. 696 */ 697 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 698 unsigned int clk_src, 699 unsigned int check_speed, 700 unsigned int step_cnt, 701 unsigned int sample_cnt) 702 { 703 const struct i2c_spec_values *spec; 704 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 705 unsigned int sda_max, sda_min, max_sta_cnt = 0x3f; 706 unsigned int clk_ns, sample_ns; 707 708 if (!i2c->dev_comp->timing_adjust) 709 return 0; 710 711 if (i2c->dev_comp->ltiming_adjust) 712 max_sta_cnt = 0x100; 713 714 spec = mtk_i2c_get_spec(check_speed); 715 716 sample_ns = div_u64(1ULL * HZ_PER_GHZ * (sample_cnt + 1), clk_src); 717 if (i2c->dev_comp->ltiming_adjust) 718 clk_ns = HZ_PER_GHZ / clk_src; 719 else 720 clk_ns = sample_ns / 2; 721 722 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + 723 i2c->timing_info.scl_int_delay_ns, clk_ns); 724 if (su_sta_cnt > max_sta_cnt) 725 return -1; 726 727 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 728 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 729 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 730 if (low_cnt > step_cnt) { 731 high_cnt = 2 * step_cnt - low_cnt; 732 } else { 733 high_cnt = step_cnt; 734 low_cnt = step_cnt; 735 } 736 } else { 737 return -2; 738 } 739 740 sda_max = spec->max_hd_dat_ns / sample_ns; 741 if (sda_max > low_cnt) 742 sda_max = 0; 743 744 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 745 if (sda_min < low_cnt) 746 sda_min = 0; 747 748 if (sda_min > sda_max) 749 return -3; 750 751 if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 752 if (i2c->dev_comp->ltiming_adjust) { 753 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 754 (sample_cnt << 12) | (high_cnt << 8); 755 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 756 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 757 (low_cnt << 9); 758 i2c->ac_timing.ext &= ~GENMASK(7, 1); 759 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 760 } else { 761 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 762 (high_cnt << 6) | low_cnt; 763 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 764 su_sta_cnt; 765 } 766 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 767 i2c->ac_timing.sda_timing |= (1 << 12) | 768 ((sda_max + sda_min) / 2) << 6; 769 } else { 770 if (i2c->dev_comp->ltiming_adjust) { 771 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 772 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 773 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 774 } else { 775 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 776 (high_cnt << 6) | low_cnt; 777 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 778 su_sta_cnt; 779 } 780 781 i2c->ac_timing.sda_timing = (1 << 12) | 782 (sda_max + sda_min) / 2; 783 } 784 785 return 0; 786 } 787 788 /* 789 * Calculate i2c port speed 790 * 791 * Hardware design: 792 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 793 * clock_div: fixed in hardware, but may be various in different SoCs 794 * 795 * The calculation want to pick the highest bus frequency that is still 796 * less than or equal to i2c->speed_hz. The calculation try to get 797 * sample_cnt and step_cn 798 */ 799 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 800 unsigned int target_speed, 801 unsigned int *timing_step_cnt, 802 unsigned int *timing_sample_cnt) 803 { 804 unsigned int step_cnt; 805 unsigned int sample_cnt; 806 unsigned int max_step_cnt; 807 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 808 unsigned int base_step_cnt; 809 unsigned int opt_div; 810 unsigned int best_mul; 811 unsigned int cnt_mul; 812 int ret = -EINVAL; 813 int clk_div_restri = 0; 814 815 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) 816 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; 817 818 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 819 base_step_cnt = max_step_cnt; 820 /* Find the best combination */ 821 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 822 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 823 824 /* Search for the best pair (sample_cnt, step_cnt) with 825 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 826 * 0 < step_cnt < max_step_cnt 827 * sample_cnt * step_cnt >= opt_div 828 * optimizing for sample_cnt * step_cnt being minimal 829 */ 830 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 831 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); 832 step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt); 833 cnt_mul = step_cnt * sample_cnt; 834 if (step_cnt > max_step_cnt) 835 continue; 836 837 if (cnt_mul < best_mul) { 838 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 839 target_speed, step_cnt - 1, sample_cnt - 1); 840 if (ret) 841 continue; 842 843 best_mul = cnt_mul; 844 base_sample_cnt = sample_cnt; 845 base_step_cnt = step_cnt; 846 if (best_mul == (opt_div + clk_div_restri)) 847 break; 848 } 849 } 850 851 if (ret) 852 return -EINVAL; 853 854 sample_cnt = base_sample_cnt; 855 step_cnt = base_step_cnt; 856 857 if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > 858 target_speed) { 859 /* In this case, hardware can't support such 860 * low i2c_bus_freq 861 */ 862 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 863 return -EINVAL; 864 } 865 866 *timing_step_cnt = step_cnt - 1; 867 *timing_sample_cnt = sample_cnt - 1; 868 869 return 0; 870 } 871 872 static void mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 873 { 874 unsigned int clk_src; 875 unsigned int step_cnt; 876 unsigned int sample_cnt; 877 unsigned int l_step_cnt; 878 unsigned int l_sample_cnt; 879 unsigned int target_speed; 880 unsigned int clk_div; 881 unsigned int max_clk_div; 882 int ret; 883 884 target_speed = i2c->speed_hz; 885 parent_clk /= i2c->clk_src_div; 886 887 if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) 888 max_clk_div = MAX_CLOCK_DIV_5BITS; 889 else if (i2c->dev_comp->timing_adjust) 890 max_clk_div = MAX_CLOCK_DIV_8BITS; 891 else 892 max_clk_div = 1; 893 894 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 895 clk_src = parent_clk / clk_div; 896 i2c->ac_timing.inter_clk_div = clk_div - 1; 897 898 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 899 /* Set master code speed register */ 900 ret = mtk_i2c_calculate_speed(i2c, clk_src, 901 I2C_MAX_FAST_MODE_FREQ, 902 &l_step_cnt, 903 &l_sample_cnt); 904 if (ret < 0) 905 continue; 906 907 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 908 909 /* Set the high speed mode register */ 910 ret = mtk_i2c_calculate_speed(i2c, clk_src, 911 target_speed, &step_cnt, 912 &sample_cnt); 913 if (ret < 0) 914 continue; 915 916 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 917 (sample_cnt << 12) | (step_cnt << 8); 918 919 if (i2c->dev_comp->ltiming_adjust) 920 i2c->ltiming_reg = 921 (l_sample_cnt << 6) | l_step_cnt | 922 (sample_cnt << 12) | (step_cnt << 9); 923 } else { 924 ret = mtk_i2c_calculate_speed(i2c, clk_src, 925 target_speed, &l_step_cnt, 926 &l_sample_cnt); 927 if (ret < 0) 928 continue; 929 930 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 931 932 /* Disable the high speed transaction */ 933 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 934 935 if (i2c->dev_comp->ltiming_adjust) 936 i2c->ltiming_reg = 937 (l_sample_cnt << 6) | l_step_cnt; 938 } 939 940 break; 941 } 942 } 943 944 static void i2c_dump_register(struct mtk_i2c *i2c) 945 { 946 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", 947 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), 948 mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); 949 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", 950 mtk_i2c_readw(i2c, OFFSET_INTR_STAT), 951 mtk_i2c_readw(i2c, OFFSET_CONTROL)); 952 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", 953 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), 954 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); 955 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", 956 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), 957 mtk_i2c_readw(i2c, OFFSET_TIMING)); 958 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", 959 mtk_i2c_readw(i2c, OFFSET_START), 960 mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); 961 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", 962 mtk_i2c_readw(i2c, OFFSET_HS), 963 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); 964 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", 965 mtk_i2c_readw(i2c, OFFSET_DCM_EN), 966 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); 967 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", 968 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), 969 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); 970 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", 971 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), 972 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); 973 if (i2c->dev_comp->regs == mt_i2c_regs_v2) { 974 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", 975 mtk_i2c_readw(i2c, OFFSET_LTIMING), 976 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); 977 } 978 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", 979 readl(i2c->pdmabase + OFFSET_INT_FLAG), 980 readl(i2c->pdmabase + OFFSET_INT_EN)); 981 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", 982 readl(i2c->pdmabase + OFFSET_EN), 983 readl(i2c->pdmabase + OFFSET_CON)); 984 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", 985 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), 986 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); 987 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", 988 readl(i2c->pdmabase + OFFSET_TX_LEN), 989 readl(i2c->pdmabase + OFFSET_RX_LEN)); 990 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", 991 readl(i2c->pdmabase + OFFSET_TX_4G_MODE), 992 readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); 993 } 994 995 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 996 int num, int left_num) 997 { 998 u16 addr_reg; 999 u16 start_reg; 1000 u16 control_reg; 1001 u16 restart_flag = 0; 1002 u16 dma_sync = 0; 1003 u32 reg_4g_mode; 1004 u32 reg_dma_reset; 1005 u8 *dma_rd_buf = NULL; 1006 u8 *dma_wr_buf = NULL; 1007 dma_addr_t rpaddr = 0; 1008 dma_addr_t wpaddr = 0; 1009 int ret; 1010 1011 i2c->irq_stat = 0; 1012 1013 if (i2c->auto_restart) 1014 restart_flag = I2C_RS_TRANSFER; 1015 1016 reinit_completion(&i2c->msg_complete); 1017 1018 if (i2c->dev_comp->apdma_sync && 1019 i2c->op != I2C_MASTER_WRRD && num > 1) { 1020 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); 1021 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, 1022 i2c->pdmabase + OFFSET_RST); 1023 1024 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, 1025 reg_dma_reset, 1026 !(reg_dma_reset & I2C_DMA_WARM_RST), 1027 0, 100); 1028 if (ret) { 1029 dev_err(i2c->dev, "DMA warm reset timeout\n"); 1030 return -ETIMEDOUT; 1031 } 1032 1033 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 1034 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); 1035 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 1036 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, 1037 OFFSET_DEBUGCTRL); 1038 } 1039 1040 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 1041 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 1042 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) 1043 control_reg |= I2C_CONTROL_RS; 1044 1045 if (i2c->op == I2C_MASTER_WRRD) 1046 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 1047 1048 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 1049 1050 addr_reg = i2c_8bit_addr_from_msg(msgs); 1051 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 1052 1053 /* Clear interrupt status */ 1054 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1055 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 1056 1057 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 1058 1059 /* Enable interrupt */ 1060 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1061 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 1062 1063 /* Set transfer and transaction len */ 1064 if (i2c->op == I2C_MASTER_WRRD) { 1065 if (i2c->dev_comp->aux_len_reg) { 1066 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 1067 mtk_i2c_writew(i2c, (msgs + 1)->len, 1068 OFFSET_TRANSFER_LEN_AUX); 1069 } else { 1070 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 1071 OFFSET_TRANSFER_LEN); 1072 } 1073 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 1074 } else { 1075 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 1076 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 1077 } 1078 1079 if (i2c->dev_comp->apdma_sync) { 1080 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 1081 if (i2c->op == I2C_MASTER_WRRD) 1082 dma_sync |= I2C_DMA_DIR_CHANGE; 1083 } 1084 1085 /* Prepare buffer data to start transfer */ 1086 if (i2c->op == I2C_MASTER_RD) { 1087 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 1088 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 1089 1090 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1091 if (!dma_rd_buf) 1092 return -ENOMEM; 1093 1094 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1095 msgs->len, DMA_FROM_DEVICE); 1096 if (dma_mapping_error(i2c->dev, rpaddr)) { 1097 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 1098 1099 return -ENOMEM; 1100 } 1101 1102 if (i2c->dev_comp->max_dma_support > 32) { 1103 reg_4g_mode = upper_32_bits(rpaddr); 1104 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1105 } 1106 1107 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1108 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 1109 } else if (i2c->op == I2C_MASTER_WR) { 1110 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 1111 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 1112 1113 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1114 if (!dma_wr_buf) 1115 return -ENOMEM; 1116 1117 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1118 msgs->len, DMA_TO_DEVICE); 1119 if (dma_mapping_error(i2c->dev, wpaddr)) { 1120 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1121 1122 return -ENOMEM; 1123 } 1124 1125 if (i2c->dev_comp->max_dma_support > 32) { 1126 reg_4g_mode = upper_32_bits(wpaddr); 1127 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1128 } 1129 1130 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1131 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1132 } else { 1133 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 1134 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 1135 1136 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1137 if (!dma_wr_buf) 1138 return -ENOMEM; 1139 1140 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1141 msgs->len, DMA_TO_DEVICE); 1142 if (dma_mapping_error(i2c->dev, wpaddr)) { 1143 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1144 1145 return -ENOMEM; 1146 } 1147 1148 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 1149 if (!dma_rd_buf) { 1150 dma_unmap_single(i2c->dev, wpaddr, 1151 msgs->len, DMA_TO_DEVICE); 1152 1153 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1154 1155 return -ENOMEM; 1156 } 1157 1158 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1159 (msgs + 1)->len, 1160 DMA_FROM_DEVICE); 1161 if (dma_mapping_error(i2c->dev, rpaddr)) { 1162 dma_unmap_single(i2c->dev, wpaddr, 1163 msgs->len, DMA_TO_DEVICE); 1164 1165 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1166 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 1167 1168 return -ENOMEM; 1169 } 1170 1171 if (i2c->dev_comp->max_dma_support > 32) { 1172 reg_4g_mode = upper_32_bits(wpaddr); 1173 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1174 1175 reg_4g_mode = upper_32_bits(rpaddr); 1176 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1177 } 1178 1179 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1180 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1181 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1182 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 1183 } 1184 1185 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 1186 1187 if (!i2c->auto_restart) { 1188 start_reg = I2C_TRANSAC_START; 1189 } else { 1190 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 1191 if (left_num >= 1) 1192 start_reg |= I2C_RS_MUL_CNFG; 1193 } 1194 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 1195 1196 ret = wait_for_completion_timeout(&i2c->msg_complete, 1197 i2c->adap.timeout); 1198 1199 /* Clear interrupt mask */ 1200 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1201 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 1202 1203 if (i2c->op == I2C_MASTER_WR) { 1204 dma_unmap_single(i2c->dev, wpaddr, 1205 msgs->len, DMA_TO_DEVICE); 1206 1207 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1208 } else if (i2c->op == I2C_MASTER_RD) { 1209 dma_unmap_single(i2c->dev, rpaddr, 1210 msgs->len, DMA_FROM_DEVICE); 1211 1212 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 1213 } else { 1214 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1215 DMA_TO_DEVICE); 1216 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1217 DMA_FROM_DEVICE); 1218 1219 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1220 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1221 } 1222 1223 if (ret == 0) { 1224 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1225 i2c_dump_register(i2c); 1226 mtk_i2c_init_hw(i2c); 1227 return -ETIMEDOUT; 1228 } 1229 1230 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1231 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1232 mtk_i2c_init_hw(i2c); 1233 return -ENXIO; 1234 } 1235 1236 return 0; 1237 } 1238 1239 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1240 struct i2c_msg msgs[], int num) 1241 { 1242 int ret; 1243 int left_num = num; 1244 bool write_then_read_en = false; 1245 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1246 1247 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1248 if (ret) 1249 return ret; 1250 1251 i2c->auto_restart = i2c->dev_comp->auto_restart; 1252 1253 /* checking if we can skip restart and optimize using WRRD mode */ 1254 if (i2c->auto_restart && num == 2) { 1255 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1256 msgs[0].addr == msgs[1].addr) { 1257 i2c->auto_restart = 0; 1258 write_then_read_en = true; 1259 } 1260 } 1261 1262 if (i2c->auto_restart && num >= 2 && 1263 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 1264 /* ignore the first restart irq after the master code, 1265 * otherwise the first transfer will be discarded. 1266 */ 1267 i2c->ignore_restart_irq = true; 1268 else 1269 i2c->ignore_restart_irq = false; 1270 1271 while (left_num--) { 1272 if (!msgs->buf) { 1273 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1274 ret = -EINVAL; 1275 goto err_exit; 1276 } 1277 1278 if (msgs->flags & I2C_M_RD) 1279 i2c->op = I2C_MASTER_RD; 1280 else 1281 i2c->op = I2C_MASTER_WR; 1282 1283 if (write_then_read_en) { 1284 /* combined two messages into one transaction */ 1285 i2c->op = I2C_MASTER_WRRD; 1286 left_num--; 1287 } 1288 1289 /* always use DMA mode. */ 1290 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1291 if (ret < 0) 1292 goto err_exit; 1293 1294 if (i2c->op == I2C_MASTER_WRRD) 1295 msgs += 2; 1296 else 1297 msgs++; 1298 } 1299 /* the return value is number of executed messages */ 1300 ret = num; 1301 1302 err_exit: 1303 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1304 return ret; 1305 } 1306 1307 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1308 { 1309 struct mtk_i2c *i2c = dev_id; 1310 u16 restart_flag = i2c->auto_restart ? I2C_RS_TRANSFER : 0; 1311 u16 intr_stat; 1312 1313 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1314 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1315 1316 /* 1317 * when occurs ack error, i2c controller generate two interrupts 1318 * first is the ack error interrupt, then the complete interrupt 1319 * i2c->irq_stat need keep the two interrupt value. 1320 */ 1321 i2c->irq_stat |= intr_stat; 1322 1323 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1324 i2c->ignore_restart_irq = false; 1325 i2c->irq_stat = 0; 1326 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1327 I2C_TRANSAC_START, OFFSET_START); 1328 } else { 1329 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1330 complete(&i2c->msg_complete); 1331 } 1332 1333 return IRQ_HANDLED; 1334 } 1335 1336 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1337 { 1338 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1339 return I2C_FUNC_I2C | 1340 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1341 else 1342 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1343 } 1344 1345 static const struct i2c_algorithm mtk_i2c_algorithm = { 1346 .xfer = mtk_i2c_transfer, 1347 .functionality = mtk_i2c_functionality, 1348 }; 1349 1350 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1351 { 1352 int ret; 1353 1354 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1355 if (ret < 0) 1356 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1357 1358 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1359 if (ret < 0) 1360 return ret; 1361 1362 if (i2c->clk_src_div == 0) 1363 return -EINVAL; 1364 1365 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1366 i2c->use_push_pull = 1367 of_property_read_bool(np, "mediatek,use-push-pull"); 1368 1369 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); 1370 1371 return 0; 1372 } 1373 1374 static int mtk_i2c_probe(struct platform_device *pdev) 1375 { 1376 int ret = 0; 1377 struct mtk_i2c *i2c; 1378 int i, irq, speed_clk; 1379 1380 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1381 if (!i2c) 1382 return -ENOMEM; 1383 1384 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1385 if (IS_ERR(i2c->base)) 1386 return PTR_ERR(i2c->base); 1387 1388 i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 1389 if (IS_ERR(i2c->pdmabase)) 1390 return PTR_ERR(i2c->pdmabase); 1391 1392 irq = platform_get_irq(pdev, 0); 1393 if (irq < 0) 1394 return irq; 1395 1396 init_completion(&i2c->msg_complete); 1397 1398 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1399 i2c->adap.dev.of_node = pdev->dev.of_node; 1400 i2c->dev = &pdev->dev; 1401 i2c->adap.dev.parent = &pdev->dev; 1402 i2c->adap.owner = THIS_MODULE; 1403 i2c->adap.algo = &mtk_i2c_algorithm; 1404 i2c->adap.quirks = i2c->dev_comp->quirks; 1405 i2c->adap.timeout = 2 * HZ; 1406 i2c->adap.retries = 1; 1407 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); 1408 if (IS_ERR(i2c->adap.bus_regulator)) { 1409 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) 1410 i2c->adap.bus_regulator = NULL; 1411 else 1412 return PTR_ERR(i2c->adap.bus_regulator); 1413 } 1414 1415 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1416 if (ret) 1417 return -EINVAL; 1418 1419 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1420 return -EINVAL; 1421 1422 /* Fill in clk-bulk IDs */ 1423 for (i = 0; i < I2C_MT65XX_CLK_MAX; i++) 1424 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; 1425 1426 /* Get clocks one by one, some may be optional */ 1427 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); 1428 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { 1429 dev_err(&pdev->dev, "cannot get main clock\n"); 1430 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); 1431 } 1432 1433 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); 1434 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { 1435 dev_err(&pdev->dev, "cannot get dma clock\n"); 1436 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); 1437 } 1438 1439 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); 1440 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) 1441 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); 1442 1443 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic"); 1444 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { 1445 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1446 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); 1447 } 1448 1449 if (i2c->have_pmic) { 1450 if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { 1451 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1452 return -ENODEV; 1453 } 1454 speed_clk = I2C_MT65XX_CLK_PMIC; 1455 } else { 1456 speed_clk = I2C_MT65XX_CLK_MAIN; 1457 } 1458 1459 strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1460 1461 mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); 1462 1463 if (i2c->dev_comp->max_dma_support > 32) { 1464 ret = dma_set_mask(&pdev->dev, 1465 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); 1466 if (ret) { 1467 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1468 return ret; 1469 } 1470 } 1471 1472 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1473 if (ret) { 1474 dev_err(&pdev->dev, "clock enable failed!\n"); 1475 return ret; 1476 } 1477 mtk_i2c_init_hw(i2c); 1478 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1479 1480 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1481 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, 1482 dev_name(&pdev->dev), i2c); 1483 if (ret < 0) { 1484 dev_err(&pdev->dev, 1485 "Request I2C IRQ %d fail\n", irq); 1486 goto err_bulk_unprepare; 1487 } 1488 1489 i2c_set_adapdata(&i2c->adap, i2c); 1490 ret = i2c_add_adapter(&i2c->adap); 1491 if (ret) 1492 goto err_bulk_unprepare; 1493 1494 platform_set_drvdata(pdev, i2c); 1495 1496 return 0; 1497 1498 err_bulk_unprepare: 1499 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1500 1501 return ret; 1502 } 1503 1504 static void mtk_i2c_remove(struct platform_device *pdev) 1505 { 1506 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1507 1508 i2c_del_adapter(&i2c->adap); 1509 1510 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1511 } 1512 1513 static int mtk_i2c_suspend_noirq(struct device *dev) 1514 { 1515 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1516 1517 i2c_mark_adapter_suspended(&i2c->adap); 1518 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1519 1520 return 0; 1521 } 1522 1523 static int mtk_i2c_resume_noirq(struct device *dev) 1524 { 1525 int ret; 1526 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1527 1528 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1529 if (ret) { 1530 dev_err(dev, "clock enable failed!\n"); 1531 return ret; 1532 } 1533 1534 mtk_i2c_init_hw(i2c); 1535 1536 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1537 1538 i2c_mark_adapter_resumed(&i2c->adap); 1539 1540 return 0; 1541 } 1542 1543 static const struct dev_pm_ops mtk_i2c_pm = { 1544 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq, 1545 mtk_i2c_resume_noirq) 1546 }; 1547 1548 static struct platform_driver mtk_i2c_driver = { 1549 .probe = mtk_i2c_probe, 1550 .remove = mtk_i2c_remove, 1551 .driver = { 1552 .name = I2C_DRV_NAME, 1553 .pm = pm_sleep_ptr(&mtk_i2c_pm), 1554 .of_match_table = mtk_i2c_of_match, 1555 }, 1556 }; 1557 1558 module_platform_driver(mtk_i2c_driver); 1559 1560 MODULE_LICENSE("GPL v2"); 1561 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1562 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1563