1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef _DML2_WRAPPER_H_ 28 #define _DML2_WRAPPER_H_ 29 30 #include "os_types.h" 31 32 #define DML2_MAX_NUM_DPM_LVL 30 33 34 struct dml2_context; 35 struct display_mode_lib_st; 36 struct dc; 37 struct pipe_ctx; 38 struct dc_plane_state; 39 struct dc_sink; 40 struct dc_stream_state; 41 struct resource_context; 42 struct display_stream_compressor; 43 struct dc_mcache_params; 44 45 // Configuration of the MALL on the SoC 46 struct dml2_soc_mall_info { 47 // Cache line size of 0 means MALL is not enabled/present 48 unsigned int cache_line_size_bytes; 49 unsigned int cache_num_ways; 50 unsigned int max_cab_allocation_bytes; 51 52 unsigned int mblk_width_pixels; 53 unsigned int mblk_size_bytes; 54 unsigned int mblk_height_4bpe_pixels; 55 unsigned int mblk_height_8bpe_pixels; 56 }; 57 58 // Output of DML2 for clock requirements 59 struct dml2_dcn_clocks { 60 unsigned int dispclk_khz; 61 unsigned int dcfclk_khz; 62 unsigned int fclk_khz; 63 unsigned int uclk_mts; 64 unsigned int phyclk_khz; 65 unsigned int socclk_khz; 66 unsigned int ref_dtbclk_khz; 67 bool p_state_supported; 68 unsigned int cab_num_ways_required; 69 unsigned int dcfclk_khz_ds; 70 }; 71 72 struct dml2_dc_callbacks { 73 struct dc *dc; 74 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx); 75 void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master); 76 bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context); 77 bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm); 78 bool (*update_pipes_for_stream_with_slice_count)( 79 struct dc_state *new_ctx, 80 const struct dc_state *cur_ctx, 81 const struct resource_pool *pool, 82 const struct dc_stream_state *stream, 83 int new_slice_count); 84 bool (*update_pipes_for_plane_with_slice_count)( 85 struct dc_state *new_ctx, 86 const struct dc_state *cur_ctx, 87 const struct resource_pool *pool, 88 const struct dc_plane_state *plane, 89 int slice_count); 90 int (*get_odm_slice_index)(const struct pipe_ctx *opp_head); 91 int (*get_odm_slice_count)(const struct pipe_ctx *opp_head); 92 int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe); 93 int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe); 94 struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx); 95 struct pipe_ctx *(*get_otg_master_for_stream)( 96 struct resource_context *res_ctx, 97 const struct dc_stream_state *stream); 98 int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master, 99 struct resource_context *res_ctx, 100 struct pipe_ctx *opp_heads[MAX_PIPES]); 101 int (*get_dpp_pipes_for_plane)(const struct dc_plane_state *plane, 102 struct resource_context *res_ctx, 103 struct pipe_ctx *dpp_pipes[MAX_PIPES]); 104 struct dc_stream_status *(*get_stream_status)( 105 struct dc_state *state, 106 const struct dc_stream_state *stream); 107 struct dc_stream_state *(*get_stream_from_id)(const struct dc_state *state, unsigned int id); 108 unsigned int (*get_max_flickerless_instant_vtotal_increase)( 109 struct dc_stream_state *stream, 110 bool is_gaming); 111 bool (*allocate_mcache)(struct dc_state *context, const struct dc_mcache_params *mcache_params); 112 }; 113 114 struct dml2_dc_svp_callbacks { 115 struct dc *dc; 116 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx); 117 struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc, 118 struct dc_state *state, 119 struct dc_stream_state *main_stream); 120 struct dc_plane_state* (*create_phantom_plane)(const struct dc *dc, 121 struct dc_state *state, 122 struct dc_plane_state *main_plane); 123 enum dc_status (*add_phantom_stream)(const struct dc *dc, 124 struct dc_state *state, 125 struct dc_stream_state *phantom_stream, 126 struct dc_stream_state *main_stream); 127 bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context); 128 bool (*remove_phantom_plane)(const struct dc *dc, 129 struct dc_stream_state *stream, 130 struct dc_plane_state *plane_state, 131 struct dc_state *context); 132 enum dc_status (*remove_phantom_stream)(const struct dc *dc, 133 struct dc_state *state, 134 struct dc_stream_state *stream); 135 void (*release_phantom_plane)(const struct dc *dc, 136 struct dc_state *state, 137 struct dc_plane_state *plane); 138 void (*release_phantom_stream)(const struct dc *dc, 139 struct dc_state *state, 140 struct dc_stream_state *stream); 141 void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); 142 enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx); 143 enum mall_stream_type (*get_stream_subvp_type)(const struct dc_state *state, const struct dc_stream_state *stream); 144 struct dc_stream_state *(*get_paired_subvp_stream)(const struct dc_state *state, const struct dc_stream_state *stream); 145 bool (*remove_phantom_streams_and_planes)( 146 const struct dc *dc, 147 struct dc_state *state); 148 void (*release_phantom_streams_and_planes)( 149 const struct dc *dc, 150 struct dc_state *state); 151 unsigned int (*calculate_mall_ways_from_bytes)( 152 const struct dc *dc, 153 unsigned int total_size_in_mall_bytes); 154 }; 155 156 struct dml2_clks_table_entry { 157 unsigned int dcfclk_mhz; 158 unsigned int fclk_mhz; 159 unsigned int memclk_mhz; 160 unsigned int socclk_mhz; 161 unsigned int dtbclk_mhz; 162 unsigned int dispclk_mhz; 163 unsigned int dppclk_mhz; 164 unsigned int dram_speed_mts; /*which is based on wck_ratio*/ 165 }; 166 167 struct dml2_clks_num_entries { 168 unsigned int num_dcfclk_levels; 169 unsigned int num_fclk_levels; 170 unsigned int num_memclk_levels; 171 unsigned int num_socclk_levels; 172 unsigned int num_dtbclk_levels; 173 unsigned int num_dispclk_levels; 174 unsigned int num_dppclk_levels; 175 }; 176 177 struct dml2_clks_limit_table { 178 struct dml2_clks_table_entry clk_entries[DML2_MAX_NUM_DPM_LVL]; 179 struct dml2_clks_num_entries num_entries_per_clk; 180 unsigned int num_states; 181 }; 182 183 // Various overrides, per ASIC or per SKU specific, or for debugging purpose when/if available 184 struct dml2_soc_bbox_overrides { 185 double xtalclk_mhz; 186 double dchub_refclk_mhz; 187 double dprefclk_mhz; 188 double disp_pll_vco_speed_mhz; 189 double urgent_latency_us; 190 double sr_exit_latency_us; 191 double sr_enter_plus_exit_latency_us; 192 double sr_exit_z8_time_us; 193 double sr_enter_plus_exit_z8_time_us; 194 double dram_clock_change_latency_us; 195 double fclk_change_latency_us; 196 unsigned int dram_num_chan; 197 unsigned int dram_chanel_width_bytes; 198 struct dml2_clks_limit_table clks_table; 199 }; 200 201 enum dml2_force_pstate_methods { 202 dml2_force_pstate_method_auto = 0, 203 dml2_force_pstate_method_vactive, 204 dml2_force_pstate_method_vblank, 205 dml2_force_pstate_method_drr, 206 dml2_force_pstate_method_subvp, 207 }; 208 209 struct dml2_configuration_options { 210 int dcn_pipe_count; 211 bool use_native_pstate_optimization; 212 bool enable_windowed_mpo_odm; 213 bool use_native_soc_bb_construction; 214 bool skip_hw_state_mapping; 215 bool optimize_odm_4to1; 216 bool minimize_dispclk_using_odm; 217 bool override_det_buffer_size_kbytes; 218 struct dml2_dc_callbacks callbacks; 219 struct { 220 bool force_disable_subvp; 221 bool force_enable_subvp; 222 unsigned int subvp_fw_processing_delay_us; 223 unsigned int subvp_pstate_allow_width_us; 224 unsigned int subvp_prefetch_end_to_mall_start_us; 225 unsigned int subvp_swath_height_margin_lines; 226 struct dml2_dc_svp_callbacks callbacks; 227 } svp_pstate; 228 struct dml2_soc_mall_info mall_cfg; 229 struct dml2_soc_bbox_overrides bbox_overrides; 230 unsigned int max_segments_per_hubp; 231 unsigned int det_segment_size; 232 /* Only for debugging purposes when initializing SOCBB params via tool for DML21. */ 233 struct socbb_ip_params_external *external_socbb_ip_params; 234 struct { 235 bool force_pstate_method_enable; 236 enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES]; 237 } pmo; 238 bool map_dc_pipes_with_callbacks; 239 240 bool use_clock_dc_limits; 241 bool gpuvm_enable; 242 bool force_tdlut_enable; 243 void *bb_from_dmub; 244 }; 245 246 /* 247 * dml2_create - Creates dml2_context. 248 * @in_dc: dc. 249 * @config: dml2 configuration options. 250 * @dml2: Created dml2 context. 251 * 252 * Create and destroy of DML2 is done as part of dc_state creation 253 * and dc_state_free. DML2 IP, SOC and STATES are initialized at 254 * creation time. 255 * 256 * Return: True if dml2 is successfully created, false otherwise. 257 */ 258 bool dml2_create(const struct dc *in_dc, 259 const struct dml2_configuration_options *config, 260 struct dml2_context **dml2); 261 262 void dml2_destroy(struct dml2_context *dml2); 263 void dml2_copy(struct dml2_context *dst_dml2, 264 struct dml2_context *src_dml2); 265 bool dml2_create_copy(struct dml2_context **dst_dml2, 266 struct dml2_context *src_dml2); 267 void dml2_reinit(const struct dc *in_dc, 268 const struct dml2_configuration_options *config, 269 struct dml2_context **dml2); 270 271 /* 272 * dml2_validate - Determines if a display configuration is supported or not. 273 * @in_dc: dc. 274 * @context: dc_state to be validated. 275 * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX will not populate context.res_ctx. 276 * 277 * DML1.0 compatible interface for validation. 278 * 279 * Based on fast_validate option internally would call: 280 * 281 * -dml2_validate_and_build_resource - for non fast_validate option 282 * Calculates if dc_state can be supported on the SOC, and attempts to 283 * optimize the power management feature supports versus minimum clocks. 284 * If supported, also builds out_new_hw_state to represent the hw programming 285 * for the new dc state. 286 * 287 * -dml2_validate_only - for fast_validate option 288 * Calculates if dc_state can be supported on the SOC (i.e. at maximum 289 * clocks) with all mandatory power features enabled. 290 291 * Context: Two threads may not invoke this function concurrently unless they reference 292 * separate dc_states for validation. 293 * Return: True if mode is supported, false otherwise. 294 */ 295 bool dml2_validate(const struct dc *in_dc, 296 struct dc_state *context, 297 struct dml2_context *dml2, 298 enum dc_validate_mode validate_mode); 299 300 /* 301 * dml2_extract_dram_and_fclk_change_support - Extracts the FCLK and UCLK change support info. 302 * @dml2: input dml2 context pointer. 303 * @fclk_change_support: output pointer holding the fclk change support info (vactive, vblank, unsupported). 304 * @dram_clk_change_support: output pointer holding the uclk change support info (vactive, vblank, unsupported). 305 */ 306 void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, 307 unsigned int *fclk_change_support, unsigned int *dram_clk_change_support); 308 void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2); 309 #endif //_DML2_WRAPPER_H_ 310