1 /*
2 * QEMU model of the Xilinx Versal CANFD device.
3 *
4 * This implementation is based on the following datasheet:
5 * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd
6 *
7 * Copyright (c) 2023 Advanced Micro Devices, Inc.
8 *
9 * Written-by: Vikram Garhwal <vikram.garhwal@amd.com>
10 *
11 * Based on QEMU CANFD Device emulation implemented by Jin Yang, Deniz Eren and
12 * Pavel Pisa
13 *
14 * Permission is hereby granted, free of charge, to any person obtaining a copy
15 * of this software and associated documentation files (the "Software"), to deal
16 * in the Software without restriction, including without limitation the rights
17 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
18 * copies of the Software, and to permit persons to whom the Software is
19 * furnished to do so, subject to the following conditions:
20 *
21 * The above copyright notice and this permission notice shall be included in
22 * all copies or substantial portions of the Software.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
28 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
29 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * THE SOFTWARE.
31 */
32
33 #include "qemu/osdep.h"
34 #include "hw/sysbus.h"
35 #include "hw/irq.h"
36 #include "hw/register.h"
37 #include "qapi/error.h"
38 #include "qemu/bitops.h"
39 #include "qemu/log.h"
40 #include "qemu/cutils.h"
41 #include "qemu/event_notifier.h"
42 #include "hw/qdev-properties.h"
43 #include "qom/object_interfaces.h"
44 #include "migration/vmstate.h"
45 #include "hw/net/xlnx-versal-canfd.h"
46 #include "trace.h"
47
48 REG32(SOFTWARE_RESET_REGISTER, 0x0)
49 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
51 REG32(MODE_SELECT_REGISTER, 0x4)
52 FIELD(MODE_SELECT_REGISTER, ITO, 8, 8)
53 FIELD(MODE_SELECT_REGISTER, ABR, 7, 1)
54 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
55 FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1)
56 FIELD(MODE_SELECT_REGISTER, DAR, 4, 1)
57 FIELD(MODE_SELECT_REGISTER, BRSD, 3, 1)
58 FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
59 FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
60 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
61 REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
62 FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
63 REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
64 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 16, 7)
65 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 8, 7)
66 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 8)
67 REG32(ERROR_COUNTER_REGISTER, 0x10)
68 FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8)
69 FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
70 REG32(ERROR_STATUS_REGISTER, 0x14)
71 FIELD(ERROR_STATUS_REGISTER, F_BERR, 11, 1)
72 FIELD(ERROR_STATUS_REGISTER, F_STER, 10, 1)
73 FIELD(ERROR_STATUS_REGISTER, F_FMER, 9, 1)
74 FIELD(ERROR_STATUS_REGISTER, F_CRCER, 8, 1)
75 FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
76 FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
77 FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
78 FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
79 FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
80 REG32(STATUS_REGISTER, 0x18)
81 FIELD(STATUS_REGISTER, TDCV, 16, 7)
82 FIELD(STATUS_REGISTER, SNOOP, 12, 1)
83 FIELD(STATUS_REGISTER, BSFR_CONFIG, 10, 1)
84 FIELD(STATUS_REGISTER, PEE_CONFIG, 9, 1)
85 FIELD(STATUS_REGISTER, ESTAT, 7, 2)
86 FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
87 FIELD(STATUS_REGISTER, BBSY, 5, 1)
88 FIELD(STATUS_REGISTER, BIDLE, 4, 1)
89 FIELD(STATUS_REGISTER, NORMAL, 3, 1)
90 FIELD(STATUS_REGISTER, SLEEP, 2, 1)
91 FIELD(STATUS_REGISTER, LBACK, 1, 1)
92 FIELD(STATUS_REGISTER, CONFIG, 0, 1)
93 REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
94 FIELD(INTERRUPT_STATUS_REGISTER, TXEWMFLL, 31, 1)
95 FIELD(INTERRUPT_STATUS_REGISTER, TXEOFLW, 30, 1)
96 FIELD(INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 24, 6)
97 FIELD(INTERRUPT_STATUS_REGISTER, RXLRM_BI, 18, 6)
98 FIELD(INTERRUPT_STATUS_REGISTER, RXMNF, 17, 1)
99 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 16, 1)
100 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 15, 1)
101 FIELD(INTERRUPT_STATUS_REGISTER, TXCRS, 14, 1)
102 FIELD(INTERRUPT_STATUS_REGISTER, TXRRS, 13, 1)
103 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
104 FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
105 FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
106 FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
107 /*
108 * In the original HW description below bit is named as ERROR but an ERROR
109 * field name collides with a macro in Windows build. To avoid Windows build
110 * failures, the bit is renamed to ERROR_BIT.
111 */
112 FIELD(INTERRUPT_STATUS_REGISTER, ERROR_BIT, 8, 1)
113 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW, 6, 1)
114 FIELD(INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 5, 1)
115 FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
116 FIELD(INTERRUPT_STATUS_REGISTER, BSFRD, 3, 1)
117 FIELD(INTERRUPT_STATUS_REGISTER, PEE, 2, 1)
118 FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
119 FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
120 REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
121 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEWMFLL, 31, 1)
122 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEOFLW, 30, 1)
123 FIELD(INTERRUPT_ENABLE_REGISTER, ERXMNF, 17, 1)
124 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL_1, 16, 1)
125 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFOFLW_1, 15, 1)
126 FIELD(INTERRUPT_ENABLE_REGISTER, ETXCRS, 14, 1)
127 FIELD(INTERRUPT_ENABLE_REGISTER, ETXRRS, 13, 1)
128 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
129 FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
130 FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
131 FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
132 FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
133 FIELD(INTERRUPT_ENABLE_REGISTER, ERFXOFLW, 6, 1)
134 FIELD(INTERRUPT_ENABLE_REGISTER, ETSCNT_OFLW, 5, 1)
135 FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
136 FIELD(INTERRUPT_ENABLE_REGISTER, EBSFRD, 3, 1)
137 FIELD(INTERRUPT_ENABLE_REGISTER, EPEE, 2, 1)
138 FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
139 FIELD(INTERRUPT_ENABLE_REGISTER, EARBLOST, 0, 1)
140 REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
141 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEWMFLL, 31, 1)
142 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEOFLW, 30, 1)
143 FIELD(INTERRUPT_CLEAR_REGISTER, CRXMNF, 17, 1)
144 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL_1, 16, 1)
145 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFOFLW_1, 15, 1)
146 FIELD(INTERRUPT_CLEAR_REGISTER, CTXCRS, 14, 1)
147 FIELD(INTERRUPT_CLEAR_REGISTER, CTXRRS, 13, 1)
148 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
149 FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
150 FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
151 FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
152 FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
153 FIELD(INTERRUPT_CLEAR_REGISTER, CRFXOFLW, 6, 1)
154 FIELD(INTERRUPT_CLEAR_REGISTER, CTSCNT_OFLW, 5, 1)
155 FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
156 FIELD(INTERRUPT_CLEAR_REGISTER, CBSFRD, 3, 1)
157 FIELD(INTERRUPT_CLEAR_REGISTER, CPEE, 2, 1)
158 FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
159 FIELD(INTERRUPT_CLEAR_REGISTER, CARBLOST, 0, 1)
160 REG32(TIMESTAMP_REGISTER, 0x28)
161 FIELD(TIMESTAMP_REGISTER, TIMESTAMP_CNT, 16, 16)
162 FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
163 REG32(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x88)
164 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDC, 16, 1)
165 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDCOFF, 8, 6)
166 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, DP_BRP, 0, 8)
167 REG32(DATA_PHASE_BIT_TIMING_REGISTER, 0x8c)
168 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_SJW, 16, 4)
169 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS2, 8, 4)
170 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS1, 0, 5)
171 REG32(TX_BUFFER_READY_REQUEST_REGISTER, 0x90)
172 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR31, 31, 1)
173 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR30, 30, 1)
174 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR29, 29, 1)
175 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR28, 28, 1)
176 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR27, 27, 1)
177 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR26, 26, 1)
178 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR25, 25, 1)
179 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR24, 24, 1)
180 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR23, 23, 1)
181 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR22, 22, 1)
182 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR21, 21, 1)
183 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR20, 20, 1)
184 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR19, 19, 1)
185 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR18, 18, 1)
186 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR17, 17, 1)
187 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR16, 16, 1)
188 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR15, 15, 1)
189 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR14, 14, 1)
190 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR13, 13, 1)
191 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR12, 12, 1)
192 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR11, 11, 1)
193 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR10, 10, 1)
194 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR9, 9, 1)
195 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR8, 8, 1)
196 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR7, 7, 1)
197 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR6, 6, 1)
198 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR5, 5, 1)
199 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR4, 4, 1)
200 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR3, 3, 1)
201 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR2, 2, 1)
202 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR1, 1, 1)
203 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR0, 0, 1)
204 REG32(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, 0x94)
205 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS31, 31, 1)
206 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS30, 30, 1)
207 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS29, 29, 1)
208 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS28, 28, 1)
209 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS27, 27, 1)
210 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS26, 26, 1)
211 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS25, 25, 1)
212 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS24, 24, 1)
213 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS23, 23, 1)
214 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS22, 22, 1)
215 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS21, 21, 1)
216 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS20, 20, 1)
217 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS19, 19, 1)
218 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS18, 18, 1)
219 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS17, 17, 1)
220 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS16, 16, 1)
221 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS15, 15, 1)
222 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS14, 14, 1)
223 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS13, 13, 1)
224 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS12, 12, 1)
225 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS11, 11, 1)
226 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS10, 10, 1)
227 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS9, 9, 1)
228 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS8, 8, 1)
229 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS7, 7, 1)
230 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS6, 6, 1)
231 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS5, 5, 1)
232 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS4, 4, 1)
233 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS3, 3, 1)
234 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS2, 2, 1)
235 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS1, 1, 1)
236 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS0, 0, 1)
237 REG32(TX_BUFFER_CANCEL_REQUEST_REGISTER, 0x98)
238 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR31, 31, 1)
239 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR30, 30, 1)
240 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR29, 29, 1)
241 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR28, 28, 1)
242 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR27, 27, 1)
243 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR26, 26, 1)
244 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR25, 25, 1)
245 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR24, 24, 1)
246 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR23, 23, 1)
247 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR22, 22, 1)
248 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR21, 21, 1)
249 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR20, 20, 1)
250 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR19, 19, 1)
251 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR18, 18, 1)
252 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR17, 17, 1)
253 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR16, 16, 1)
254 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR15, 15, 1)
255 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR14, 14, 1)
256 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR13, 13, 1)
257 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR12, 12, 1)
258 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR11, 11, 1)
259 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR10, 10, 1)
260 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR9, 9, 1)
261 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR8, 8, 1)
262 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR7, 7, 1)
263 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR6, 6, 1)
264 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR5, 5, 1)
265 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR4, 4, 1)
266 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR3, 3, 1)
267 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR2, 2, 1)
268 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR1, 1, 1)
269 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR0, 0, 1)
270 REG32(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, 0x9c)
271 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS31, 31,
272 1)
273 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS30, 30,
274 1)
275 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS29, 29,
276 1)
277 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS28, 28,
278 1)
279 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS27, 27,
280 1)
281 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS26, 26,
282 1)
283 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS25, 25,
284 1)
285 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS24, 24,
286 1)
287 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS23, 23,
288 1)
289 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS22, 22,
290 1)
291 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS21, 21,
292 1)
293 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS20, 20,
294 1)
295 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS19, 19,
296 1)
297 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS18, 18,
298 1)
299 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS17, 17,
300 1)
301 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS16, 16,
302 1)
303 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS15, 15,
304 1)
305 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS14, 14,
306 1)
307 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS13, 13,
308 1)
309 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS12, 12,
310 1)
311 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS11, 11,
312 1)
313 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS10, 10,
314 1)
315 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS9, 9, 1)
316 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS8, 8, 1)
317 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS7, 7, 1)
318 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS6, 6, 1)
319 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS5, 5, 1)
320 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS4, 4, 1)
321 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS3, 3, 1)
322 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS2, 2, 1)
323 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS1, 1, 1)
324 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS0, 0, 1)
325 REG32(TX_EVENT_FIFO_STATUS_REGISTER, 0xa0)
326 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, 8, 6)
327 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI, 7, 1)
328 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, 0, 5)
329 REG32(TX_EVENT_FIFO_WATERMARK_REGISTER, 0xa4)
330 FIELD(TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM, 0, 5)
331 REG32(ACCEPTANCE_FILTER_CONTROL_REGISTER, 0xe0)
332 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF31, 31, 1)
333 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF30, 30, 1)
334 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF29, 29, 1)
335 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF28, 28, 1)
336 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF27, 27, 1)
337 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF26, 26, 1)
338 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF25, 25, 1)
339 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF24, 24, 1)
340 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF23, 23, 1)
341 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF22, 22, 1)
342 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF21, 21, 1)
343 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF20, 20, 1)
344 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF19, 19, 1)
345 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF18, 18, 1)
346 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF17, 17, 1)
347 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF16, 16, 1)
348 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF15, 15, 1)
349 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF14, 14, 1)
350 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF13, 13, 1)
351 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF12, 12, 1)
352 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF11, 11, 1)
353 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF10, 10, 1)
354 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF9, 9, 1)
355 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF8, 8, 1)
356 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF7, 7, 1)
357 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF6, 6, 1)
358 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF5, 5, 1)
359 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF4, 4, 1)
360 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF3, 3, 1)
361 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF2, 2, 1)
362 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF1, 1, 1)
363 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF0, 0, 1)
364 REG32(RX_FIFO_STATUS_REGISTER, 0xe8)
365 FIELD(RX_FIFO_STATUS_REGISTER, FL_1, 24, 7)
366 FIELD(RX_FIFO_STATUS_REGISTER, IRI_1, 23, 1)
367 FIELD(RX_FIFO_STATUS_REGISTER, RI_1, 16, 6)
368 FIELD(RX_FIFO_STATUS_REGISTER, FL, 8, 7)
369 FIELD(RX_FIFO_STATUS_REGISTER, IRI, 7, 1)
370 FIELD(RX_FIFO_STATUS_REGISTER, RI, 0, 6)
371 REG32(RX_FIFO_WATERMARK_REGISTER, 0xec)
372 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFP, 16, 5)
373 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM_1, 8, 6)
374 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM, 0, 6)
375 REG32(TB_ID_REGISTER, 0x100)
376 FIELD(TB_ID_REGISTER, ID, 21, 11)
377 FIELD(TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
378 FIELD(TB_ID_REGISTER, IDE, 19, 1)
379 FIELD(TB_ID_REGISTER, ID_EXT, 1, 18)
380 FIELD(TB_ID_REGISTER, RTR_RRS, 0, 1)
381 REG32(TB0_DLC_REGISTER, 0x104)
382 FIELD(TB0_DLC_REGISTER, DLC, 28, 4)
383 FIELD(TB0_DLC_REGISTER, FDF, 27, 1)
384 FIELD(TB0_DLC_REGISTER, BRS, 26, 1)
385 FIELD(TB0_DLC_REGISTER, RSVD2, 25, 1)
386 FIELD(TB0_DLC_REGISTER, EFC, 24, 1)
387 FIELD(TB0_DLC_REGISTER, MM, 16, 8)
388 FIELD(TB0_DLC_REGISTER, RSVD1, 0, 16)
389 REG32(TB_DW0_REGISTER, 0x108)
390 FIELD(TB_DW0_REGISTER, DATA_BYTES0, 24, 8)
391 FIELD(TB_DW0_REGISTER, DATA_BYTES1, 16, 8)
392 FIELD(TB_DW0_REGISTER, DATA_BYTES2, 8, 8)
393 FIELD(TB_DW0_REGISTER, DATA_BYTES3, 0, 8)
394 REG32(TB_DW1_REGISTER, 0x10c)
395 FIELD(TB_DW1_REGISTER, DATA_BYTES4, 24, 8)
396 FIELD(TB_DW1_REGISTER, DATA_BYTES5, 16, 8)
397 FIELD(TB_DW1_REGISTER, DATA_BYTES6, 8, 8)
398 FIELD(TB_DW1_REGISTER, DATA_BYTES7, 0, 8)
399 REG32(TB_DW2_REGISTER, 0x110)
400 FIELD(TB_DW2_REGISTER, DATA_BYTES8, 24, 8)
401 FIELD(TB_DW2_REGISTER, DATA_BYTES9, 16, 8)
402 FIELD(TB_DW2_REGISTER, DATA_BYTES10, 8, 8)
403 FIELD(TB_DW2_REGISTER, DATA_BYTES11, 0, 8)
404 REG32(TB_DW3_REGISTER, 0x114)
405 FIELD(TB_DW3_REGISTER, DATA_BYTES12, 24, 8)
406 FIELD(TB_DW3_REGISTER, DATA_BYTES13, 16, 8)
407 FIELD(TB_DW3_REGISTER, DATA_BYTES14, 8, 8)
408 FIELD(TB_DW3_REGISTER, DATA_BYTES15, 0, 8)
409 REG32(TB_DW4_REGISTER, 0x118)
410 FIELD(TB_DW4_REGISTER, DATA_BYTES16, 24, 8)
411 FIELD(TB_DW4_REGISTER, DATA_BYTES17, 16, 8)
412 FIELD(TB_DW4_REGISTER, DATA_BYTES18, 8, 8)
413 FIELD(TB_DW4_REGISTER, DATA_BYTES19, 0, 8)
414 REG32(TB_DW5_REGISTER, 0x11c)
415 FIELD(TB_DW5_REGISTER, DATA_BYTES20, 24, 8)
416 FIELD(TB_DW5_REGISTER, DATA_BYTES21, 16, 8)
417 FIELD(TB_DW5_REGISTER, DATA_BYTES22, 8, 8)
418 FIELD(TB_DW5_REGISTER, DATA_BYTES23, 0, 8)
419 REG32(TB_DW6_REGISTER, 0x120)
420 FIELD(TB_DW6_REGISTER, DATA_BYTES24, 24, 8)
421 FIELD(TB_DW6_REGISTER, DATA_BYTES25, 16, 8)
422 FIELD(TB_DW6_REGISTER, DATA_BYTES26, 8, 8)
423 FIELD(TB_DW6_REGISTER, DATA_BYTES27, 0, 8)
424 REG32(TB_DW7_REGISTER, 0x124)
425 FIELD(TB_DW7_REGISTER, DATA_BYTES28, 24, 8)
426 FIELD(TB_DW7_REGISTER, DATA_BYTES29, 16, 8)
427 FIELD(TB_DW7_REGISTER, DATA_BYTES30, 8, 8)
428 FIELD(TB_DW7_REGISTER, DATA_BYTES31, 0, 8)
429 REG32(TB_DW8_REGISTER, 0x128)
430 FIELD(TB_DW8_REGISTER, DATA_BYTES32, 24, 8)
431 FIELD(TB_DW8_REGISTER, DATA_BYTES33, 16, 8)
432 FIELD(TB_DW8_REGISTER, DATA_BYTES34, 8, 8)
433 FIELD(TB_DW8_REGISTER, DATA_BYTES35, 0, 8)
434 REG32(TB_DW9_REGISTER, 0x12c)
435 FIELD(TB_DW9_REGISTER, DATA_BYTES36, 24, 8)
436 FIELD(TB_DW9_REGISTER, DATA_BYTES37, 16, 8)
437 FIELD(TB_DW9_REGISTER, DATA_BYTES38, 8, 8)
438 FIELD(TB_DW9_REGISTER, DATA_BYTES39, 0, 8)
439 REG32(TB_DW10_REGISTER, 0x130)
440 FIELD(TB_DW10_REGISTER, DATA_BYTES40, 24, 8)
441 FIELD(TB_DW10_REGISTER, DATA_BYTES41, 16, 8)
442 FIELD(TB_DW10_REGISTER, DATA_BYTES42, 8, 8)
443 FIELD(TB_DW10_REGISTER, DATA_BYTES43, 0, 8)
444 REG32(TB_DW11_REGISTER, 0x134)
445 FIELD(TB_DW11_REGISTER, DATA_BYTES44, 24, 8)
446 FIELD(TB_DW11_REGISTER, DATA_BYTES45, 16, 8)
447 FIELD(TB_DW11_REGISTER, DATA_BYTES46, 8, 8)
448 FIELD(TB_DW11_REGISTER, DATA_BYTES47, 0, 8)
449 REG32(TB_DW12_REGISTER, 0x138)
450 FIELD(TB_DW12_REGISTER, DATA_BYTES48, 24, 8)
451 FIELD(TB_DW12_REGISTER, DATA_BYTES49, 16, 8)
452 FIELD(TB_DW12_REGISTER, DATA_BYTES50, 8, 8)
453 FIELD(TB_DW12_REGISTER, DATA_BYTES51, 0, 8)
454 REG32(TB_DW13_REGISTER, 0x13c)
455 FIELD(TB_DW13_REGISTER, DATA_BYTES52, 24, 8)
456 FIELD(TB_DW13_REGISTER, DATA_BYTES53, 16, 8)
457 FIELD(TB_DW13_REGISTER, DATA_BYTES54, 8, 8)
458 FIELD(TB_DW13_REGISTER, DATA_BYTES55, 0, 8)
459 REG32(TB_DW14_REGISTER, 0x140)
460 FIELD(TB_DW14_REGISTER, DATA_BYTES56, 24, 8)
461 FIELD(TB_DW14_REGISTER, DATA_BYTES57, 16, 8)
462 FIELD(TB_DW14_REGISTER, DATA_BYTES58, 8, 8)
463 FIELD(TB_DW14_REGISTER, DATA_BYTES59, 0, 8)
464 REG32(TB_DW15_REGISTER, 0x144)
465 FIELD(TB_DW15_REGISTER, DATA_BYTES60, 24, 8)
466 FIELD(TB_DW15_REGISTER, DATA_BYTES61, 16, 8)
467 FIELD(TB_DW15_REGISTER, DATA_BYTES62, 8, 8)
468 FIELD(TB_DW15_REGISTER, DATA_BYTES63, 0, 8)
469 REG32(AFMR_REGISTER, 0xa00)
470 FIELD(AFMR_REGISTER, AMID, 21, 11)
471 FIELD(AFMR_REGISTER, AMSRR, 20, 1)
472 FIELD(AFMR_REGISTER, AMIDE, 19, 1)
473 FIELD(AFMR_REGISTER, AMID_EXT, 1, 18)
474 FIELD(AFMR_REGISTER, AMRTR, 0, 1)
475 REG32(AFIR_REGISTER, 0xa04)
476 FIELD(AFIR_REGISTER, AIID, 21, 11)
477 FIELD(AFIR_REGISTER, AISRR, 20, 1)
478 FIELD(AFIR_REGISTER, AIIDE, 19, 1)
479 FIELD(AFIR_REGISTER, AIID_EXT, 1, 18)
480 FIELD(AFIR_REGISTER, AIRTR, 0, 1)
481 REG32(TXE_FIFO_TB_ID_REGISTER, 0x2000)
482 FIELD(TXE_FIFO_TB_ID_REGISTER, ID, 21, 11)
483 FIELD(TXE_FIFO_TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
484 FIELD(TXE_FIFO_TB_ID_REGISTER, IDE, 19, 1)
485 FIELD(TXE_FIFO_TB_ID_REGISTER, ID_EXT, 1, 18)
486 FIELD(TXE_FIFO_TB_ID_REGISTER, RTR_RRS, 0, 1)
487 REG32(TXE_FIFO_TB_DLC_REGISTER, 0x2004)
488 FIELD(TXE_FIFO_TB_DLC_REGISTER, DLC, 28, 4)
489 FIELD(TXE_FIFO_TB_DLC_REGISTER, FDF, 27, 1)
490 FIELD(TXE_FIFO_TB_DLC_REGISTER, BRS, 26, 1)
491 FIELD(TXE_FIFO_TB_DLC_REGISTER, ET, 24, 2)
492 FIELD(TXE_FIFO_TB_DLC_REGISTER, MM, 16, 8)
493 FIELD(TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP, 0, 16)
494 REG32(RB_ID_REGISTER, 0x2100)
495 FIELD(RB_ID_REGISTER, ID, 21, 11)
496 FIELD(RB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
497 FIELD(RB_ID_REGISTER, IDE, 19, 1)
498 FIELD(RB_ID_REGISTER, ID_EXT, 1, 18)
499 FIELD(RB_ID_REGISTER, RTR_RRS, 0, 1)
500 REG32(RB_DLC_REGISTER, 0x2104)
501 FIELD(RB_DLC_REGISTER, DLC, 28, 4)
502 FIELD(RB_DLC_REGISTER, FDF, 27, 1)
503 FIELD(RB_DLC_REGISTER, BRS, 26, 1)
504 FIELD(RB_DLC_REGISTER, ESI, 25, 1)
505 FIELD(RB_DLC_REGISTER, MATCHED_FILTER_INDEX, 16, 5)
506 FIELD(RB_DLC_REGISTER, TIMESTAMP, 0, 16)
507 REG32(RB_DW0_REGISTER, 0x2108)
508 FIELD(RB_DW0_REGISTER, DATA_BYTES0, 24, 8)
509 FIELD(RB_DW0_REGISTER, DATA_BYTES1, 16, 8)
510 FIELD(RB_DW0_REGISTER, DATA_BYTES2, 8, 8)
511 FIELD(RB_DW0_REGISTER, DATA_BYTES3, 0, 8)
512 REG32(RB_DW1_REGISTER, 0x210c)
513 FIELD(RB_DW1_REGISTER, DATA_BYTES4, 24, 8)
514 FIELD(RB_DW1_REGISTER, DATA_BYTES5, 16, 8)
515 FIELD(RB_DW1_REGISTER, DATA_BYTES6, 8, 8)
516 FIELD(RB_DW1_REGISTER, DATA_BYTES7, 0, 8)
517 REG32(RB_DW2_REGISTER, 0x2110)
518 FIELD(RB_DW2_REGISTER, DATA_BYTES8, 24, 8)
519 FIELD(RB_DW2_REGISTER, DATA_BYTES9, 16, 8)
520 FIELD(RB_DW2_REGISTER, DATA_BYTES10, 8, 8)
521 FIELD(RB_DW2_REGISTER, DATA_BYTES11, 0, 8)
522 REG32(RB_DW3_REGISTER, 0x2114)
523 FIELD(RB_DW3_REGISTER, DATA_BYTES12, 24, 8)
524 FIELD(RB_DW3_REGISTER, DATA_BYTES13, 16, 8)
525 FIELD(RB_DW3_REGISTER, DATA_BYTES14, 8, 8)
526 FIELD(RB_DW3_REGISTER, DATA_BYTES15, 0, 8)
527 REG32(RB_DW4_REGISTER, 0x2118)
528 FIELD(RB_DW4_REGISTER, DATA_BYTES16, 24, 8)
529 FIELD(RB_DW4_REGISTER, DATA_BYTES17, 16, 8)
530 FIELD(RB_DW4_REGISTER, DATA_BYTES18, 8, 8)
531 FIELD(RB_DW4_REGISTER, DATA_BYTES19, 0, 8)
532 REG32(RB_DW5_REGISTER, 0x211c)
533 FIELD(RB_DW5_REGISTER, DATA_BYTES20, 24, 8)
534 FIELD(RB_DW5_REGISTER, DATA_BYTES21, 16, 8)
535 FIELD(RB_DW5_REGISTER, DATA_BYTES22, 8, 8)
536 FIELD(RB_DW5_REGISTER, DATA_BYTES23, 0, 8)
537 REG32(RB_DW6_REGISTER, 0x2120)
538 FIELD(RB_DW6_REGISTER, DATA_BYTES24, 24, 8)
539 FIELD(RB_DW6_REGISTER, DATA_BYTES25, 16, 8)
540 FIELD(RB_DW6_REGISTER, DATA_BYTES26, 8, 8)
541 FIELD(RB_DW6_REGISTER, DATA_BYTES27, 0, 8)
542 REG32(RB_DW7_REGISTER, 0x2124)
543 FIELD(RB_DW7_REGISTER, DATA_BYTES28, 24, 8)
544 FIELD(RB_DW7_REGISTER, DATA_BYTES29, 16, 8)
545 FIELD(RB_DW7_REGISTER, DATA_BYTES30, 8, 8)
546 FIELD(RB_DW7_REGISTER, DATA_BYTES31, 0, 8)
547 REG32(RB_DW8_REGISTER, 0x2128)
548 FIELD(RB_DW8_REGISTER, DATA_BYTES32, 24, 8)
549 FIELD(RB_DW8_REGISTER, DATA_BYTES33, 16, 8)
550 FIELD(RB_DW8_REGISTER, DATA_BYTES34, 8, 8)
551 FIELD(RB_DW8_REGISTER, DATA_BYTES35, 0, 8)
552 REG32(RB_DW9_REGISTER, 0x212c)
553 FIELD(RB_DW9_REGISTER, DATA_BYTES36, 24, 8)
554 FIELD(RB_DW9_REGISTER, DATA_BYTES37, 16, 8)
555 FIELD(RB_DW9_REGISTER, DATA_BYTES38, 8, 8)
556 FIELD(RB_DW9_REGISTER, DATA_BYTES39, 0, 8)
557 REG32(RB_DW10_REGISTER, 0x2130)
558 FIELD(RB_DW10_REGISTER, DATA_BYTES40, 24, 8)
559 FIELD(RB_DW10_REGISTER, DATA_BYTES41, 16, 8)
560 FIELD(RB_DW10_REGISTER, DATA_BYTES42, 8, 8)
561 FIELD(RB_DW10_REGISTER, DATA_BYTES43, 0, 8)
562 REG32(RB_DW11_REGISTER, 0x2134)
563 FIELD(RB_DW11_REGISTER, DATA_BYTES44, 24, 8)
564 FIELD(RB_DW11_REGISTER, DATA_BYTES45, 16, 8)
565 FIELD(RB_DW11_REGISTER, DATA_BYTES46, 8, 8)
566 FIELD(RB_DW11_REGISTER, DATA_BYTES47, 0, 8)
567 REG32(RB_DW12_REGISTER, 0x2138)
568 FIELD(RB_DW12_REGISTER, DATA_BYTES48, 24, 8)
569 FIELD(RB_DW12_REGISTER, DATA_BYTES49, 16, 8)
570 FIELD(RB_DW12_REGISTER, DATA_BYTES50, 8, 8)
571 FIELD(RB_DW12_REGISTER, DATA_BYTES51, 0, 8)
572 REG32(RB_DW13_REGISTER, 0x213c)
573 FIELD(RB_DW13_REGISTER, DATA_BYTES52, 24, 8)
574 FIELD(RB_DW13_REGISTER, DATA_BYTES53, 16, 8)
575 FIELD(RB_DW13_REGISTER, DATA_BYTES54, 8, 8)
576 FIELD(RB_DW13_REGISTER, DATA_BYTES55, 0, 8)
577 REG32(RB_DW14_REGISTER, 0x2140)
578 FIELD(RB_DW14_REGISTER, DATA_BYTES56, 24, 8)
579 FIELD(RB_DW14_REGISTER, DATA_BYTES57, 16, 8)
580 FIELD(RB_DW14_REGISTER, DATA_BYTES58, 8, 8)
581 FIELD(RB_DW14_REGISTER, DATA_BYTES59, 0, 8)
582 REG32(RB_DW15_REGISTER, 0x2144)
583 FIELD(RB_DW15_REGISTER, DATA_BYTES60, 24, 8)
584 FIELD(RB_DW15_REGISTER, DATA_BYTES61, 16, 8)
585 FIELD(RB_DW15_REGISTER, DATA_BYTES62, 8, 8)
586 FIELD(RB_DW15_REGISTER, DATA_BYTES63, 0, 8)
587 REG32(RB_ID_REGISTER_1, 0x4100)
588 FIELD(RB_ID_REGISTER_1, ID, 21, 11)
589 FIELD(RB_ID_REGISTER_1, SRR_RTR_RRS, 20, 1)
590 FIELD(RB_ID_REGISTER_1, IDE, 19, 1)
591 FIELD(RB_ID_REGISTER_1, ID_EXT, 1, 18)
592 FIELD(RB_ID_REGISTER_1, RTR_RRS, 0, 1)
593 REG32(RB_DLC_REGISTER_1, 0x4104)
594 FIELD(RB_DLC_REGISTER_1, DLC, 28, 4)
595 FIELD(RB_DLC_REGISTER_1, FDF, 27, 1)
596 FIELD(RB_DLC_REGISTER_1, BRS, 26, 1)
597 FIELD(RB_DLC_REGISTER_1, ESI, 25, 1)
598 FIELD(RB_DLC_REGISTER_1, MATCHED_FILTER_INDEX, 16, 5)
599 FIELD(RB_DLC_REGISTER_1, TIMESTAMP, 0, 16)
600 REG32(RB0_DW0_REGISTER_1, 0x4108)
601 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES0, 24, 8)
602 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES1, 16, 8)
603 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES2, 8, 8)
604 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES3, 0, 8)
605 REG32(RB_DW1_REGISTER_1, 0x410c)
606 FIELD(RB_DW1_REGISTER_1, DATA_BYTES4, 24, 8)
607 FIELD(RB_DW1_REGISTER_1, DATA_BYTES5, 16, 8)
608 FIELD(RB_DW1_REGISTER_1, DATA_BYTES6, 8, 8)
609 FIELD(RB_DW1_REGISTER_1, DATA_BYTES7, 0, 8)
610 REG32(RB_DW2_REGISTER_1, 0x4110)
611 FIELD(RB_DW2_REGISTER_1, DATA_BYTES8, 24, 8)
612 FIELD(RB_DW2_REGISTER_1, DATA_BYTES9, 16, 8)
613 FIELD(RB_DW2_REGISTER_1, DATA_BYTES10, 8, 8)
614 FIELD(RB_DW2_REGISTER_1, DATA_BYTES11, 0, 8)
615 REG32(RB_DW3_REGISTER_1, 0x4114)
616 FIELD(RB_DW3_REGISTER_1, DATA_BYTES12, 24, 8)
617 FIELD(RB_DW3_REGISTER_1, DATA_BYTES13, 16, 8)
618 FIELD(RB_DW3_REGISTER_1, DATA_BYTES14, 8, 8)
619 FIELD(RB_DW3_REGISTER_1, DATA_BYTES15, 0, 8)
620 REG32(RB_DW4_REGISTER_1, 0x4118)
621 FIELD(RB_DW4_REGISTER_1, DATA_BYTES16, 24, 8)
622 FIELD(RB_DW4_REGISTER_1, DATA_BYTES17, 16, 8)
623 FIELD(RB_DW4_REGISTER_1, DATA_BYTES18, 8, 8)
624 FIELD(RB_DW4_REGISTER_1, DATA_BYTES19, 0, 8)
625 REG32(RB_DW5_REGISTER_1, 0x411c)
626 FIELD(RB_DW5_REGISTER_1, DATA_BYTES20, 24, 8)
627 FIELD(RB_DW5_REGISTER_1, DATA_BYTES21, 16, 8)
628 FIELD(RB_DW5_REGISTER_1, DATA_BYTES22, 8, 8)
629 FIELD(RB_DW5_REGISTER_1, DATA_BYTES23, 0, 8)
630 REG32(RB_DW6_REGISTER_1, 0x4120)
631 FIELD(RB_DW6_REGISTER_1, DATA_BYTES24, 24, 8)
632 FIELD(RB_DW6_REGISTER_1, DATA_BYTES25, 16, 8)
633 FIELD(RB_DW6_REGISTER_1, DATA_BYTES26, 8, 8)
634 FIELD(RB_DW6_REGISTER_1, DATA_BYTES27, 0, 8)
635 REG32(RB_DW7_REGISTER_1, 0x4124)
636 FIELD(RB_DW7_REGISTER_1, DATA_BYTES28, 24, 8)
637 FIELD(RB_DW7_REGISTER_1, DATA_BYTES29, 16, 8)
638 FIELD(RB_DW7_REGISTER_1, DATA_BYTES30, 8, 8)
639 FIELD(RB_DW7_REGISTER_1, DATA_BYTES31, 0, 8)
640 REG32(RB_DW8_REGISTER_1, 0x4128)
641 FIELD(RB_DW8_REGISTER_1, DATA_BYTES32, 24, 8)
642 FIELD(RB_DW8_REGISTER_1, DATA_BYTES33, 16, 8)
643 FIELD(RB_DW8_REGISTER_1, DATA_BYTES34, 8, 8)
644 FIELD(RB_DW8_REGISTER_1, DATA_BYTES35, 0, 8)
645 REG32(RB_DW9_REGISTER_1, 0x412c)
646 FIELD(RB_DW9_REGISTER_1, DATA_BYTES36, 24, 8)
647 FIELD(RB_DW9_REGISTER_1, DATA_BYTES37, 16, 8)
648 FIELD(RB_DW9_REGISTER_1, DATA_BYTES38, 8, 8)
649 FIELD(RB_DW9_REGISTER_1, DATA_BYTES39, 0, 8)
650 REG32(RB_DW10_REGISTER_1, 0x4130)
651 FIELD(RB_DW10_REGISTER_1, DATA_BYTES40, 24, 8)
652 FIELD(RB_DW10_REGISTER_1, DATA_BYTES41, 16, 8)
653 FIELD(RB_DW10_REGISTER_1, DATA_BYTES42, 8, 8)
654 FIELD(RB_DW10_REGISTER_1, DATA_BYTES43, 0, 8)
655 REG32(RB_DW11_REGISTER_1, 0x4134)
656 FIELD(RB_DW11_REGISTER_1, DATA_BYTES44, 24, 8)
657 FIELD(RB_DW11_REGISTER_1, DATA_BYTES45, 16, 8)
658 FIELD(RB_DW11_REGISTER_1, DATA_BYTES46, 8, 8)
659 FIELD(RB_DW11_REGISTER_1, DATA_BYTES47, 0, 8)
660 REG32(RB_DW12_REGISTER_1, 0x4138)
661 FIELD(RB_DW12_REGISTER_1, DATA_BYTES48, 24, 8)
662 FIELD(RB_DW12_REGISTER_1, DATA_BYTES49, 16, 8)
663 FIELD(RB_DW12_REGISTER_1, DATA_BYTES50, 8, 8)
664 FIELD(RB_DW12_REGISTER_1, DATA_BYTES51, 0, 8)
665 REG32(RB_DW13_REGISTER_1, 0x413c)
666 FIELD(RB_DW13_REGISTER_1, DATA_BYTES52, 24, 8)
667 FIELD(RB_DW13_REGISTER_1, DATA_BYTES53, 16, 8)
668 FIELD(RB_DW13_REGISTER_1, DATA_BYTES54, 8, 8)
669 FIELD(RB_DW13_REGISTER_1, DATA_BYTES55, 0, 8)
670 REG32(RB_DW14_REGISTER_1, 0x4140)
671 FIELD(RB_DW14_REGISTER_1, DATA_BYTES56, 24, 8)
672 FIELD(RB_DW14_REGISTER_1, DATA_BYTES57, 16, 8)
673 FIELD(RB_DW14_REGISTER_1, DATA_BYTES58, 8, 8)
674 FIELD(RB_DW14_REGISTER_1, DATA_BYTES59, 0, 8)
675 REG32(RB_DW15_REGISTER_1, 0x4144)
676 FIELD(RB_DW15_REGISTER_1, DATA_BYTES60, 24, 8)
677 FIELD(RB_DW15_REGISTER_1, DATA_BYTES61, 16, 8)
678 FIELD(RB_DW15_REGISTER_1, DATA_BYTES62, 8, 8)
679 FIELD(RB_DW15_REGISTER_1, DATA_BYTES63, 0, 8)
680
canfd_update_irq(XlnxVersalCANFDState * s)681 static void canfd_update_irq(XlnxVersalCANFDState *s)
682 {
683 const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] &
684 s->regs[R_INTERRUPT_ENABLE_REGISTER]) != 0;
685 g_autofree char *path = object_get_canonical_path(OBJECT(s));
686
687 /* RX watermark interrupts. */
688 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL) >
689 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM)) {
690 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1);
691 }
692
693 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1) >
694 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM_1)) {
695 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 1);
696 }
697
698 /* TX watermark interrupt. */
699 if (ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL) >
700 ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM)) {
701 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEWMFLL, 1);
702 }
703
704 trace_xlnx_canfd_update_irq(path, s->regs[R_INTERRUPT_STATUS_REGISTER],
705 s->regs[R_INTERRUPT_ENABLE_REGISTER], irq);
706
707 qemu_set_irq(s->irq_canfd_int, irq);
708 }
709
canfd_ier_post_write(RegisterInfo * reg,uint64_t val64)710 static void canfd_ier_post_write(RegisterInfo *reg, uint64_t val64)
711 {
712 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
713
714 canfd_update_irq(s);
715 }
716
canfd_icr_pre_write(RegisterInfo * reg,uint64_t val64)717 static uint64_t canfd_icr_pre_write(RegisterInfo *reg, uint64_t val64)
718 {
719 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
720 uint32_t val = val64;
721
722 s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
723
724 /*
725 * RXBOFLW_BI field is automatically cleared to default if RXBOFLW bit is
726 * cleared in ISR.
727 */
728 if (ARRAY_FIELD_EX32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1)) {
729 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 0);
730 }
731
732 canfd_update_irq(s);
733
734 return 0;
735 }
736
canfd_config_reset(XlnxVersalCANFDState * s)737 static void canfd_config_reset(XlnxVersalCANFDState *s)
738 {
739
740 unsigned int i;
741
742 /* Reset all the configuration registers. */
743 for (i = 0; i < R_RX_FIFO_WATERMARK_REGISTER; ++i) {
744 register_reset(&s->reg_info[i]);
745 }
746
747 canfd_update_irq(s);
748 }
749
canfd_config_mode(XlnxVersalCANFDState * s)750 static void canfd_config_mode(XlnxVersalCANFDState *s)
751 {
752 register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]);
753 register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]);
754 register_reset(&s->reg_info[R_STATUS_REGISTER]);
755
756 /* Put XlnxVersalCANFDState in configuration mode. */
757 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1);
758 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0);
759 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0);
760 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0);
761 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR_BIT, 0);
762 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 0);
763 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 0);
764 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0);
765 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0);
766 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0);
767
768 /* Clear the time stamp. */
769 ptimer_transaction_begin(s->canfd_timer);
770 ptimer_set_count(s->canfd_timer, 0);
771 ptimer_transaction_commit(s->canfd_timer);
772
773 canfd_update_irq(s);
774 }
775
update_status_register_mode_bits(XlnxVersalCANFDState * s)776 static void update_status_register_mode_bits(XlnxVersalCANFDState *s)
777 {
778 bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP);
779 bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP);
780 /* Wake up interrupt bit. */
781 bool wakeup_irq_val = !sleep_mode && sleep_status;
782 /* Sleep interrupt bit. */
783 bool sleep_irq_val = sleep_mode && !sleep_status;
784
785 /* Clear previous core mode status bits. */
786 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0);
787 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0);
788 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0);
789 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0);
790
791 /* set current mode bit and generate irqs accordingly. */
792 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) {
793 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1);
794 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) {
795 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1);
796 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP,
797 sleep_irq_val);
798 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
799 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
800 } else {
801 /* If all bits are zero, XlnxVersalCANFDState is set in normal mode. */
802 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1);
803 /* Set wakeup interrupt bit. */
804 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP,
805 wakeup_irq_val);
806 }
807
808 /* Put the CANFD in error active state. */
809 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ESTAT, 1);
810
811 canfd_update_irq(s);
812 }
813
canfd_msr_pre_write(RegisterInfo * reg,uint64_t val64)814 static uint64_t canfd_msr_pre_write(RegisterInfo *reg, uint64_t val64)
815 {
816 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
817 uint32_t val = val64;
818 uint8_t multi_mode = 0;
819
820 /*
821 * Multiple mode set check. This is done to make sure user doesn't set
822 * multiple modes.
823 */
824 multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) +
825 FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) +
826 FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP);
827
828 if (multi_mode > 1) {
829 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to configure several modes"
830 " simultaneously. One mode will be selected according to"
831 " their priority: LBACK > SLEEP > SNOOP.\n");
832 }
833
834 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
835 /* In configuration mode, any mode can be selected. */
836 s->regs[R_MODE_SELECT_REGISTER] = val;
837 } else {
838 bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP);
839
840 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit);
841
842 if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) {
843 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set LBACK mode"
844 " without setting CEN bit as 0\n");
845 } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) {
846 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set SNOOP mode"
847 " without setting CEN bit as 0\n");
848 }
849
850 update_status_register_mode_bits(s);
851 }
852
853 return s->regs[R_MODE_SELECT_REGISTER];
854 }
855
canfd_exit_sleep_mode(XlnxVersalCANFDState * s)856 static void canfd_exit_sleep_mode(XlnxVersalCANFDState *s)
857 {
858 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0);
859 update_status_register_mode_bits(s);
860 }
861
regs2frame(XlnxVersalCANFDState * s,qemu_can_frame * frame,uint32_t reg_num)862 static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame,
863 uint32_t reg_num)
864 {
865 uint32_t i = 0;
866 uint32_t j = 0;
867 uint32_t val = 0;
868 uint32_t dlc_reg_val = 0;
869 uint32_t dlc_value = 0;
870 uint32_t id_reg_val = 0;
871 bool is_rtr = false;
872
873 frame->flags = 0;
874
875 /* Check that reg_num should be within TX register space. */
876 assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE *
877 s->cfg.tx_fifo));
878
879 dlc_reg_val = s->regs[reg_num + 1];
880 dlc_value = FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, DLC);
881
882 id_reg_val = s->regs[reg_num];
883 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, IDE)) {
884 frame->can_id = (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID) << 18) |
885 (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID_EXT)) |
886 QEMU_CAN_EFF_FLAG;
887 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, RTR_RRS)) {
888 is_rtr = true;
889 }
890 } else {
891 frame->can_id = FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID);
892 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, SRR_RTR_RRS)) {
893 is_rtr = true;
894 }
895 }
896
897 if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) {
898 frame->flags |= QEMU_CAN_FRMF_TYPE_FD;
899
900 if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) {
901 frame->flags |= QEMU_CAN_FRMF_BRS;
902 }
903 } else {
904 if (is_rtr) {
905 frame->can_id |= QEMU_CAN_RTR_FLAG;
906 }
907 }
908
909 frame->can_dlc = can_dlc2len(dlc_value);
910
911 for (j = 0; j < frame->can_dlc; j++) {
912 val = 8 * (3 - i);
913
914 frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8);
915 i++;
916
917 if (i % 4 == 0) {
918 i = 0;
919 }
920 }
921 }
922
process_cancellation_requests(XlnxVersalCANFDState * s)923 static void process_cancellation_requests(XlnxVersalCANFDState *s)
924 {
925 uint32_t clear_mask = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &
926 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER];
927
928 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &= ~clear_mask;
929 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] &= ~clear_mask;
930
931 canfd_update_irq(s);
932 }
933
frame_to_reg_id(const qemu_can_frame * frame)934 static uint32_t frame_to_reg_id(const qemu_can_frame *frame)
935 {
936 uint32_t id_reg_val = 0;
937 const bool is_canfd_frame = frame->flags & QEMU_CAN_FRMF_TYPE_FD;
938 const bool is_rtr = !is_canfd_frame && (frame->can_id & QEMU_CAN_RTR_FLAG);
939
940 if (frame->can_id & QEMU_CAN_EFF_FLAG) {
941 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID,
942 (frame->can_id & QEMU_CAN_EFF_MASK) >> 18);
943 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID_EXT,
944 frame->can_id & QEMU_CAN_EFF_MASK);
945 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, IDE, 1);
946 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1);
947 if (is_rtr) {
948 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, RTR_RRS, 1);
949 }
950 } else {
951 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID,
952 frame->can_id & QEMU_CAN_SFF_MASK);
953 if (is_rtr) {
954 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1);
955 }
956 }
957
958 return id_reg_val;
959 }
960
store_rx_sequential(XlnxVersalCANFDState * s,const qemu_can_frame * frame,uint32_t fill_level,uint32_t read_index,uint32_t store_location,uint8_t rx_fifo,bool rx_fifo_id,uint8_t filter_index)961 static void store_rx_sequential(XlnxVersalCANFDState *s,
962 const qemu_can_frame *frame,
963 uint32_t fill_level, uint32_t read_index,
964 uint32_t store_location, uint8_t rx_fifo,
965 bool rx_fifo_id, uint8_t filter_index)
966 {
967 int i;
968 uint8_t dlc = frame->can_dlc;
969 uint8_t rx_reg_num = 0;
970 uint32_t dlc_reg_val = 0;
971 uint32_t data_reg_val = 0;
972
973 /* Getting RX0/1 fill level */
974 if ((fill_level) > rx_fifo - 1) {
975 g_autofree char *path = object_get_canonical_path(OBJECT(s));
976
977 qemu_log_mask(LOG_GUEST_ERROR, "%s: RX%d Buffer is full. Discarding the"
978 " message\n", path, rx_fifo_id);
979
980 /* Set the corresponding RF buffer overflow interrupt. */
981 if (rx_fifo_id == 0) {
982 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 1);
983 } else {
984 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 1);
985 }
986 } else {
987 uint16_t rx_timestamp = CANFD_TIMER_MAX -
988 ptimer_get_count(s->canfd_timer);
989
990 if (rx_timestamp == 0xFFFF) {
991 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 1);
992 } else {
993 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT,
994 rx_timestamp);
995 }
996
997 if (rx_fifo_id == 0) {
998 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL,
999 fill_level + 1);
1000 assert(store_location <=
1001 R_RB_ID_REGISTER + (s->cfg.rx0_fifo *
1002 NUM_REGS_PER_MSG_SPACE));
1003 } else {
1004 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1,
1005 fill_level + 1);
1006 assert(store_location <=
1007 R_RB_ID_REGISTER_1 + (s->cfg.rx1_fifo *
1008 NUM_REGS_PER_MSG_SPACE));
1009 }
1010
1011 s->regs[store_location] = frame_to_reg_id(frame);
1012
1013 dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, can_len2dlc(dlc));
1014
1015 if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) {
1016 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, 1);
1017
1018 if (frame->flags & QEMU_CAN_FRMF_BRS) {
1019 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1);
1020 }
1021 if (frame->flags & QEMU_CAN_FRMF_ESI) {
1022 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1);
1023 }
1024 }
1025
1026 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, TIMESTAMP, rx_timestamp);
1027 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, MATCHED_FILTER_INDEX,
1028 filter_index);
1029 s->regs[store_location + 1] = dlc_reg_val;
1030
1031 for (i = 0; i < dlc; i++) {
1032 /* Register size is 4 byte but frame->data each is 1 byte. */
1033 switch (i % 4) {
1034 case 0:
1035 rx_reg_num = i / 4;
1036
1037 data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0,
1038 frame->data[i]);
1039 break;
1040 case 1:
1041 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES1,
1042 frame->data[i]);
1043 break;
1044 case 2:
1045 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2,
1046 frame->data[i]);
1047 break;
1048 case 3:
1049 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3,
1050 frame->data[i]);
1051 /*
1052 * Last Bytes data which means we have all 4 bytes ready to
1053 * store in one rx regs.
1054 */
1055 s->regs[store_location + rx_reg_num + 2] = data_reg_val;
1056 break;
1057 }
1058 }
1059
1060 if (i % 4) {
1061 /*
1062 * In case DLC is not multiplier of 4, data is not saved to RX FIFO
1063 * in above switch case. Store the remaining bytes here.
1064 */
1065 s->regs[store_location + rx_reg_num + 2] = data_reg_val;
1066 }
1067
1068 /* set the interrupt as RXOK. */
1069 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
1070 }
1071 }
1072
update_rx_sequential(XlnxVersalCANFDState * s,const qemu_can_frame * frame)1073 static void update_rx_sequential(XlnxVersalCANFDState *s,
1074 const qemu_can_frame *frame)
1075 {
1076 bool filter_pass = false;
1077 uint8_t filter_index = 0;
1078 int i;
1079 int filter_partition = ARRAY_FIELD_EX32(s->regs,
1080 RX_FIFO_WATERMARK_REGISTER, RXFP);
1081 uint32_t store_location;
1082 uint32_t fill_level;
1083 uint32_t read_index;
1084 uint8_t store_index = 0;
1085 g_autofree char *path = NULL;
1086 /*
1087 * If all UAF bits are set to 0, then received messages are not stored
1088 * in the RX buffers.
1089 */
1090 if (s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]) {
1091 uint32_t acceptance_filter_status =
1092 s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER];
1093 const uint32_t reg_id = frame_to_reg_id(frame);
1094
1095 for (i = 0; i < 32; i++) {
1096 if (acceptance_filter_status & 0x1) {
1097 uint32_t msg_id_masked = s->regs[R_AFMR_REGISTER + 2 * i] &
1098 reg_id;
1099 uint32_t afir_id_masked = s->regs[R_AFIR_REGISTER + 2 * i] &
1100 s->regs[R_AFMR_REGISTER + 2 * i];
1101 uint16_t std_msg_id_masked = FIELD_EX32(msg_id_masked,
1102 AFIR_REGISTER, AIID);
1103 uint16_t std_afir_id_masked = FIELD_EX32(afir_id_masked,
1104 AFIR_REGISTER, AIID);
1105 uint32_t ext_msg_id_masked = FIELD_EX32(msg_id_masked,
1106 AFIR_REGISTER,
1107 AIID_EXT);
1108 uint32_t ext_afir_id_masked = FIELD_EX32(afir_id_masked,
1109 AFIR_REGISTER,
1110 AIID_EXT);
1111 bool ext_ide = FIELD_EX32(s->regs[R_AFMR_REGISTER + 2 * i],
1112 AFMR_REGISTER, AMIDE);
1113
1114 if (std_msg_id_masked == std_afir_id_masked) {
1115 if (ext_ide) {
1116 /* Extended message ID message. */
1117 if (ext_msg_id_masked == ext_afir_id_masked) {
1118 filter_pass = true;
1119 filter_index = i;
1120
1121 break;
1122 }
1123 } else {
1124 /* Standard message ID. */
1125 filter_pass = true;
1126 filter_index = i;
1127
1128 break;
1129 }
1130 }
1131 }
1132 acceptance_filter_status >>= 1;
1133 }
1134 }
1135
1136 if (!filter_pass) {
1137 path = object_get_canonical_path(OBJECT(s));
1138
1139 trace_xlnx_canfd_rx_fifo_filter_reject(path, frame->can_id,
1140 frame->can_dlc);
1141 } else {
1142 if (filter_index <= filter_partition) {
1143 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL);
1144 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, RI);
1145 store_index = read_index + fill_level;
1146
1147 if (store_index > s->cfg.rx0_fifo - 1) {
1148 store_index -= s->cfg.rx0_fifo;
1149 }
1150
1151 store_location = R_RB_ID_REGISTER +
1152 (store_index * NUM_REGS_PER_MSG_SPACE);
1153
1154 store_rx_sequential(s, frame, fill_level, read_index,
1155 store_location, s->cfg.rx0_fifo, 0,
1156 filter_index);
1157 } else {
1158 /* RX 1 fill level message */
1159 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER,
1160 FL_1);
1161 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER,
1162 RI_1);
1163 store_index = read_index + fill_level;
1164
1165 if (store_index > s->cfg.rx1_fifo - 1) {
1166 store_index -= s->cfg.rx1_fifo;
1167 }
1168
1169 store_location = R_RB_ID_REGISTER_1 +
1170 (store_index * NUM_REGS_PER_MSG_SPACE);
1171
1172 store_rx_sequential(s, frame, fill_level, read_index,
1173 store_location, s->cfg.rx1_fifo, 1,
1174 filter_index);
1175 }
1176
1177 path = object_get_canonical_path(OBJECT(s));
1178
1179 trace_xlnx_canfd_rx_data(path, frame->can_id, frame->can_dlc,
1180 frame->flags);
1181 canfd_update_irq(s);
1182 }
1183 }
1184
tx_ready_check(XlnxVersalCANFDState * s)1185 static bool tx_ready_check(XlnxVersalCANFDState *s)
1186 {
1187 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
1188 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1189
1190 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1191 " XlnxVersalCANFDState is in reset mode\n", path);
1192
1193 return false;
1194 }
1195
1196 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1197 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1198
1199 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1200 " XlnxVersalCANFDState is in configuration mode."
1201 " Reset the core so operations can start fresh\n",
1202 path);
1203 return false;
1204 }
1205
1206 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
1207 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1208
1209 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1210 " XlnxVersalCANFDState is in SNOOP MODE\n",
1211 path);
1212 return false;
1213 }
1214
1215 return true;
1216 }
1217
tx_fifo_stamp(XlnxVersalCANFDState * s,uint32_t tb0_regid)1218 static void tx_fifo_stamp(XlnxVersalCANFDState *s, uint32_t tb0_regid)
1219 {
1220 /*
1221 * If EFC bit in DLC message is set, this means we will store the
1222 * event of this transmitted message with time stamp.
1223 */
1224 uint32_t dlc_reg_val = 0;
1225
1226 if (FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, EFC)) {
1227 uint8_t dlc_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1228 DLC);
1229 bool fdf_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1230 FDF);
1231 bool brs_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1232 BRS);
1233 uint8_t mm_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1234 MM);
1235 uint8_t fill_level = ARRAY_FIELD_EX32(s->regs,
1236 TX_EVENT_FIFO_STATUS_REGISTER,
1237 TXE_FL);
1238 uint8_t read_index = ARRAY_FIELD_EX32(s->regs,
1239 TX_EVENT_FIFO_STATUS_REGISTER,
1240 TXE_RI);
1241 uint8_t store_index = fill_level + read_index;
1242
1243 if ((fill_level) > s->cfg.tx_fifo - 1) {
1244 qemu_log_mask(LOG_GUEST_ERROR, "TX Event Buffer is full."
1245 " Discarding the message\n");
1246 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEOFLW, 1);
1247 } else {
1248 if (store_index > s->cfg.tx_fifo - 1) {
1249 store_index -= s->cfg.tx_fifo;
1250 }
1251
1252 assert(store_index < s->cfg.tx_fifo);
1253
1254 uint32_t tx_event_reg0_id = R_TXE_FIFO_TB_ID_REGISTER +
1255 (store_index * 2);
1256
1257 /* Store message ID in TX event register. */
1258 s->regs[tx_event_reg0_id] = s->regs[tb0_regid];
1259
1260 uint16_t tx_timestamp = CANFD_TIMER_MAX -
1261 ptimer_get_count(s->canfd_timer);
1262
1263 /* Store DLC with time stamp in DLC regs. */
1264 dlc_reg_val = FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, DLC, dlc_val);
1265 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, FDF,
1266 fdf_val);
1267 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, BRS,
1268 brs_val);
1269 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, ET, 0x3);
1270 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, MM, mm_val);
1271 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP,
1272 tx_timestamp);
1273 s->regs[tx_event_reg0_id + 1] = dlc_reg_val;
1274
1275 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL,
1276 fill_level + 1);
1277 }
1278 }
1279 }
1280
g_cmp_ids(gconstpointer data1,gconstpointer data2,gpointer d)1281 static gint g_cmp_ids(gconstpointer data1, gconstpointer data2, gpointer d)
1282 {
1283 tx_ready_reg_info *tx_reg_1 = (tx_ready_reg_info *) data1;
1284 tx_ready_reg_info *tx_reg_2 = (tx_ready_reg_info *) data2;
1285
1286 if (tx_reg_1->can_id == tx_reg_2->can_id) {
1287 return (tx_reg_1->reg_num < tx_reg_2->reg_num) ? -1 : 1;
1288 }
1289 return (tx_reg_1->can_id < tx_reg_2->can_id) ? -1 : 1;
1290 }
1291
free_list(GSList * list)1292 static void free_list(GSList *list)
1293 {
1294 GSList *iterator = NULL;
1295
1296 for (iterator = list; iterator != NULL; iterator = iterator->next) {
1297 g_free((tx_ready_reg_info *)iterator->data);
1298 }
1299
1300 g_slist_free(list);
1301 }
1302
prepare_tx_data(XlnxVersalCANFDState * s)1303 static GSList *prepare_tx_data(XlnxVersalCANFDState *s)
1304 {
1305 uint8_t i = 0;
1306 GSList *list = NULL;
1307 uint32_t reg_num = 0;
1308 uint32_t reg_ready = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER];
1309
1310 /* First find the messages which are ready for transmission. */
1311 for (i = 0; i < s->cfg.tx_fifo; i++) {
1312 if (reg_ready & 1) {
1313 reg_num = R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * i);
1314 tx_ready_reg_info *temp = g_new(tx_ready_reg_info, 1);
1315
1316 temp->can_id = s->regs[reg_num];
1317 temp->reg_num = reg_num;
1318 list = g_slist_prepend(list, temp);
1319 list = g_slist_sort_with_data(list, g_cmp_ids, NULL);
1320 }
1321
1322 reg_ready >>= 1;
1323 }
1324
1325 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] = 0;
1326 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] = 0;
1327
1328 return list;
1329 }
1330
transfer_data(XlnxVersalCANFDState * s)1331 static void transfer_data(XlnxVersalCANFDState *s)
1332 {
1333 bool canfd_tx = tx_ready_check(s);
1334 GSList *list, *iterator = NULL;
1335 qemu_can_frame frame;
1336
1337 if (!canfd_tx) {
1338 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1339
1340 qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller not enabled for data"
1341 " transfer\n", path);
1342 return;
1343 }
1344
1345 list = prepare_tx_data(s);
1346 if (list == NULL) {
1347 return;
1348 }
1349
1350 for (iterator = list; iterator != NULL; iterator = iterator->next) {
1351 regs2frame(s, &frame,
1352 ((tx_ready_reg_info *)iterator->data)->reg_num);
1353
1354 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
1355 update_rx_sequential(s, &frame);
1356 tx_fifo_stamp(s, ((tx_ready_reg_info *)iterator->data)->reg_num);
1357
1358 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
1359 } else {
1360 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1361
1362 trace_xlnx_canfd_tx_data(path, frame.can_id, frame.can_dlc,
1363 frame.flags);
1364 can_bus_client_send(&s->bus_client, &frame, 1);
1365 tx_fifo_stamp(s,
1366 ((tx_ready_reg_info *)iterator->data)->reg_num);
1367
1368 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXRRS, 1);
1369
1370 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
1371 canfd_exit_sleep_mode(s);
1372 }
1373 }
1374 }
1375
1376 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
1377 free_list(list);
1378
1379 canfd_update_irq(s);
1380 }
1381
canfd_srr_pre_write(RegisterInfo * reg,uint64_t val64)1382 static uint64_t canfd_srr_pre_write(RegisterInfo *reg, uint64_t val64)
1383 {
1384 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1385 uint32_t val = val64;
1386
1387 ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
1388 FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
1389
1390 if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
1391 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1392
1393 trace_xlnx_canfd_reset(path, val64);
1394
1395 /* First, core will do software reset then will enter in config mode. */
1396 canfd_config_reset(s);
1397 } else if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1398 canfd_config_mode(s);
1399 } else {
1400 /*
1401 * Leave config mode. Now XlnxVersalCANFD core will enter Normal, Sleep,
1402 * snoop or Loopback mode depending upon LBACK, SLEEP, SNOOP register
1403 * states.
1404 */
1405 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0);
1406
1407 ptimer_transaction_begin(s->canfd_timer);
1408 ptimer_set_count(s->canfd_timer, 0);
1409 ptimer_transaction_commit(s->canfd_timer);
1410 update_status_register_mode_bits(s);
1411 transfer_data(s);
1412 }
1413
1414 return s->regs[R_SOFTWARE_RESET_REGISTER];
1415 }
1416
filter_mask(RegisterInfo * reg,uint64_t val64)1417 static uint64_t filter_mask(RegisterInfo *reg, uint64_t val64)
1418 {
1419 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1420 uint32_t reg_idx = (reg->access->addr) / 4;
1421 uint32_t val = val64;
1422 uint32_t filter_offset = (reg_idx - R_AFMR_REGISTER) / 2;
1423
1424 if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] &
1425 (1 << filter_offset))) {
1426 s->regs[reg_idx] = val;
1427 } else {
1428 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1429
1430 qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabled\n",
1431 path, filter_offset + 1);
1432 }
1433
1434 return s->regs[reg_idx];
1435 }
1436
filter_id(RegisterInfo * reg,uint64_t val64)1437 static uint64_t filter_id(RegisterInfo *reg, uint64_t val64)
1438 {
1439 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1440 hwaddr reg_idx = (reg->access->addr) / 4;
1441 uint32_t val = val64;
1442 uint32_t filter_offset = (reg_idx - R_AFIR_REGISTER) / 2;
1443
1444 if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] &
1445 (1 << filter_offset))) {
1446 s->regs[reg_idx] = val;
1447 } else {
1448 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1449
1450 qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabled\n",
1451 path, filter_offset + 1);
1452 }
1453
1454 return s->regs[reg_idx];
1455 }
1456
canfd_tx_fifo_status_prew(RegisterInfo * reg,uint64_t val64)1457 static uint64_t canfd_tx_fifo_status_prew(RegisterInfo *reg, uint64_t val64)
1458 {
1459 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1460 uint32_t val = val64;
1461 uint8_t read_ind = 0;
1462 uint8_t fill_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER,
1463 TXE_FL);
1464
1465 if (FIELD_EX32(val, TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI) && fill_ind) {
1466 read_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER,
1467 TXE_RI) + 1;
1468
1469 if (read_ind > s->cfg.tx_fifo - 1) {
1470 read_ind = 0;
1471 }
1472
1473 /*
1474 * Increase the read index by 1 and decrease the fill level by 1.
1475 */
1476 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI,
1477 read_ind);
1478 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL,
1479 fill_ind - 1);
1480 }
1481
1482 return s->regs[R_TX_EVENT_FIFO_STATUS_REGISTER];
1483 }
1484
canfd_rx_fifo_status_prew(RegisterInfo * reg,uint64_t val64)1485 static uint64_t canfd_rx_fifo_status_prew(RegisterInfo *reg, uint64_t val64)
1486 {
1487 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1488 uint32_t val = val64;
1489 uint8_t read_ind = 0;
1490 uint8_t fill_ind = 0;
1491
1492 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI)) {
1493 /* FL index is zero, setting IRI bit has no effect. */
1494 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) != 0) {
1495 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI) + 1;
1496
1497 if (read_ind > s->cfg.rx0_fifo - 1) {
1498 read_ind = 0;
1499 }
1500
1501 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) - 1;
1502
1503 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI, read_ind);
1504 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL, fill_ind);
1505 }
1506 }
1507
1508 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI_1)) {
1509 /* FL_1 index is zero, setting IRI_1 bit has no effect. */
1510 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) != 0) {
1511 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI_1) + 1;
1512
1513 if (read_ind > s->cfg.rx1_fifo - 1) {
1514 read_ind = 0;
1515 }
1516
1517 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) - 1;
1518
1519 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1, read_ind);
1520 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1, fill_ind);
1521 }
1522 }
1523
1524 return s->regs[R_RX_FIFO_STATUS_REGISTER];
1525 }
1526
canfd_tsr_pre_write(RegisterInfo * reg,uint64_t val64)1527 static uint64_t canfd_tsr_pre_write(RegisterInfo *reg, uint64_t val64)
1528 {
1529 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1530 uint32_t val = val64;
1531
1532 if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
1533 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, 0);
1534 ptimer_transaction_begin(s->canfd_timer);
1535 ptimer_set_count(s->canfd_timer, 0);
1536 ptimer_transaction_commit(s->canfd_timer);
1537 }
1538
1539 return 0;
1540 }
1541
canfd_trr_reg_prew(RegisterInfo * reg,uint64_t val64)1542 static uint64_t canfd_trr_reg_prew(RegisterInfo *reg, uint64_t val64)
1543 {
1544 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1545
1546 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
1547 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1548
1549 qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in SNOOP mode."
1550 " tx_ready_register will stay in reset mode\n", path);
1551 return 0;
1552 } else {
1553 return val64;
1554 }
1555 }
1556
canfd_trr_reg_postw(RegisterInfo * reg,uint64_t val64)1557 static void canfd_trr_reg_postw(RegisterInfo *reg, uint64_t val64)
1558 {
1559 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1560
1561 transfer_data(s);
1562 }
1563
canfd_cancel_reg_postw(RegisterInfo * reg,uint64_t val64)1564 static void canfd_cancel_reg_postw(RegisterInfo *reg, uint64_t val64)
1565 {
1566 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1567
1568 process_cancellation_requests(s);
1569 }
1570
canfd_write_check_prew(RegisterInfo * reg,uint64_t val64)1571 static uint64_t canfd_write_check_prew(RegisterInfo *reg, uint64_t val64)
1572 {
1573 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1574 uint32_t val = val64;
1575
1576 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1577 return val;
1578 }
1579 return 0;
1580 }
1581
1582 static const RegisterAccessInfo canfd_tx_regs[] = {
1583 { .name = "TB_ID_REGISTER", .addr = A_TB_ID_REGISTER,
1584 },{ .name = "TB0_DLC_REGISTER", .addr = A_TB0_DLC_REGISTER,
1585 },{ .name = "TB_DW0_REGISTER", .addr = A_TB_DW0_REGISTER,
1586 },{ .name = "TB_DW1_REGISTER", .addr = A_TB_DW1_REGISTER,
1587 },{ .name = "TB_DW2_REGISTER", .addr = A_TB_DW2_REGISTER,
1588 },{ .name = "TB_DW3_REGISTER", .addr = A_TB_DW3_REGISTER,
1589 },{ .name = "TB_DW4_REGISTER", .addr = A_TB_DW4_REGISTER,
1590 },{ .name = "TB_DW5_REGISTER", .addr = A_TB_DW5_REGISTER,
1591 },{ .name = "TB_DW6_REGISTER", .addr = A_TB_DW6_REGISTER,
1592 },{ .name = "TB_DW7_REGISTER", .addr = A_TB_DW7_REGISTER,
1593 },{ .name = "TB_DW8_REGISTER", .addr = A_TB_DW8_REGISTER,
1594 },{ .name = "TB_DW9_REGISTER", .addr = A_TB_DW9_REGISTER,
1595 },{ .name = "TB_DW10_REGISTER", .addr = A_TB_DW10_REGISTER,
1596 },{ .name = "TB_DW11_REGISTER", .addr = A_TB_DW11_REGISTER,
1597 },{ .name = "TB_DW12_REGISTER", .addr = A_TB_DW12_REGISTER,
1598 },{ .name = "TB_DW13_REGISTER", .addr = A_TB_DW13_REGISTER,
1599 },{ .name = "TB_DW14_REGISTER", .addr = A_TB_DW14_REGISTER,
1600 },{ .name = "TB_DW15_REGISTER", .addr = A_TB_DW15_REGISTER,
1601 }
1602 };
1603
1604 static const RegisterAccessInfo canfd_rx0_regs[] = {
1605 { .name = "RB_ID_REGISTER", .addr = A_RB_ID_REGISTER,
1606 .ro = 0xffffffff,
1607 },{ .name = "RB_DLC_REGISTER", .addr = A_RB_DLC_REGISTER,
1608 .ro = 0xfe1fffff,
1609 },{ .name = "RB_DW0_REGISTER", .addr = A_RB_DW0_REGISTER,
1610 .ro = 0xffffffff,
1611 },{ .name = "RB_DW1_REGISTER", .addr = A_RB_DW1_REGISTER,
1612 .ro = 0xffffffff,
1613 },{ .name = "RB_DW2_REGISTER", .addr = A_RB_DW2_REGISTER,
1614 .ro = 0xffffffff,
1615 },{ .name = "RB_DW3_REGISTER", .addr = A_RB_DW3_REGISTER,
1616 .ro = 0xffffffff,
1617 },{ .name = "RB_DW4_REGISTER", .addr = A_RB_DW4_REGISTER,
1618 .ro = 0xffffffff,
1619 },{ .name = "RB_DW5_REGISTER", .addr = A_RB_DW5_REGISTER,
1620 .ro = 0xffffffff,
1621 },{ .name = "RB_DW6_REGISTER", .addr = A_RB_DW6_REGISTER,
1622 .ro = 0xffffffff,
1623 },{ .name = "RB_DW7_REGISTER", .addr = A_RB_DW7_REGISTER,
1624 .ro = 0xffffffff,
1625 },{ .name = "RB_DW8_REGISTER", .addr = A_RB_DW8_REGISTER,
1626 .ro = 0xffffffff,
1627 },{ .name = "RB_DW9_REGISTER", .addr = A_RB_DW9_REGISTER,
1628 .ro = 0xffffffff,
1629 },{ .name = "RB_DW10_REGISTER", .addr = A_RB_DW10_REGISTER,
1630 .ro = 0xffffffff,
1631 },{ .name = "RB_DW11_REGISTER", .addr = A_RB_DW11_REGISTER,
1632 .ro = 0xffffffff,
1633 },{ .name = "RB_DW12_REGISTER", .addr = A_RB_DW12_REGISTER,
1634 .ro = 0xffffffff,
1635 },{ .name = "RB_DW13_REGISTER", .addr = A_RB_DW13_REGISTER,
1636 .ro = 0xffffffff,
1637 },{ .name = "RB_DW14_REGISTER", .addr = A_RB_DW14_REGISTER,
1638 .ro = 0xffffffff,
1639 },{ .name = "RB_DW15_REGISTER", .addr = A_RB_DW15_REGISTER,
1640 .ro = 0xffffffff,
1641 }
1642 };
1643
1644 static const RegisterAccessInfo canfd_rx1_regs[] = {
1645 { .name = "RB_ID_REGISTER_1", .addr = A_RB_ID_REGISTER_1,
1646 .ro = 0xffffffff,
1647 },{ .name = "RB_DLC_REGISTER_1", .addr = A_RB_DLC_REGISTER_1,
1648 .ro = 0xfe1fffff,
1649 },{ .name = "RB0_DW0_REGISTER_1", .addr = A_RB0_DW0_REGISTER_1,
1650 .ro = 0xffffffff,
1651 },{ .name = "RB_DW1_REGISTER_1", .addr = A_RB_DW1_REGISTER_1,
1652 .ro = 0xffffffff,
1653 },{ .name = "RB_DW2_REGISTER_1", .addr = A_RB_DW2_REGISTER_1,
1654 .ro = 0xffffffff,
1655 },{ .name = "RB_DW3_REGISTER_1", .addr = A_RB_DW3_REGISTER_1,
1656 .ro = 0xffffffff,
1657 },{ .name = "RB_DW4_REGISTER_1", .addr = A_RB_DW4_REGISTER_1,
1658 .ro = 0xffffffff,
1659 },{ .name = "RB_DW5_REGISTER_1", .addr = A_RB_DW5_REGISTER_1,
1660 .ro = 0xffffffff,
1661 },{ .name = "RB_DW6_REGISTER_1", .addr = A_RB_DW6_REGISTER_1,
1662 .ro = 0xffffffff,
1663 },{ .name = "RB_DW7_REGISTER_1", .addr = A_RB_DW7_REGISTER_1,
1664 .ro = 0xffffffff,
1665 },{ .name = "RB_DW8_REGISTER_1", .addr = A_RB_DW8_REGISTER_1,
1666 .ro = 0xffffffff,
1667 },{ .name = "RB_DW9_REGISTER_1", .addr = A_RB_DW9_REGISTER_1,
1668 .ro = 0xffffffff,
1669 },{ .name = "RB_DW10_REGISTER_1", .addr = A_RB_DW10_REGISTER_1,
1670 .ro = 0xffffffff,
1671 },{ .name = "RB_DW11_REGISTER_1", .addr = A_RB_DW11_REGISTER_1,
1672 .ro = 0xffffffff,
1673 },{ .name = "RB_DW12_REGISTER_1", .addr = A_RB_DW12_REGISTER_1,
1674 .ro = 0xffffffff,
1675 },{ .name = "RB_DW13_REGISTER_1", .addr = A_RB_DW13_REGISTER_1,
1676 .ro = 0xffffffff,
1677 },{ .name = "RB_DW14_REGISTER_1", .addr = A_RB_DW14_REGISTER_1,
1678 .ro = 0xffffffff,
1679 },{ .name = "RB_DW15_REGISTER_1", .addr = A_RB_DW15_REGISTER_1,
1680 .ro = 0xffffffff,
1681 }
1682 };
1683
1684 /* Acceptance filter registers. */
1685 static const RegisterAccessInfo canfd_af_regs[] = {
1686 { .name = "AFMR_REGISTER", .addr = A_AFMR_REGISTER,
1687 .pre_write = filter_mask,
1688 },{ .name = "AFIR_REGISTER", .addr = A_AFIR_REGISTER,
1689 .pre_write = filter_id,
1690 }
1691 };
1692
1693 static const RegisterAccessInfo canfd_txe_regs[] = {
1694 { .name = "TXE_FIFO_TB_ID_REGISTER", .addr = A_TXE_FIFO_TB_ID_REGISTER,
1695 .ro = 0xffffffff,
1696 },{ .name = "TXE_FIFO_TB_DLC_REGISTER", .addr = A_TXE_FIFO_TB_DLC_REGISTER,
1697 .ro = 0xffffffff,
1698 }
1699 };
1700
1701 static const RegisterAccessInfo canfd_regs_info[] = {
1702 { .name = "SOFTWARE_RESET_REGISTER", .addr = A_SOFTWARE_RESET_REGISTER,
1703 .pre_write = canfd_srr_pre_write,
1704 },{ .name = "MODE_SELECT_REGISTER", .addr = A_MODE_SELECT_REGISTER,
1705 .pre_write = canfd_msr_pre_write,
1706 },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER",
1707 .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER,
1708 .pre_write = canfd_write_check_prew,
1709 },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER",
1710 .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER,
1711 .pre_write = canfd_write_check_prew,
1712 },{ .name = "ERROR_COUNTER_REGISTER", .addr = A_ERROR_COUNTER_REGISTER,
1713 .ro = 0xffff,
1714 },{ .name = "ERROR_STATUS_REGISTER", .addr = A_ERROR_STATUS_REGISTER,
1715 .w1c = 0xf1f,
1716 },{ .name = "STATUS_REGISTER", .addr = A_STATUS_REGISTER,
1717 .reset = 0x1,
1718 .ro = 0x7f17ff,
1719 },{ .name = "INTERRUPT_STATUS_REGISTER",
1720 .addr = A_INTERRUPT_STATUS_REGISTER,
1721 .ro = 0xffffff7f,
1722 },{ .name = "INTERRUPT_ENABLE_REGISTER",
1723 .addr = A_INTERRUPT_ENABLE_REGISTER,
1724 .post_write = canfd_ier_post_write,
1725 },{ .name = "INTERRUPT_CLEAR_REGISTER",
1726 .addr = A_INTERRUPT_CLEAR_REGISTER, .pre_write = canfd_icr_pre_write,
1727 },{ .name = "TIMESTAMP_REGISTER", .addr = A_TIMESTAMP_REGISTER,
1728 .ro = 0xffff0000,
1729 .pre_write = canfd_tsr_pre_write,
1730 },{ .name = "DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER",
1731 .addr = A_DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER,
1732 .pre_write = canfd_write_check_prew,
1733 },{ .name = "DATA_PHASE_BIT_TIMING_REGISTER",
1734 .addr = A_DATA_PHASE_BIT_TIMING_REGISTER,
1735 .pre_write = canfd_write_check_prew,
1736 },{ .name = "TX_BUFFER_READY_REQUEST_REGISTER",
1737 .addr = A_TX_BUFFER_READY_REQUEST_REGISTER,
1738 .pre_write = canfd_trr_reg_prew,
1739 .post_write = canfd_trr_reg_postw,
1740 },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER",
1741 .addr = A_INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER,
1742 },{ .name = "TX_BUFFER_CANCEL_REQUEST_REGISTER",
1743 .addr = A_TX_BUFFER_CANCEL_REQUEST_REGISTER,
1744 .post_write = canfd_cancel_reg_postw,
1745 },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER",
1746 .addr = A_INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER,
1747 },{ .name = "TX_EVENT_FIFO_STATUS_REGISTER",
1748 .addr = A_TX_EVENT_FIFO_STATUS_REGISTER,
1749 .ro = 0x3f1f, .pre_write = canfd_tx_fifo_status_prew,
1750 },{ .name = "TX_EVENT_FIFO_WATERMARK_REGISTER",
1751 .addr = A_TX_EVENT_FIFO_WATERMARK_REGISTER,
1752 .reset = 0xf,
1753 .pre_write = canfd_write_check_prew,
1754 },{ .name = "ACCEPTANCE_FILTER_CONTROL_REGISTER",
1755 .addr = A_ACCEPTANCE_FILTER_CONTROL_REGISTER,
1756 },{ .name = "RX_FIFO_STATUS_REGISTER", .addr = A_RX_FIFO_STATUS_REGISTER,
1757 .ro = 0x7f3f7f3f, .pre_write = canfd_rx_fifo_status_prew,
1758 },{ .name = "RX_FIFO_WATERMARK_REGISTER",
1759 .addr = A_RX_FIFO_WATERMARK_REGISTER,
1760 .reset = 0x1f0f0f,
1761 .pre_write = canfd_write_check_prew,
1762 }
1763 };
1764
xlnx_versal_canfd_ptimer_cb(void * opaque)1765 static void xlnx_versal_canfd_ptimer_cb(void *opaque)
1766 {
1767 /* No action required on the timer rollover. */
1768 }
1769
1770 static const MemoryRegionOps canfd_ops = {
1771 .read = register_read_memory,
1772 .write = register_write_memory,
1773 .endianness = DEVICE_LITTLE_ENDIAN,
1774 .valid = {
1775 .min_access_size = 4,
1776 .max_access_size = 4,
1777 },
1778 };
1779
canfd_reset(DeviceState * dev)1780 static void canfd_reset(DeviceState *dev)
1781 {
1782 XlnxVersalCANFDState *s = XILINX_CANFD(dev);
1783 unsigned int i;
1784
1785 for (i = 0; i < ARRAY_SIZE(s->reg_info); ++i) {
1786 register_reset(&s->reg_info[i]);
1787 }
1788
1789 ptimer_transaction_begin(s->canfd_timer);
1790 ptimer_set_count(s->canfd_timer, 0);
1791 ptimer_transaction_commit(s->canfd_timer);
1792 }
1793
can_xilinx_canfd_receive(CanBusClientState * client)1794 static bool can_xilinx_canfd_receive(CanBusClientState *client)
1795 {
1796 XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState,
1797 bus_client);
1798
1799 bool reset_state = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST);
1800 bool can_enabled = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN);
1801
1802 return !reset_state && can_enabled;
1803 }
1804
canfd_xilinx_receive(CanBusClientState * client,const qemu_can_frame * buf,size_t buf_size)1805 static ssize_t canfd_xilinx_receive(CanBusClientState *client,
1806 const qemu_can_frame *buf,
1807 size_t buf_size)
1808 {
1809 XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState,
1810 bus_client);
1811 const qemu_can_frame *frame = buf;
1812
1813 assert(buf_size > 0);
1814
1815 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
1816 /*
1817 * XlnxVersalCANFDState will not participate in normal bus communication
1818 * and does not receive any messages transmitted by other CAN nodes.
1819 */
1820 return 1;
1821 }
1822
1823 /* Update the status register that we are receiving message. */
1824 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 1);
1825
1826 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
1827 /* Snoop Mode: Just keep the data. no response back. */
1828 update_rx_sequential(s, frame);
1829 } else {
1830 if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
1831 /*
1832 * XlnxVersalCANFDState is in sleep mode. Any data on bus will bring
1833 * it to the wake up state.
1834 */
1835 canfd_exit_sleep_mode(s);
1836 }
1837
1838 update_rx_sequential(s, frame);
1839 }
1840
1841 /* Message processing done. Update the status back to !busy */
1842 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 0);
1843 return 1;
1844 }
1845
1846 static CanBusClientInfo canfd_xilinx_bus_client_info = {
1847 .can_receive = can_xilinx_canfd_receive,
1848 .receive = canfd_xilinx_receive,
1849 };
1850
xlnx_canfd_connect_to_bus(XlnxVersalCANFDState * s,CanBusState * bus)1851 static int xlnx_canfd_connect_to_bus(XlnxVersalCANFDState *s,
1852 CanBusState *bus)
1853 {
1854 s->bus_client.info = &canfd_xilinx_bus_client_info;
1855
1856 return can_bus_insert_client(bus, &s->bus_client);
1857 }
1858
1859 #define NUM_REG_PER_AF ARRAY_SIZE(canfd_af_regs)
1860 #define NUM_AF 32
1861 #define NUM_REG_PER_TXE ARRAY_SIZE(canfd_txe_regs)
1862 #define NUM_TXE 32
1863
canfd_populate_regarray(XlnxVersalCANFDState * s,RegisterInfoArray * r_array,int pos,const RegisterAccessInfo * rae,int num_rae)1864 static int canfd_populate_regarray(XlnxVersalCANFDState *s,
1865 RegisterInfoArray *r_array, int pos,
1866 const RegisterAccessInfo *rae,
1867 int num_rae)
1868 {
1869 int i;
1870
1871 for (i = 0; i < num_rae; i++) {
1872 int index = rae[i].addr / 4;
1873 RegisterInfo *r = &s->reg_info[index];
1874
1875 object_initialize(r, sizeof(*r), TYPE_REGISTER);
1876
1877 *r = (RegisterInfo) {
1878 .data = &s->regs[index],
1879 .data_size = sizeof(uint32_t),
1880 .access = &rae[i],
1881 .opaque = OBJECT(s),
1882 };
1883
1884 r_array->r[i + pos] = r;
1885 }
1886 return i + pos;
1887 }
1888
canfd_create_rai(RegisterAccessInfo * rai_array,const RegisterAccessInfo * canfd_regs,int template_rai_array_sz,int num_template_to_copy)1889 static void canfd_create_rai(RegisterAccessInfo *rai_array,
1890 const RegisterAccessInfo *canfd_regs,
1891 int template_rai_array_sz,
1892 int num_template_to_copy)
1893 {
1894 int i;
1895 int reg_num;
1896
1897 for (reg_num = 0; reg_num < num_template_to_copy; reg_num++) {
1898 int pos = reg_num * template_rai_array_sz;
1899
1900 memcpy(rai_array + pos, canfd_regs,
1901 template_rai_array_sz * sizeof(RegisterAccessInfo));
1902
1903 for (i = 0; i < template_rai_array_sz; i++) {
1904 const char *name = canfd_regs[i].name;
1905 uint64_t addr = canfd_regs[i].addr;
1906 rai_array[i + pos].name = g_strdup_printf("%s%d", name, reg_num);
1907 rai_array[i + pos].addr = addr + pos * 4;
1908 }
1909 }
1910 }
1911
canfd_create_regarray(XlnxVersalCANFDState * s)1912 static RegisterInfoArray *canfd_create_regarray(XlnxVersalCANFDState *s)
1913 {
1914 const char *device_prefix = object_get_typename(OBJECT(s));
1915 uint64_t memory_size = XLNX_VERSAL_CANFD_R_MAX * 4;
1916 int num_regs;
1917 int pos = 0;
1918 RegisterInfoArray *r_array;
1919
1920 num_regs = ARRAY_SIZE(canfd_regs_info) +
1921 s->cfg.tx_fifo * NUM_REGS_PER_MSG_SPACE +
1922 s->cfg.rx0_fifo * NUM_REGS_PER_MSG_SPACE +
1923 NUM_AF * NUM_REG_PER_AF +
1924 NUM_TXE * NUM_REG_PER_TXE;
1925
1926 s->tx_regs = g_new0(RegisterAccessInfo,
1927 s->cfg.tx_fifo * ARRAY_SIZE(canfd_tx_regs));
1928
1929 canfd_create_rai(s->tx_regs, canfd_tx_regs,
1930 ARRAY_SIZE(canfd_tx_regs), s->cfg.tx_fifo);
1931
1932 s->rx0_regs = g_new0(RegisterAccessInfo,
1933 s->cfg.rx0_fifo * ARRAY_SIZE(canfd_rx0_regs));
1934
1935 canfd_create_rai(s->rx0_regs, canfd_rx0_regs,
1936 ARRAY_SIZE(canfd_rx0_regs), s->cfg.rx0_fifo);
1937
1938 s->af_regs = g_new0(RegisterAccessInfo,
1939 NUM_AF * ARRAY_SIZE(canfd_af_regs));
1940
1941 canfd_create_rai(s->af_regs, canfd_af_regs,
1942 ARRAY_SIZE(canfd_af_regs), NUM_AF);
1943
1944 s->txe_regs = g_new0(RegisterAccessInfo,
1945 NUM_TXE * ARRAY_SIZE(canfd_txe_regs));
1946
1947 canfd_create_rai(s->txe_regs, canfd_txe_regs,
1948 ARRAY_SIZE(canfd_txe_regs), NUM_TXE);
1949
1950 if (s->cfg.enable_rx_fifo1) {
1951 num_regs += s->cfg.rx1_fifo * NUM_REGS_PER_MSG_SPACE;
1952
1953 s->rx1_regs = g_new0(RegisterAccessInfo,
1954 s->cfg.rx1_fifo * ARRAY_SIZE(canfd_rx1_regs));
1955
1956 canfd_create_rai(s->rx1_regs, canfd_rx1_regs,
1957 ARRAY_SIZE(canfd_rx1_regs), s->cfg.rx1_fifo);
1958 }
1959
1960 r_array = g_new0(RegisterInfoArray, 1);
1961 r_array->r = g_new0(RegisterInfo * , num_regs);
1962 r_array->num_elements = num_regs;
1963 r_array->prefix = device_prefix;
1964
1965 pos = canfd_populate_regarray(s, r_array, pos,
1966 canfd_regs_info,
1967 ARRAY_SIZE(canfd_regs_info));
1968 pos = canfd_populate_regarray(s, r_array, pos,
1969 s->tx_regs, s->cfg.tx_fifo *
1970 NUM_REGS_PER_MSG_SPACE);
1971 pos = canfd_populate_regarray(s, r_array, pos,
1972 s->rx0_regs, s->cfg.rx0_fifo *
1973 NUM_REGS_PER_MSG_SPACE);
1974 if (s->cfg.enable_rx_fifo1) {
1975 pos = canfd_populate_regarray(s, r_array, pos,
1976 s->rx1_regs, s->cfg.rx1_fifo *
1977 NUM_REGS_PER_MSG_SPACE);
1978 }
1979 pos = canfd_populate_regarray(s, r_array, pos,
1980 s->af_regs, NUM_AF * NUM_REG_PER_AF);
1981 pos = canfd_populate_regarray(s, r_array, pos,
1982 s->txe_regs, NUM_TXE * NUM_REG_PER_TXE);
1983
1984 memory_region_init_io(&r_array->mem, OBJECT(s), &canfd_ops, r_array,
1985 device_prefix, memory_size);
1986 return r_array;
1987 }
1988
canfd_realize(DeviceState * dev,Error ** errp)1989 static void canfd_realize(DeviceState *dev, Error **errp)
1990 {
1991 XlnxVersalCANFDState *s = XILINX_CANFD(dev);
1992 RegisterInfoArray *reg_array;
1993
1994 reg_array = canfd_create_regarray(s);
1995 memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem);
1996 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1997 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_canfd_int);
1998
1999 if (s->canfdbus) {
2000 if (xlnx_canfd_connect_to_bus(s, s->canfdbus) < 0) {
2001 g_autofree char *path = object_get_canonical_path(OBJECT(s));
2002
2003 error_setg(errp, "%s: xlnx_canfd_connect_to_bus failed", path);
2004 return;
2005 }
2006
2007 }
2008
2009 /* Allocate a new timer. */
2010 s->canfd_timer = ptimer_init(xlnx_versal_canfd_ptimer_cb, s,
2011 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
2012 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
2013 PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
2014
2015 ptimer_transaction_begin(s->canfd_timer);
2016
2017 ptimer_set_freq(s->canfd_timer, s->cfg.ext_clk_freq);
2018 ptimer_set_limit(s->canfd_timer, CANFD_TIMER_MAX, 1);
2019 ptimer_run(s->canfd_timer, 0);
2020 ptimer_transaction_commit(s->canfd_timer);
2021 }
2022
canfd_init(Object * obj)2023 static void canfd_init(Object *obj)
2024 {
2025 XlnxVersalCANFDState *s = XILINX_CANFD(obj);
2026
2027 memory_region_init(&s->iomem, obj, TYPE_XILINX_CANFD,
2028 XLNX_VERSAL_CANFD_R_MAX * 4);
2029 }
2030
2031 static const VMStateDescription vmstate_canfd = {
2032 .name = TYPE_XILINX_CANFD,
2033 .version_id = 1,
2034 .minimum_version_id = 1,
2035 .fields = (const VMStateField[]) {
2036 VMSTATE_UINT32_ARRAY(regs, XlnxVersalCANFDState,
2037 XLNX_VERSAL_CANFD_R_MAX),
2038 VMSTATE_PTIMER(canfd_timer, XlnxVersalCANFDState),
2039 VMSTATE_END_OF_LIST(),
2040 }
2041 };
2042
2043 static const Property canfd_core_properties[] = {
2044 DEFINE_PROP_UINT8("rx-fifo0", XlnxVersalCANFDState, cfg.rx0_fifo, 0x40),
2045 DEFINE_PROP_UINT8("rx-fifo1", XlnxVersalCANFDState, cfg.rx1_fifo, 0x40),
2046 DEFINE_PROP_UINT8("tx-fifo", XlnxVersalCANFDState, cfg.tx_fifo, 0x20),
2047 DEFINE_PROP_BOOL("enable-rx-fifo1", XlnxVersalCANFDState,
2048 cfg.enable_rx_fifo1, true),
2049 DEFINE_PROP_UINT32("ext_clk_freq", XlnxVersalCANFDState, cfg.ext_clk_freq,
2050 CANFD_DEFAULT_CLOCK),
2051 DEFINE_PROP_LINK("canfdbus", XlnxVersalCANFDState, canfdbus, TYPE_CAN_BUS,
2052 CanBusState *),
2053 };
2054
canfd_class_init(ObjectClass * klass,const void * data)2055 static void canfd_class_init(ObjectClass *klass, const void *data)
2056 {
2057 DeviceClass *dc = DEVICE_CLASS(klass);
2058
2059 device_class_set_legacy_reset(dc, canfd_reset);
2060 dc->realize = canfd_realize;
2061 device_class_set_props(dc, canfd_core_properties);
2062 dc->vmsd = &vmstate_canfd;
2063 }
2064
2065 static const TypeInfo canfd_info = {
2066 .name = TYPE_XILINX_CANFD,
2067 .parent = TYPE_SYS_BUS_DEVICE,
2068 .instance_size = sizeof(XlnxVersalCANFDState),
2069 .class_init = canfd_class_init,
2070 .instance_init = canfd_init,
2071 };
2072
canfd_register_types(void)2073 static void canfd_register_types(void)
2074 {
2075 type_register_static(&canfd_info);
2076 }
2077
2078 type_init(canfd_register_types)
2079