1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_H__ 27 #define __DAL_CLK_MGR_H__ 28 29 #include "dc.h" 30 #include "dm_pp_smu.h" 31 32 #define DCN_MINIMUM_DISPCLK_Khz 100000 33 #define DCN_MINIMUM_DPPCLK_Khz 100000 34 35 /* Constants */ 36 #define DDR4_DRAM_WIDTH 64 37 #define WM_A 0 38 #define WM_B 1 39 #define WM_C 2 40 #define WM_D 3 41 #define WM_SET_COUNT 4 42 43 #define DCN_MINIMUM_DISPCLK_Khz 100000 44 #define DCN_MINIMUM_DPPCLK_Khz 100000 45 46 struct dcn3_clk_internal { 47 int dummy; 48 // TODO: 49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 51 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 53 uint32_t CLK1_CLK4_CURRENT_CNT; 54 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 55 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 56 57 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 58 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 59 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 60 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 61 62 uint32_t CLK4_CLK0_CURRENT_CNT; //fclk 63 }; 64 65 struct dcn35_clk_internal { 66 int dummy; 67 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 68 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 69 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 70 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 71 uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk 72 //uint32_t CLK1_CLK5_CURRENT_CNT; //dpiaclk 73 //uint32_t CLK1_CLK6_CURRENT_CNT; //srdbgclk 74 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 75 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 76 77 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 78 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 79 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 80 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 81 uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass 82 }; 83 84 struct dcn301_clk_internal { 85 int dummy; 86 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 87 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 88 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 89 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 90 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 91 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 92 93 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 94 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 95 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 96 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 97 }; 98 99 /* Will these bw structures be ASIC specific? */ 100 101 #define MAX_NUM_DPM_LVL 8 102 #define WM_SET_COUNT 4 103 104 105 struct clk_limit_table_entry { 106 unsigned int voltage; /* milivolts withh 2 fractional bits */ 107 unsigned int dcfclk_mhz; 108 unsigned int fclk_mhz; 109 unsigned int memclk_mhz; 110 unsigned int socclk_mhz; 111 unsigned int dtbclk_mhz; 112 unsigned int dispclk_mhz; 113 unsigned int dppclk_mhz; 114 unsigned int phyclk_mhz; 115 unsigned int phyclk_d18_mhz; 116 unsigned int wck_ratio; 117 }; 118 119 struct clk_limit_num_entries { 120 unsigned int num_dcfclk_levels; 121 unsigned int num_fclk_levels; 122 unsigned int num_memclk_levels; 123 unsigned int num_socclk_levels; 124 unsigned int num_dtbclk_levels; 125 unsigned int num_dispclk_levels; 126 unsigned int num_dppclk_levels; 127 unsigned int num_phyclk_levels; 128 unsigned int num_phyclk_d18_levels; 129 }; 130 131 /* This table is contiguous */ 132 struct clk_limit_table { 133 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; 134 struct clk_limit_num_entries num_entries_per_clk; 135 unsigned int num_entries; /* highest populated dpm level for back compatibility */ 136 }; 137 138 struct wm_range_table_entry { 139 unsigned int wm_inst; 140 unsigned int wm_type; 141 double pstate_latency_us; 142 double sr_exit_time_us; 143 double sr_enter_plus_exit_time_us; 144 bool valid; 145 }; 146 147 struct nv_wm_range_entry { 148 bool valid; 149 150 struct { 151 uint8_t wm_type; 152 uint16_t min_dcfclk; 153 uint16_t max_dcfclk; 154 uint16_t min_uclk; 155 uint16_t max_uclk; 156 } pmfw_breakdown; 157 158 struct { 159 double pstate_latency_us; 160 double sr_exit_time_us; 161 double sr_enter_plus_exit_time_us; 162 double fclk_change_latency_us; 163 } dml_input; 164 }; 165 166 struct clk_log_info { 167 bool enabled; 168 char *pBuf; 169 unsigned int bufSize; 170 unsigned int *sum_chars_printed; 171 }; 172 173 struct clk_state_registers_and_bypass { 174 uint32_t dcfclk; 175 uint32_t dcf_deep_sleep_divider; 176 uint32_t dcf_deep_sleep_allow; 177 uint32_t dprefclk; 178 uint32_t dispclk; 179 uint32_t dppclk; 180 uint32_t dtbclk; 181 182 uint32_t dppclk_bypass; 183 uint32_t dcfclk_bypass; 184 uint32_t dprefclk_bypass; 185 uint32_t dispclk_bypass; 186 }; 187 188 struct rv1_clk_internal { 189 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 190 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 191 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 192 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 193 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 194 195 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 196 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass 197 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass 198 }; 199 200 struct rn_clk_internal { 201 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 202 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 203 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 204 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 205 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 206 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 207 208 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 209 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 210 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 211 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 212 213 }; 214 215 /* For dtn logging and debugging */ 216 struct clk_state_registers { 217 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 218 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 219 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 220 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 221 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 222 }; 223 224 /* TODO: combine this with the above */ 225 struct clk_bypass { 226 uint32_t dcfclk_bypass; 227 uint32_t dispclk_pypass; 228 uint32_t dprefclk_bypass; 229 }; 230 /* 231 * This table is not contiguous, can have holes, each 232 * entry correspond to one set of WM. For example if 233 * we have 2 DPM and LPDDR, we will WM set A, B and 234 * D occupied, C will be emptry. 235 */ 236 struct wm_table { 237 union { 238 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; 239 struct wm_range_table_entry entries[WM_SET_COUNT]; 240 }; 241 }; 242 243 struct dummy_pstate_entry { 244 unsigned int dram_speed_mts; 245 double dummy_pstate_latency_us; 246 }; 247 248 struct clk_bw_params { 249 unsigned int vram_type; 250 unsigned int num_channels; 251 unsigned int dram_channel_width_bytes; 252 unsigned int dispclk_vco_khz; 253 unsigned int dc_mode_softmax_memclk; 254 unsigned int max_memclk_mhz; 255 struct clk_limit_table clk_table; 256 struct wm_table wm_table; 257 struct dummy_pstate_entry dummy_pstate_table[4]; 258 struct clk_limit_table_entry dc_mode_limit; 259 }; 260 /* Public interfaces */ 261 262 struct clk_states { 263 uint32_t dprefclk_khz; 264 }; 265 266 struct clk_mgr_funcs { 267 /* 268 * This function should set new clocks based on the input "safe_to_lower". 269 * If safe_to_lower == false, then only clocks which are to be increased 270 * should changed. 271 * If safe_to_lower == true, then only clocks which are to be decreased 272 * should be changed. 273 */ 274 void (*update_clocks)(struct clk_mgr *clk_mgr, 275 struct dc_state *context, 276 bool safe_to_lower); 277 278 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 279 int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr); 280 281 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 282 void (*exit_low_power_state)(struct clk_mgr *clk_mgr); 283 bool (*is_ips_supported)(struct clk_mgr *clk_mgr); 284 void (*set_idle_state)(struct clk_mgr *clk_mgr, bool allow_idle); 285 uint32_t (*get_idle_state)(struct clk_mgr *clk_mgr); 286 287 void (*init_clocks)(struct clk_mgr *clk_mgr); 288 289 void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass, 290 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); 291 292 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 293 void (*get_clock)(struct clk_mgr *clk_mgr, 294 struct dc_state *context, 295 enum dc_clock_type clock_type, 296 struct dc_clock_config *clock_cfg); 297 298 bool (*are_clock_states_equal) (struct dc_clocks *a, 299 struct dc_clocks *b); 300 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 301 302 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 303 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); 304 /* 305 * Send message to PMFW to set hard min memclk frequency 306 * When current_mode = false, set DPM0 307 * When current_mode = true, set required clock for current mode 308 */ 309 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); 310 311 /* Send message to PMFW to set hard max memclk frequency to highest DPM */ 312 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 313 314 /* Custom set a memclk freq range*/ 315 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 316 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 317 318 /* Get current memclk states from PMFW, update relevant structures */ 319 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 320 321 /* Get SMU present */ 322 bool (*is_smu_present)(struct clk_mgr *clk_mgr); 323 324 int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base); 325 326 }; 327 328 struct clk_mgr { 329 struct dc_context *ctx; 330 struct clk_mgr_funcs *funcs; 331 struct dc_clocks clks; 332 bool psr_allow_active_cache; 333 bool force_smu_not_present; 334 bool dc_mode_softmax_enabled; 335 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes 336 int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314 337 int dentist_vco_freq_khz; 338 struct clk_state_registers_and_bypass boot_snapshot; 339 struct clk_bw_params *bw_params; 340 struct pp_smu_wm_range_sets ranges; 341 }; 342 343 /* forward declarations */ 344 struct dccg; 345 346 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); 347 348 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); 349 350 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 351 352 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 353 354 #endif /* __DAL_CLK_MGR_H__ */ 355