1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/devfreq.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interconnect.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset-controller.h>
17 #include <linux/time.h>
18 #include <linux/unaligned.h>
19 #include <linux/units.h>
20
21 #include <soc/qcom/ice.h>
22
23 #include <ufs/ufshcd.h>
24 #include <ufs/ufshci.h>
25 #include <ufs/ufs_quirks.h>
26 #include <ufs/unipro.h>
27 #include "ufshcd-pltfrm.h"
28 #include "ufs-qcom.h"
29
30 #define MCQ_QCFGPTR_MASK GENMASK(7, 0)
31 #define MCQ_QCFGPTR_UNIT 0x200
32 #define MCQ_SQATTR_OFFSET(c) \
33 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
34 #define MCQ_QCFG_SIZE 0x40
35
36 /* De-emphasis for gear-5 */
37 #define DEEMPHASIS_3_5_dB 0x04
38 #define NO_DEEMPHASIS 0x0
39
40 enum {
41 TSTBUS_UAWM,
42 TSTBUS_UARM,
43 TSTBUS_TXUC,
44 TSTBUS_RXUC,
45 TSTBUS_DFC,
46 TSTBUS_TRLUT,
47 TSTBUS_TMRLUT,
48 TSTBUS_OCSC,
49 TSTBUS_UTP_HCI,
50 TSTBUS_COMBINED,
51 TSTBUS_WRAPPER,
52 TSTBUS_UNIPRO,
53 TSTBUS_MAX,
54 };
55
56 #define QCOM_UFS_MAX_GEAR 5
57 #define QCOM_UFS_MAX_LANE 2
58
59 enum {
60 MODE_MIN,
61 MODE_PWM,
62 MODE_HS_RA,
63 MODE_HS_RB,
64 MODE_MAX,
65 };
66
67 static const struct __ufs_qcom_bw_table {
68 u32 mem_bw;
69 u32 cfg_bw;
70 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
71 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */
72 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 },
73 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 },
74 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 },
75 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 },
76 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 },
77 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 },
78 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 },
79 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 },
80 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 },
81 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 },
82 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 },
83 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 },
84 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
85 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
86 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
87 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 },
88 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 },
89 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
90 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
91 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
92 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 },
93 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 },
94 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
95 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
96 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
97 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 },
98 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 },
99 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
100 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
101 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
102 [MODE_MAX][0][0] = { 7643136, 819200 },
103 };
104
105 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
106 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq);
107
rcdev_to_ufs_host(struct reset_controller_dev * rcd)108 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
109 {
110 return container_of(rcd, struct ufs_qcom_host, rcdev);
111 }
112
113 #ifdef CONFIG_SCSI_UFS_CRYPTO
114 /**
115 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration
116 *
117 * @host: pointer to qcom specific variant structure.
118 */
ufs_qcom_config_ice_allocator(struct ufs_qcom_host * host)119 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
120 {
121 struct ufs_hba *hba = host->hba;
122 static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 };
123 u32 config;
124
125 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) ||
126 !(host->hba->caps & UFSHCD_CAP_CRYPTO))
127 return;
128
129 config = get_unaligned_le32(val);
130
131 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG);
132 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE);
133 }
134
ufs_qcom_ice_enable(struct ufs_qcom_host * host)135 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
136 {
137 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
138 qcom_ice_enable(host->ice);
139 }
140
141 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */
142
ufs_qcom_ice_init(struct ufs_qcom_host * host)143 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
144 {
145 struct ufs_hba *hba = host->hba;
146 struct blk_crypto_profile *profile = &hba->crypto_profile;
147 struct device *dev = hba->dev;
148 struct qcom_ice *ice;
149 union ufs_crypto_capabilities caps;
150 union ufs_crypto_cap_entry cap;
151 int err;
152 int i;
153
154 ice = devm_of_qcom_ice_get(dev);
155 if (ice == ERR_PTR(-EOPNOTSUPP)) {
156 dev_warn(dev, "Disabling inline encryption support\n");
157 ice = NULL;
158 }
159
160 if (IS_ERR_OR_NULL(ice))
161 return PTR_ERR_OR_ZERO(ice);
162
163 host->ice = ice;
164
165 /* Initialize the blk_crypto_profile */
166
167 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
168
169 /* The number of keyslots supported is (CFGC+1) */
170 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1);
171 if (err)
172 return err;
173
174 profile->ll_ops = ufs_qcom_crypto_ops;
175 profile->max_dun_bytes_supported = 8;
176 profile->key_types_supported = BLK_CRYPTO_KEY_TYPE_RAW;
177 profile->dev = dev;
178
179 /*
180 * Currently this driver only supports AES-256-XTS. All known versions
181 * of ICE support it, but to be safe make sure it is really declared in
182 * the crypto capability registers. The crypto capability registers
183 * also give the supported data unit size(s).
184 */
185 for (i = 0; i < caps.num_crypto_cap; i++) {
186 cap.reg_val = cpu_to_le32(ufshcd_readl(hba,
187 REG_UFS_CRYPTOCAP +
188 i * sizeof(__le32)));
189 if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS &&
190 cap.key_size == UFS_CRYPTO_KEY_SIZE_256)
191 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |=
192 cap.sdus_mask * 512;
193 }
194
195 hba->caps |= UFSHCD_CAP_CRYPTO;
196 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE;
197 return 0;
198 }
199
ufs_qcom_ice_resume(struct ufs_qcom_host * host)200 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
201 {
202 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
203 return qcom_ice_resume(host->ice);
204
205 return 0;
206 }
207
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)208 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
209 {
210 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
211 return qcom_ice_suspend(host->ice);
212
213 return 0;
214 }
215
ufs_qcom_ice_keyslot_program(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)216 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile,
217 const struct blk_crypto_key *key,
218 unsigned int slot)
219 {
220 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
221 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
222 int err;
223
224 /* Only AES-256-XTS has been tested so far. */
225 if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS)
226 return -EOPNOTSUPP;
227
228 ufshcd_hold(hba);
229 err = qcom_ice_program_key(host->ice,
230 QCOM_ICE_CRYPTO_ALG_AES_XTS,
231 QCOM_ICE_CRYPTO_KEY_SIZE_256,
232 key->bytes,
233 key->crypto_cfg.data_unit_size / 512,
234 slot);
235 ufshcd_release(hba);
236 return err;
237 }
238
ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)239 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile,
240 const struct blk_crypto_key *key,
241 unsigned int slot)
242 {
243 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
244 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
245 int err;
246
247 ufshcd_hold(hba);
248 err = qcom_ice_evict_key(host->ice, slot);
249 ufshcd_release(hba);
250 return err;
251 }
252
253 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = {
254 .keyslot_program = ufs_qcom_ice_keyslot_program,
255 .keyslot_evict = ufs_qcom_ice_keyslot_evict,
256 };
257
258 #else
259
ufs_qcom_ice_enable(struct ufs_qcom_host * host)260 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
261 {
262 }
263
ufs_qcom_ice_init(struct ufs_qcom_host * host)264 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
265 {
266 return 0;
267 }
268
ufs_qcom_ice_resume(struct ufs_qcom_host * host)269 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
270 {
271 return 0;
272 }
273
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)274 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
275 {
276 return 0;
277 }
278
ufs_qcom_config_ice_allocator(struct ufs_qcom_host * host)279 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
280 {
281 }
282
283 #endif
284
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)285 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
286 {
287 if (!host->is_lane_clks_enabled)
288 return;
289
290 clk_bulk_disable_unprepare(host->num_clks, host->clks);
291
292 host->is_lane_clks_enabled = false;
293 }
294
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)295 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
296 {
297 int err;
298
299 err = clk_bulk_prepare_enable(host->num_clks, host->clks);
300 if (err)
301 return err;
302
303 host->is_lane_clks_enabled = true;
304
305 return 0;
306 }
307
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)308 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
309 {
310 int err;
311 struct device *dev = host->hba->dev;
312
313 if (has_acpi_companion(dev))
314 return 0;
315
316 err = devm_clk_bulk_get_all(dev, &host->clks);
317 if (err <= 0)
318 return err;
319
320 host->num_clks = err;
321
322 return 0;
323 }
324
ufs_qcom_check_hibern8(struct ufs_hba * hba)325 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
326 {
327 int err;
328 u32 tx_fsm_val;
329 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
330
331 do {
332 err = ufshcd_dme_get(hba,
333 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
334 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
335 &tx_fsm_val);
336 if (err || tx_fsm_val == TX_FSM_HIBERN8)
337 break;
338
339 /* sleep for max. 200us */
340 usleep_range(100, 200);
341 } while (time_before(jiffies, timeout));
342
343 /*
344 * we might have scheduled out for long during polling so
345 * check the state again.
346 */
347 if (time_after(jiffies, timeout))
348 err = ufshcd_dme_get(hba,
349 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
350 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
351 &tx_fsm_val);
352
353 if (err) {
354 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
355 __func__, err);
356 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
357 err = tx_fsm_val;
358 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
359 __func__, err);
360 }
361
362 return err;
363 }
364
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)365 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
366 {
367 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
368
369 if (host->hw_ver.major >= 0x05)
370 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
371 }
372
373 /*
374 * ufs_qcom_host_reset - reset host controller and PHY
375 */
ufs_qcom_host_reset(struct ufs_hba * hba)376 static int ufs_qcom_host_reset(struct ufs_hba *hba)
377 {
378 int ret;
379 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
380 bool reenable_intr;
381
382 if (!host->core_reset)
383 return 0;
384
385 reenable_intr = hba->is_irq_enabled;
386 ufshcd_disable_irq(hba);
387
388 ret = reset_control_assert(host->core_reset);
389 if (ret) {
390 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
391 __func__, ret);
392 return ret;
393 }
394
395 /*
396 * The hardware requirement for delay between assert/deassert
397 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
398 * ~125us (4/32768). To be on the safe side add 200us delay.
399 */
400 usleep_range(200, 210);
401
402 ret = reset_control_deassert(host->core_reset);
403 if (ret) {
404 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
405 __func__, ret);
406 return ret;
407 }
408
409 usleep_range(1000, 1100);
410
411 if (reenable_intr)
412 ufshcd_enable_irq(hba);
413
414 return 0;
415 }
416
ufs_qcom_get_hs_gear(struct ufs_hba * hba)417 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
418 {
419 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
420
421 if (host->hw_ver.major >= 0x4)
422 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
423
424 /* Default is HS-G3 */
425 return UFS_HS_G3;
426 }
427
ufs_qcom_power_up_sequence(struct ufs_hba * hba)428 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
429 {
430 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
431 struct ufs_host_params *host_params = &host->host_params;
432 struct phy *phy = host->generic_phy;
433 enum phy_mode mode;
434 int ret;
435
436 /*
437 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
438 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
439 * so that the subsequent power mode change shall stick to Rate-A.
440 */
441 if (host->hw_ver.major == 0x5) {
442 if (host->phy_gear == UFS_HS_G5)
443 host_params->hs_rate = PA_HS_MODE_A;
444 else
445 host_params->hs_rate = PA_HS_MODE_B;
446 }
447
448 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
449
450 /* Reset UFS Host Controller and PHY */
451 ret = ufs_qcom_host_reset(hba);
452 if (ret)
453 return ret;
454
455 if (phy->power_count) {
456 phy_power_off(phy);
457 phy_exit(phy);
458 }
459
460 /* phy initialization - calibrate the phy */
461 ret = phy_init(phy);
462 if (ret) {
463 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
464 __func__, ret);
465 return ret;
466 }
467
468 ret = phy_set_mode_ext(phy, mode, host->phy_gear);
469 if (ret)
470 goto out_disable_phy;
471
472 /* power on phy - start serdes and phy's power and clocks */
473 ret = phy_power_on(phy);
474 if (ret) {
475 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
476 __func__, ret);
477 goto out_disable_phy;
478 }
479
480 ufs_qcom_select_unipro_mode(host);
481
482 return 0;
483
484 out_disable_phy:
485 phy_exit(phy);
486
487 return ret;
488 }
489
490 /*
491 * The UTP controller has a number of internal clock gating cells (CGCs).
492 * Internal hardware sub-modules within the UTP controller control the CGCs.
493 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
494 * in a specific operation, UTP controller CGCs are by default disabled and
495 * this function enables them (after every UFS link startup) to save some power
496 * leakage.
497 */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)498 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
499 {
500 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
501 REG_UFS_CFG2);
502
503 /* Ensure that HW clock gating is enabled before next operations */
504 ufshcd_readl(hba, REG_UFS_CFG2);
505 }
506
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)507 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
508 enum ufs_notify_change_status status)
509 {
510 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
511 int err;
512
513 switch (status) {
514 case PRE_CHANGE:
515 err = ufs_qcom_power_up_sequence(hba);
516 if (err)
517 return err;
518
519 /*
520 * The PHY PLL output is the source of tx/rx lane symbol
521 * clocks, hence, enable the lane clocks only after PHY
522 * is initialized.
523 */
524 err = ufs_qcom_enable_lane_clks(host);
525 break;
526 case POST_CHANGE:
527 /* check if UFS PHY moved from DISABLED to HIBERN8 */
528 err = ufs_qcom_check_hibern8(hba);
529 ufs_qcom_enable_hw_clk_gating(hba);
530 ufs_qcom_ice_enable(host);
531 ufs_qcom_config_ice_allocator(host);
532 break;
533 default:
534 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
535 err = -EINVAL;
536 break;
537 }
538 return err;
539 }
540
541 /**
542 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
543 *
544 * @hba: host controller instance
545 * @is_pre_scale_up: flag to check if pre scale up condition.
546 * Return: zero for success and non-zero in case of a failure.
547 */
ufs_qcom_cfg_timers(struct ufs_hba * hba,bool is_pre_scale_up)548 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up)
549 {
550 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
551 struct ufs_clk_info *clki;
552 unsigned long core_clk_rate = 0;
553 u32 core_clk_cycles_per_us;
554
555 /*
556 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
557 * Aggregation logic.
558 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
559 * controller V4.0.0 onwards.
560 */
561 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
562 return 0;
563
564 list_for_each_entry(clki, &hba->clk_list_head, list) {
565 if (!strcmp(clki->name, "core_clk")) {
566 if (is_pre_scale_up)
567 core_clk_rate = clki->max_freq;
568 else
569 core_clk_rate = clk_get_rate(clki->clk);
570 break;
571 }
572
573 }
574
575 /* If frequency is smaller than 1MHz, set to 1MHz */
576 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
577 core_clk_rate = DEFAULT_CLK_RATE_HZ;
578
579 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
580 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
581 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
582 /*
583 * make sure above write gets applied before we return from
584 * this function.
585 */
586 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
587 }
588
589 return 0;
590 }
591
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)592 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
593 enum ufs_notify_change_status status)
594 {
595 int err = 0;
596
597 switch (status) {
598 case PRE_CHANGE:
599 if (ufs_qcom_cfg_timers(hba, false)) {
600 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
601 __func__);
602 return -EINVAL;
603 }
604
605 err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX);
606 if (err)
607 dev_err(hba->dev, "cfg core clk ctrl failed\n");
608 /*
609 * Some UFS devices (and may be host) have issues if LCC is
610 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
611 * before link startup which will make sure that both host
612 * and device TX LCC are disabled once link startup is
613 * completed.
614 */
615 err = ufshcd_disable_host_tx_lcc(hba);
616
617 break;
618 default:
619 break;
620 }
621
622 return err;
623 }
624
ufs_qcom_device_reset_ctrl(struct ufs_hba * hba,bool asserted)625 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
626 {
627 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
628
629 /* reset gpio is optional */
630 if (!host->device_reset)
631 return;
632
633 gpiod_set_value_cansleep(host->device_reset, asserted);
634 }
635
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)636 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
637 enum ufs_notify_change_status status)
638 {
639 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
640 struct phy *phy = host->generic_phy;
641
642 if (status == PRE_CHANGE)
643 return 0;
644
645 if (ufs_qcom_is_link_off(hba)) {
646 /*
647 * Disable the tx/rx lane symbol clocks before PHY is
648 * powered down as the PLL source should be disabled
649 * after downstream clocks are disabled.
650 */
651 ufs_qcom_disable_lane_clks(host);
652 phy_power_off(phy);
653
654 /* reset the connected UFS device during power down */
655 ufs_qcom_device_reset_ctrl(hba, true);
656
657 } else if (!ufs_qcom_is_link_active(hba)) {
658 ufs_qcom_disable_lane_clks(host);
659 }
660
661 return ufs_qcom_ice_suspend(host);
662 }
663
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)664 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
665 {
666 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
667 struct phy *phy = host->generic_phy;
668 int err;
669
670 if (ufs_qcom_is_link_off(hba)) {
671 err = phy_power_on(phy);
672 if (err) {
673 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
674 __func__, err);
675 return err;
676 }
677
678 err = ufs_qcom_enable_lane_clks(host);
679 if (err)
680 return err;
681
682 } else if (!ufs_qcom_is_link_active(hba)) {
683 err = ufs_qcom_enable_lane_clks(host);
684 if (err)
685 return err;
686 }
687
688 return ufs_qcom_ice_resume(host);
689 }
690
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)691 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
692 {
693 if (host->dev_ref_clk_ctrl_mmio &&
694 (enable ^ host->is_dev_ref_clk_enabled)) {
695 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
696
697 if (enable)
698 temp |= host->dev_ref_clk_en_mask;
699 else
700 temp &= ~host->dev_ref_clk_en_mask;
701
702 /*
703 * If we are here to disable this clock it might be immediately
704 * after entering into hibern8 in which case we need to make
705 * sure that device ref_clk is active for specific time after
706 * hibern8 enter.
707 */
708 if (!enable) {
709 unsigned long gating_wait;
710
711 gating_wait = host->hba->dev_info.clk_gating_wait_us;
712 if (!gating_wait) {
713 udelay(1);
714 } else {
715 /*
716 * bRefClkGatingWaitTime defines the minimum
717 * time for which the reference clock is
718 * required by device during transition from
719 * HS-MODE to LS-MODE or HIBERN8 state. Give it
720 * more delay to be on the safe side.
721 */
722 gating_wait += 10;
723 usleep_range(gating_wait, gating_wait + 10);
724 }
725 }
726
727 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
728
729 /*
730 * Make sure the write to ref_clk reaches the destination and
731 * not stored in a Write Buffer (WB).
732 */
733 readl(host->dev_ref_clk_ctrl_mmio);
734
735 /*
736 * If we call hibern8 exit after this, we need to make sure that
737 * device ref_clk is stable for at least 1us before the hibern8
738 * exit command.
739 */
740 if (enable)
741 udelay(1);
742
743 host->is_dev_ref_clk_enabled = enable;
744 }
745 }
746
ufs_qcom_icc_set_bw(struct ufs_qcom_host * host,u32 mem_bw,u32 cfg_bw)747 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
748 {
749 struct device *dev = host->hba->dev;
750 int ret;
751
752 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
753 if (ret < 0) {
754 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
755 return ret;
756 }
757
758 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
759 if (ret < 0) {
760 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
761 return ret;
762 }
763
764 return 0;
765 }
766
ufs_qcom_get_bw_table(struct ufs_qcom_host * host)767 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
768 {
769 struct ufs_pa_layer_attr *p = &host->dev_req_params;
770 int gear = max_t(u32, p->gear_rx, p->gear_tx);
771 int lane = max_t(u32, p->lane_rx, p->lane_tx);
772
773 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR,
774 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n",
775 gear, QCOM_UFS_MAX_GEAR))
776 gear = QCOM_UFS_MAX_GEAR;
777
778 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE,
779 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n",
780 lane, QCOM_UFS_MAX_LANE))
781 lane = QCOM_UFS_MAX_LANE;
782
783 if (ufshcd_is_hs_mode(p)) {
784 if (p->hs_rate == PA_HS_MODE_B)
785 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
786 else
787 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
788 } else {
789 return ufs_qcom_bw_table[MODE_PWM][gear][lane];
790 }
791 }
792
ufs_qcom_icc_update_bw(struct ufs_qcom_host * host)793 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
794 {
795 struct __ufs_qcom_bw_table bw_table;
796
797 bw_table = ufs_qcom_get_bw_table(host);
798
799 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
800 }
801
ufs_qcom_set_tx_hs_equalizer(struct ufs_hba * hba,u32 gear,u32 tx_lanes)802 static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_lanes)
803 {
804 u32 equalizer_val;
805 int ret, i;
806
807 /* Determine the equalizer value based on the gear */
808 equalizer_val = (gear == 5) ? DEEMPHASIS_3_5_dB : NO_DEEMPHASIS;
809
810 for (i = 0; i < tx_lanes; i++) {
811 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i),
812 equalizer_val);
813 if (ret)
814 dev_err(hba->dev, "%s: failed equalizer lane %d\n",
815 __func__, i);
816 }
817 }
818
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,const struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)819 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
820 enum ufs_notify_change_status status,
821 const struct ufs_pa_layer_attr *dev_max_params,
822 struct ufs_pa_layer_attr *dev_req_params)
823 {
824 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
825 struct ufs_host_params *host_params = &host->host_params;
826 int ret = 0;
827
828 if (!dev_req_params) {
829 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
830 return -EINVAL;
831 }
832
833 switch (status) {
834 case PRE_CHANGE:
835 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params);
836 if (ret) {
837 dev_err(hba->dev, "%s: failed to determine capabilities\n",
838 __func__);
839 return ret;
840 }
841
842 /*
843 * During UFS driver probe, always update the PHY gear to match the negotiated
844 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
845 * the second init can program the optimal PHY settings. This allows one to start
846 * the first init with either the minimum or the maximum support gear.
847 */
848 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
849 /*
850 * Skip REINIT if the negotiated gear matches with the
851 * initial phy_gear. Otherwise, update the phy_gear to
852 * program the optimal gear setting during REINIT.
853 */
854 if (host->phy_gear == dev_req_params->gear_tx)
855 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
856 else
857 host->phy_gear = dev_req_params->gear_tx;
858 }
859
860 /* enable the device ref clock before changing to HS mode */
861 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
862 ufshcd_is_hs_mode(dev_req_params))
863 ufs_qcom_dev_ref_clk_ctrl(host, true);
864
865 if (host->hw_ver.major >= 0x4) {
866 ufshcd_dme_configure_adapt(hba,
867 dev_req_params->gear_tx,
868 PA_INITIAL_ADAPT);
869 }
870
871 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING)
872 ufs_qcom_set_tx_hs_equalizer(hba,
873 dev_req_params->gear_tx, dev_req_params->lane_tx);
874
875 break;
876 case POST_CHANGE:
877 if (ufs_qcom_cfg_timers(hba, false)) {
878 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
879 __func__);
880 /*
881 * we return error code at the end of the routine,
882 * but continue to configure UFS_PHY_TX_LANE_ENABLE
883 * and bus voting as usual
884 */
885 ret = -EINVAL;
886 }
887
888 /* cache the power mode parameters to use internally */
889 memcpy(&host->dev_req_params,
890 dev_req_params, sizeof(*dev_req_params));
891
892 ufs_qcom_icc_update_bw(host);
893
894 /* disable the device ref clock if entered PWM mode */
895 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
896 !ufshcd_is_hs_mode(dev_req_params))
897 ufs_qcom_dev_ref_clk_ctrl(host, false);
898 break;
899 default:
900 ret = -EINVAL;
901 break;
902 }
903
904 return ret;
905 }
906
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)907 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
908 {
909 int err;
910 u32 pa_vs_config_reg1;
911
912 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
913 &pa_vs_config_reg1);
914 if (err)
915 return err;
916
917 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
918 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
919 (pa_vs_config_reg1 | (1 << 12)));
920 }
921
ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba * hba)922 static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba)
923 {
924 int err;
925
926 err = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TX_HSG1_SYNC_LENGTH),
927 PA_TX_HSG1_SYNC_LENGTH_VAL);
928 if (err)
929 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err);
930 }
931
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)932 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
933 {
934 int err = 0;
935
936 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
937 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
938
939 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH)
940 ufs_qcom_override_pa_tx_hsg1_sync_len(hba);
941
942 return err;
943 }
944
945 /* UFS device-specific quirks */
946 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = {
947 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
948 .model = UFS_ANY_MODEL,
949 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
950 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
951 .model = UFS_ANY_MODEL,
952 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM },
953 { .wmanufacturerid = UFS_VENDOR_WDC,
954 .model = UFS_ANY_MODEL,
955 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE },
956 { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
957 .model = UFS_ANY_MODEL,
958 .quirk = UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH |
959 UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING },
960 {}
961 };
962
ufs_qcom_fixup_dev_quirks(struct ufs_hba * hba)963 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba)
964 {
965 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups);
966 }
967
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)968 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
969 {
970 return ufshci_version(2, 0);
971 }
972
973 /**
974 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
975 * @hba: host controller instance
976 *
977 * QCOM UFS host controller might have some non standard behaviours (quirks)
978 * than what is specified by UFSHCI specification. Advertise all such
979 * quirks to standard UFS host controller driver so standard takes them into
980 * account.
981 */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)982 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
983 {
984 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
985 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
986
987 if (host->hw_ver.major == 0x2)
988 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
989
990 if (host->hw_ver.major > 0x3)
991 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
992
993 if (drvdata && drvdata->quirks)
994 hba->quirks |= drvdata->quirks;
995 }
996
ufs_qcom_set_phy_gear(struct ufs_qcom_host * host)997 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
998 {
999 struct ufs_host_params *host_params = &host->host_params;
1000 u32 val, dev_major;
1001
1002 /*
1003 * Default to powering up the PHY to the max gear possible, which is
1004 * backwards compatible with lower gears but not optimal from
1005 * a power usage point of view. After device negotiation, if the
1006 * gear is lower a reinit will be performed to program the PHY
1007 * to the ideal gear for this combo of controller and device.
1008 */
1009 host->phy_gear = host_params->hs_tx_gear;
1010
1011 if (host->hw_ver.major < 0x4) {
1012 /*
1013 * These controllers only have one PHY init sequence,
1014 * let's power up the PHY using that (the minimum supported
1015 * gear, UFS_HS_G2).
1016 */
1017 host->phy_gear = UFS_HS_G2;
1018 } else if (host->hw_ver.major >= 0x5) {
1019 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
1020 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
1021
1022 /*
1023 * Since the UFS device version is populated, let's remove the
1024 * REINIT quirk as the negotiated gear won't change during boot.
1025 * So there is no need to do reinit.
1026 */
1027 if (dev_major != 0x0)
1028 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
1029
1030 /*
1031 * For UFS 3.1 device and older, power up the PHY using HS-G4
1032 * PHY gear to save power.
1033 */
1034 if (dev_major > 0x0 && dev_major < 0x4)
1035 host->phy_gear = UFS_HS_G4;
1036 }
1037 }
1038
ufs_qcom_set_host_params(struct ufs_hba * hba)1039 static void ufs_qcom_set_host_params(struct ufs_hba *hba)
1040 {
1041 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1042 struct ufs_host_params *host_params = &host->host_params;
1043
1044 ufshcd_init_host_params(host_params);
1045
1046 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
1047 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
1048 }
1049
ufs_qcom_set_host_caps(struct ufs_hba * hba)1050 static void ufs_qcom_set_host_caps(struct ufs_hba *hba)
1051 {
1052 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1053
1054 if (host->hw_ver.major >= 0x5)
1055 host->caps |= UFS_QCOM_CAP_ICE_CONFIG;
1056 }
1057
ufs_qcom_set_caps(struct ufs_hba * hba)1058 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1059 {
1060 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1061 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
1062 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1063 hba->caps |= UFSHCD_CAP_WB_EN;
1064 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
1065 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
1066
1067 ufs_qcom_set_host_caps(hba);
1068 }
1069
1070 /**
1071 * ufs_qcom_setup_clocks - enables/disable clocks
1072 * @hba: host controller instance
1073 * @on: If true, enable clocks else disable them.
1074 * @status: PRE_CHANGE or POST_CHANGE notify
1075 *
1076 * Return: 0 on success, non-zero on failure.
1077 */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)1078 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1079 enum ufs_notify_change_status status)
1080 {
1081 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1082
1083 /*
1084 * In case ufs_qcom_init() is not yet done, simply ignore.
1085 * This ufs_qcom_setup_clocks() shall be called from
1086 * ufs_qcom_init() after init is done.
1087 */
1088 if (!host)
1089 return 0;
1090
1091 switch (status) {
1092 case PRE_CHANGE:
1093 if (on) {
1094 ufs_qcom_icc_update_bw(host);
1095 } else {
1096 if (!ufs_qcom_is_link_active(hba)) {
1097 /* disable device ref_clk */
1098 ufs_qcom_dev_ref_clk_ctrl(host, false);
1099 }
1100 }
1101 break;
1102 case POST_CHANGE:
1103 if (on) {
1104 /* enable the device ref clock for HS mode*/
1105 if (ufshcd_is_hs_mode(&hba->pwr_info))
1106 ufs_qcom_dev_ref_clk_ctrl(host, true);
1107 } else {
1108 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
1109 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
1110 }
1111 break;
1112 }
1113
1114 return 0;
1115 }
1116
1117 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)1118 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1119 {
1120 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1121
1122 ufs_qcom_assert_reset(host->hba);
1123 /* provide 1ms delay to let the reset pulse propagate. */
1124 usleep_range(1000, 1100);
1125 return 0;
1126 }
1127
1128 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)1129 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1130 {
1131 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1132
1133 ufs_qcom_deassert_reset(host->hba);
1134
1135 /*
1136 * after reset deassertion, phy will need all ref clocks,
1137 * voltage, current to settle down before starting serdes.
1138 */
1139 usleep_range(1000, 1100);
1140 return 0;
1141 }
1142
1143 static const struct reset_control_ops ufs_qcom_reset_ops = {
1144 .assert = ufs_qcom_reset_assert,
1145 .deassert = ufs_qcom_reset_deassert,
1146 };
1147
ufs_qcom_icc_init(struct ufs_qcom_host * host)1148 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1149 {
1150 struct device *dev = host->hba->dev;
1151 int ret;
1152
1153 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1154 if (IS_ERR(host->icc_ddr))
1155 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1156 "failed to acquire interconnect path\n");
1157
1158 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1159 if (IS_ERR(host->icc_cpu))
1160 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1161 "failed to acquire interconnect path\n");
1162
1163 /*
1164 * Set Maximum bandwidth vote before initializing the UFS controller and
1165 * device. Ideally, a minimal interconnect vote would suffice for the
1166 * initialization, but a max vote would allow faster initialization.
1167 */
1168 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1169 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1170 if (ret < 0)
1171 return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1172
1173 return 0;
1174 }
1175
1176 /**
1177 * ufs_qcom_init - bind phy with controller
1178 * @hba: host controller instance
1179 *
1180 * Binds PHY with controller and powers up PHY enabling clocks
1181 * and regulators.
1182 *
1183 * Return: -EPROBE_DEFER if binding fails, returns negative error
1184 * on phy power up failure and returns zero on success.
1185 */
ufs_qcom_init(struct ufs_hba * hba)1186 static int ufs_qcom_init(struct ufs_hba *hba)
1187 {
1188 int err;
1189 struct device *dev = hba->dev;
1190 struct ufs_qcom_host *host;
1191 struct ufs_clk_info *clki;
1192 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
1193
1194 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1195 if (!host)
1196 return -ENOMEM;
1197
1198 /* Make a two way bind between the qcom host and the hba */
1199 host->hba = hba;
1200 ufshcd_set_variant(hba, host);
1201
1202 /* Setup the optional reset control of HCI */
1203 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1204 if (IS_ERR(host->core_reset)) {
1205 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1206 "Failed to get reset control\n");
1207 goto out_variant_clear;
1208 }
1209
1210 /* Fire up the reset controller. Failure here is non-fatal. */
1211 host->rcdev.of_node = dev->of_node;
1212 host->rcdev.ops = &ufs_qcom_reset_ops;
1213 host->rcdev.owner = dev->driver->owner;
1214 host->rcdev.nr_resets = 1;
1215 err = devm_reset_controller_register(dev, &host->rcdev);
1216 if (err)
1217 dev_warn(dev, "Failed to register reset controller\n");
1218
1219 if (!has_acpi_companion(dev)) {
1220 host->generic_phy = devm_phy_get(dev, "ufsphy");
1221 if (IS_ERR(host->generic_phy)) {
1222 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1223 goto out_variant_clear;
1224 }
1225 }
1226
1227 err = ufs_qcom_icc_init(host);
1228 if (err)
1229 goto out_variant_clear;
1230
1231 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1232 GPIOD_OUT_HIGH);
1233 if (IS_ERR(host->device_reset)) {
1234 err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1235 "Failed to acquire device reset gpio\n");
1236 goto out_variant_clear;
1237 }
1238
1239 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1240 &host->hw_ver.minor, &host->hw_ver.step);
1241
1242 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1243 host->dev_ref_clk_en_mask = BIT(26);
1244
1245 list_for_each_entry(clki, &hba->clk_list_head, list) {
1246 if (!strcmp(clki->name, "core_clk_unipro"))
1247 clki->keep_link_active = true;
1248 }
1249
1250 err = ufs_qcom_init_lane_clks(host);
1251 if (err)
1252 goto out_variant_clear;
1253
1254 ufs_qcom_set_caps(hba);
1255 ufs_qcom_advertise_quirks(hba);
1256 ufs_qcom_set_host_params(hba);
1257 ufs_qcom_set_phy_gear(host);
1258
1259 err = ufs_qcom_ice_init(host);
1260 if (err)
1261 goto out_variant_clear;
1262
1263 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1264
1265 ufs_qcom_get_default_testbus_cfg(host);
1266 err = ufs_qcom_testbus_config(host);
1267 if (err)
1268 /* Failure is non-fatal */
1269 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1270 __func__, err);
1271
1272 if (drvdata && drvdata->no_phy_retention)
1273 hba->spm_lvl = UFS_PM_LVL_5;
1274
1275 return 0;
1276
1277 out_variant_clear:
1278 ufshcd_set_variant(hba, NULL);
1279
1280 return err;
1281 }
1282
ufs_qcom_exit(struct ufs_hba * hba)1283 static void ufs_qcom_exit(struct ufs_hba *hba)
1284 {
1285 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1286
1287 ufs_qcom_disable_lane_clks(host);
1288 phy_power_off(host->generic_phy);
1289 phy_exit(host->generic_phy);
1290 }
1291
1292 /**
1293 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1294 *
1295 * @hba: host controller instance
1296 * @cycles_in_1us: No of cycles in 1us to be configured
1297 *
1298 * Returns error if dme get/set configuration for 40ns fails
1299 * and returns zero on success.
1300 */
ufs_qcom_set_clk_40ns_cycles(struct ufs_hba * hba,u32 cycles_in_1us)1301 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
1302 u32 cycles_in_1us)
1303 {
1304 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1305 u32 cycles_in_40ns;
1306 u32 reg;
1307 int err;
1308
1309 /*
1310 * UFS host controller V4.0.0 onwards needs to program
1311 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
1312 * frequency of unipro core clk of UFS host controller.
1313 */
1314 if (host->hw_ver.major < 4)
1315 return 0;
1316
1317 /*
1318 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
1319 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
1320 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
1321 * specification expect to be 16. Hence use exact hardware spec
1322 * mandated value for cycles_in_40ns instead of calculating using
1323 * generic formulae.
1324 */
1325 switch (cycles_in_1us) {
1326 case UNIPRO_CORE_CLK_FREQ_403_MHZ:
1327 cycles_in_40ns = 16;
1328 break;
1329 case UNIPRO_CORE_CLK_FREQ_300_MHZ:
1330 cycles_in_40ns = 12;
1331 break;
1332 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
1333 cycles_in_40ns = 8;
1334 break;
1335 case UNIPRO_CORE_CLK_FREQ_150_MHZ:
1336 cycles_in_40ns = 6;
1337 break;
1338 case UNIPRO_CORE_CLK_FREQ_100_MHZ:
1339 cycles_in_40ns = 4;
1340 break;
1341 case UNIPRO_CORE_CLK_FREQ_75_MHZ:
1342 cycles_in_40ns = 3;
1343 break;
1344 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
1345 cycles_in_40ns = 2;
1346 break;
1347 default:
1348 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
1349 cycles_in_1us);
1350 return -EINVAL;
1351 }
1352
1353 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®);
1354 if (err)
1355 return err;
1356
1357 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
1358 reg |= cycles_in_40ns;
1359
1360 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
1361 }
1362
ufs_qcom_set_core_clk_ctrl(struct ufs_hba * hba,unsigned long freq)1363 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq)
1364 {
1365 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1366 struct list_head *head = &hba->clk_list_head;
1367 struct ufs_clk_info *clki;
1368 u32 cycles_in_1us = 0;
1369 u32 core_clk_ctrl_reg;
1370 int err;
1371
1372 list_for_each_entry(clki, head, list) {
1373 if (!IS_ERR_OR_NULL(clki->clk) &&
1374 !strcmp(clki->name, "core_clk_unipro")) {
1375 if (!clki->max_freq)
1376 cycles_in_1us = 150; /* default for backwards compatibility */
1377 else if (freq == ULONG_MAX)
1378 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
1379 else
1380 cycles_in_1us = ceil(freq, HZ_PER_MHZ);
1381
1382 break;
1383 }
1384 }
1385
1386 err = ufshcd_dme_get(hba,
1387 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1388 &core_clk_ctrl_reg);
1389 if (err)
1390 return err;
1391
1392 /* Bit mask is different for UFS host controller V4.0.0 onwards */
1393 if (host->hw_ver.major >= 4) {
1394 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
1395 return -ERANGE;
1396 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1397 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1398 } else {
1399 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
1400 return -ERANGE;
1401 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1402 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1403 }
1404
1405 /* Clear CORE_CLK_DIV_EN */
1406 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1407
1408 err = ufshcd_dme_set(hba,
1409 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1410 core_clk_ctrl_reg);
1411 if (err)
1412 return err;
1413
1414 /* Configure unipro core clk 40ns attribute */
1415 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
1416 }
1417
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba,unsigned long freq)1418 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq)
1419 {
1420 int ret;
1421
1422 ret = ufs_qcom_cfg_timers(hba, true);
1423 if (ret) {
1424 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
1425 return ret;
1426 }
1427 /* set unipro core clock attributes and clear clock divider */
1428 return ufs_qcom_set_core_clk_ctrl(hba, freq);
1429 }
1430
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1431 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1432 {
1433 return 0;
1434 }
1435
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1436 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1437 {
1438 int err;
1439 u32 core_clk_ctrl_reg;
1440
1441 err = ufshcd_dme_get(hba,
1442 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1443 &core_clk_ctrl_reg);
1444
1445 /* make sure CORE_CLK_DIV_EN is cleared */
1446 if (!err &&
1447 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1448 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1449 err = ufshcd_dme_set(hba,
1450 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1451 core_clk_ctrl_reg);
1452 }
1453
1454 return err;
1455 }
1456
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba,unsigned long freq)1457 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq)
1458 {
1459 /* set unipro core clock attributes and clear clock divider */
1460 return ufs_qcom_set_core_clk_ctrl(hba, freq);
1461 }
1462
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,unsigned long target_freq,enum ufs_notify_change_status status)1463 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
1464 unsigned long target_freq,
1465 enum ufs_notify_change_status status)
1466 {
1467 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1468 int err;
1469
1470 /* check the host controller state before sending hibern8 cmd */
1471 if (!ufshcd_is_hba_active(hba))
1472 return 0;
1473
1474 if (status == PRE_CHANGE) {
1475 err = ufshcd_uic_hibern8_enter(hba);
1476 if (err)
1477 return err;
1478 if (scale_up)
1479 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq);
1480 else
1481 err = ufs_qcom_clk_scale_down_pre_change(hba);
1482
1483 if (err) {
1484 ufshcd_uic_hibern8_exit(hba);
1485 return err;
1486 }
1487 } else {
1488 if (scale_up)
1489 err = ufs_qcom_clk_scale_up_post_change(hba);
1490 else
1491 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq);
1492
1493
1494 if (err) {
1495 ufshcd_uic_hibern8_exit(hba);
1496 return err;
1497 }
1498
1499 ufs_qcom_icc_update_bw(host);
1500 ufshcd_uic_hibern8_exit(hba);
1501 }
1502
1503 return 0;
1504 }
1505
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1506 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1507 {
1508 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1509 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1510 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1511 }
1512
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1513 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1514 {
1515 /* provide a legal default configuration */
1516 host->testbus.select_major = TSTBUS_UNIPRO;
1517 host->testbus.select_minor = 37;
1518 }
1519
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1520 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1521 {
1522 if (host->testbus.select_major >= TSTBUS_MAX) {
1523 dev_err(host->hba->dev,
1524 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1525 __func__, host->testbus.select_major);
1526 return false;
1527 }
1528
1529 return true;
1530 }
1531
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1532 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1533 {
1534 int reg;
1535 int offset;
1536 u32 mask = TEST_BUS_SUB_SEL_MASK;
1537
1538 if (!host)
1539 return -EINVAL;
1540
1541 if (!ufs_qcom_testbus_cfg_is_ok(host))
1542 return -EPERM;
1543
1544 switch (host->testbus.select_major) {
1545 case TSTBUS_UAWM:
1546 reg = UFS_TEST_BUS_CTRL_0;
1547 offset = 24;
1548 break;
1549 case TSTBUS_UARM:
1550 reg = UFS_TEST_BUS_CTRL_0;
1551 offset = 16;
1552 break;
1553 case TSTBUS_TXUC:
1554 reg = UFS_TEST_BUS_CTRL_0;
1555 offset = 8;
1556 break;
1557 case TSTBUS_RXUC:
1558 reg = UFS_TEST_BUS_CTRL_0;
1559 offset = 0;
1560 break;
1561 case TSTBUS_DFC:
1562 reg = UFS_TEST_BUS_CTRL_1;
1563 offset = 24;
1564 break;
1565 case TSTBUS_TRLUT:
1566 reg = UFS_TEST_BUS_CTRL_1;
1567 offset = 16;
1568 break;
1569 case TSTBUS_TMRLUT:
1570 reg = UFS_TEST_BUS_CTRL_1;
1571 offset = 8;
1572 break;
1573 case TSTBUS_OCSC:
1574 reg = UFS_TEST_BUS_CTRL_1;
1575 offset = 0;
1576 break;
1577 case TSTBUS_WRAPPER:
1578 reg = UFS_TEST_BUS_CTRL_2;
1579 offset = 16;
1580 break;
1581 case TSTBUS_COMBINED:
1582 reg = UFS_TEST_BUS_CTRL_2;
1583 offset = 8;
1584 break;
1585 case TSTBUS_UTP_HCI:
1586 reg = UFS_TEST_BUS_CTRL_2;
1587 offset = 0;
1588 break;
1589 case TSTBUS_UNIPRO:
1590 reg = UFS_UNIPRO_CFG;
1591 offset = 20;
1592 mask = 0xFFF;
1593 break;
1594 /*
1595 * No need for a default case, since
1596 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1597 * is legal
1598 */
1599 }
1600 mask <<= offset;
1601 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1602 (u32)host->testbus.select_major << 19,
1603 REG_UFS_CFG1);
1604 ufshcd_rmwl(host->hba, mask,
1605 (u32)host->testbus.select_minor << offset,
1606 reg);
1607 ufs_qcom_enable_test_bus(host);
1608
1609 return 0;
1610 }
1611
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1612 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1613 {
1614 u32 reg;
1615 struct ufs_qcom_host *host;
1616
1617 host = ufshcd_get_variant(hba);
1618
1619 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1620 "HCI Vendor Specific Registers ");
1621
1622 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1623 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1624
1625 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1626 reg |= UTP_DBG_RAMS_EN;
1627 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1628
1629 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1630 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1631
1632 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1633 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1634
1635 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1636 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1637
1638 /* clear bit 17 - UTP_DBG_RAMS_EN */
1639 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1640
1641 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1642 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1643
1644 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1645 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1646
1647 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1648 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1649
1650 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1651 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1652
1653 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1654 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1655
1656 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1657 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1658
1659 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1660 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1661 }
1662
1663 /**
1664 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1665 * @hba: per-adapter instance
1666 *
1667 * Toggles the (optional) reset line to reset the attached device.
1668 */
ufs_qcom_device_reset(struct ufs_hba * hba)1669 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1670 {
1671 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1672
1673 /* reset gpio is optional */
1674 if (!host->device_reset)
1675 return -EOPNOTSUPP;
1676
1677 /*
1678 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1679 * be on the safe side.
1680 */
1681 ufs_qcom_device_reset_ctrl(hba, true);
1682 usleep_range(10, 15);
1683
1684 ufs_qcom_device_reset_ctrl(hba, false);
1685 usleep_range(10, 15);
1686
1687 return 0;
1688 }
1689
1690 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * d)1691 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1692 struct devfreq_dev_profile *p,
1693 struct devfreq_simple_ondemand_data *d)
1694 {
1695 p->polling_ms = 60;
1696 p->timer = DEVFREQ_TIMER_DELAYED;
1697 d->upthreshold = 70;
1698 d->downdifferential = 5;
1699
1700 hba->clk_scaling.suspend_on_no_request = true;
1701 }
1702 #else
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * data)1703 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1704 struct devfreq_dev_profile *p,
1705 struct devfreq_simple_ondemand_data *data)
1706 {
1707 }
1708 #endif
1709
1710 /* Resources */
1711 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1712 {.name = "ufs_mem",},
1713 {.name = "mcq",},
1714 /* Submission Queue DAO */
1715 {.name = "mcq_sqd",},
1716 /* Submission Queue Interrupt Status */
1717 {.name = "mcq_sqis",},
1718 /* Completion Queue DAO */
1719 {.name = "mcq_cqd",},
1720 /* Completion Queue Interrupt Status */
1721 {.name = "mcq_cqis",},
1722 /* MCQ vendor specific */
1723 {.name = "mcq_vs",},
1724 };
1725
ufs_qcom_mcq_config_resource(struct ufs_hba * hba)1726 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1727 {
1728 struct platform_device *pdev = to_platform_device(hba->dev);
1729 struct ufshcd_res_info *res;
1730 struct resource *res_mem, *res_mcq;
1731 int i, ret;
1732
1733 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1734
1735 for (i = 0; i < RES_MAX; i++) {
1736 res = &hba->res[i];
1737 res->resource = platform_get_resource_byname(pdev,
1738 IORESOURCE_MEM,
1739 res->name);
1740 if (!res->resource) {
1741 dev_info(hba->dev, "Resource %s not provided\n", res->name);
1742 if (i == RES_UFS)
1743 return -ENODEV;
1744 continue;
1745 } else if (i == RES_UFS) {
1746 res_mem = res->resource;
1747 res->base = hba->mmio_base;
1748 continue;
1749 }
1750
1751 res->base = devm_ioremap_resource(hba->dev, res->resource);
1752 if (IS_ERR(res->base)) {
1753 dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1754 res->name, (int)PTR_ERR(res->base));
1755 ret = PTR_ERR(res->base);
1756 res->base = NULL;
1757 return ret;
1758 }
1759 }
1760
1761 /* MCQ resource provided in DT */
1762 res = &hba->res[RES_MCQ];
1763 /* Bail if MCQ resource is provided */
1764 if (res->base)
1765 goto out;
1766
1767 /* Explicitly allocate MCQ resource from ufs_mem */
1768 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
1769 if (!res_mcq)
1770 return -ENOMEM;
1771
1772 res_mcq->start = res_mem->start +
1773 MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
1774 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
1775 res_mcq->flags = res_mem->flags;
1776 res_mcq->name = "mcq";
1777
1778 ret = insert_resource(&iomem_resource, res_mcq);
1779 if (ret) {
1780 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1781 ret);
1782 return ret;
1783 }
1784
1785 res->base = devm_ioremap_resource(hba->dev, res_mcq);
1786 if (IS_ERR(res->base)) {
1787 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1788 (int)PTR_ERR(res->base));
1789 ret = PTR_ERR(res->base);
1790 goto ioremap_err;
1791 }
1792
1793 out:
1794 hba->mcq_base = res->base;
1795 return 0;
1796 ioremap_err:
1797 res->base = NULL;
1798 remove_resource(res_mcq);
1799 return ret;
1800 }
1801
ufs_qcom_op_runtime_config(struct ufs_hba * hba)1802 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1803 {
1804 struct ufshcd_res_info *mem_res, *sqdao_res;
1805 struct ufshcd_mcq_opr_info_t *opr;
1806 int i;
1807
1808 mem_res = &hba->res[RES_UFS];
1809 sqdao_res = &hba->res[RES_MCQ_SQD];
1810
1811 if (!mem_res->base || !sqdao_res->base)
1812 return -EINVAL;
1813
1814 for (i = 0; i < OPR_MAX; i++) {
1815 opr = &hba->mcq_opr[i];
1816 opr->offset = sqdao_res->resource->start -
1817 mem_res->resource->start + 0x40 * i;
1818 opr->stride = 0x100;
1819 opr->base = sqdao_res->base + 0x40 * i;
1820 }
1821
1822 return 0;
1823 }
1824
ufs_qcom_get_hba_mac(struct ufs_hba * hba)1825 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
1826 {
1827 /* Qualcomm HC supports up to 64 */
1828 return MAX_SUPP_MAC;
1829 }
1830
ufs_qcom_get_outstanding_cqs(struct ufs_hba * hba,unsigned long * ocqs)1831 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
1832 unsigned long *ocqs)
1833 {
1834 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
1835
1836 if (!mcq_vs_res->base)
1837 return -EINVAL;
1838
1839 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
1840
1841 return 0;
1842 }
1843
ufs_qcom_write_msi_msg(struct msi_desc * desc,struct msi_msg * msg)1844 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1845 {
1846 struct device *dev = msi_desc_to_dev(desc);
1847 struct ufs_hba *hba = dev_get_drvdata(dev);
1848
1849 ufshcd_mcq_config_esi(hba, msg);
1850 }
1851
ufs_qcom_mcq_esi_handler(int irq,void * data)1852 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
1853 {
1854 struct msi_desc *desc = data;
1855 struct device *dev = msi_desc_to_dev(desc);
1856 struct ufs_hba *hba = dev_get_drvdata(dev);
1857 u32 id = desc->msi_index;
1858 struct ufs_hw_queue *hwq = &hba->uhq[id];
1859
1860 ufshcd_mcq_write_cqis(hba, 0x1, id);
1861 ufshcd_mcq_poll_cqe_lock(hba, hwq);
1862
1863 return IRQ_HANDLED;
1864 }
1865
ufs_qcom_config_esi(struct ufs_hba * hba)1866 static int ufs_qcom_config_esi(struct ufs_hba *hba)
1867 {
1868 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1869 struct msi_desc *desc;
1870 struct msi_desc *failed_desc = NULL;
1871 int nr_irqs, ret;
1872
1873 if (host->esi_enabled)
1874 return 0;
1875
1876 /*
1877 * 1. We only handle CQs as of now.
1878 * 2. Poll queues do not need ESI.
1879 */
1880 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
1881 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs,
1882 ufs_qcom_write_msi_msg);
1883 if (ret) {
1884 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret);
1885 return ret;
1886 }
1887
1888 msi_lock_descs(hba->dev);
1889 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1890 ret = devm_request_irq(hba->dev, desc->irq,
1891 ufs_qcom_mcq_esi_handler,
1892 IRQF_SHARED, "qcom-mcq-esi", desc);
1893 if (ret) {
1894 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1895 __func__, desc->irq, ret);
1896 failed_desc = desc;
1897 break;
1898 }
1899 }
1900 msi_unlock_descs(hba->dev);
1901
1902 if (ret) {
1903 /* Rewind */
1904 msi_lock_descs(hba->dev);
1905 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1906 if (desc == failed_desc)
1907 break;
1908 devm_free_irq(hba->dev, desc->irq, hba);
1909 }
1910 msi_unlock_descs(hba->dev);
1911 platform_device_msi_free_irqs_all(hba->dev);
1912 } else {
1913 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1914 host->hw_ver.step == 0)
1915 ufshcd_rmwl(hba, ESI_VEC_MASK,
1916 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
1917 REG_UFS_CFG3);
1918 ufshcd_mcq_enable_esi(hba);
1919 host->esi_enabled = true;
1920 }
1921
1922 return ret;
1923 }
1924
ufs_qcom_freq_to_gear_speed(struct ufs_hba * hba,unsigned long freq)1925 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq)
1926 {
1927 u32 gear = 0;
1928
1929 switch (freq) {
1930 case 403000000:
1931 gear = UFS_HS_G5;
1932 break;
1933 case 300000000:
1934 gear = UFS_HS_G4;
1935 break;
1936 case 201500000:
1937 gear = UFS_HS_G3;
1938 break;
1939 case 150000000:
1940 case 100000000:
1941 gear = UFS_HS_G2;
1942 break;
1943 case 75000000:
1944 case 37500000:
1945 gear = UFS_HS_G1;
1946 break;
1947 default:
1948 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq);
1949 break;
1950 }
1951
1952 return gear;
1953 }
1954
1955 /*
1956 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1957 *
1958 * The variant operations configure the necessary controller and PHY
1959 * handshake during initialization.
1960 */
1961 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1962 .name = "qcom",
1963 .init = ufs_qcom_init,
1964 .exit = ufs_qcom_exit,
1965 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1966 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1967 .setup_clocks = ufs_qcom_setup_clocks,
1968 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1969 .link_startup_notify = ufs_qcom_link_startup_notify,
1970 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1971 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1972 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks,
1973 .suspend = ufs_qcom_suspend,
1974 .resume = ufs_qcom_resume,
1975 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1976 .device_reset = ufs_qcom_device_reset,
1977 .config_scaling_param = ufs_qcom_config_scaling_param,
1978 .mcq_config_resource = ufs_qcom_mcq_config_resource,
1979 .get_hba_mac = ufs_qcom_get_hba_mac,
1980 .op_runtime_config = ufs_qcom_op_runtime_config,
1981 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
1982 .config_esi = ufs_qcom_config_esi,
1983 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed,
1984 };
1985
1986 /**
1987 * ufs_qcom_probe - probe routine of the driver
1988 * @pdev: pointer to Platform device handle
1989 *
1990 * Return: zero for success and non-zero for failure.
1991 */
ufs_qcom_probe(struct platform_device * pdev)1992 static int ufs_qcom_probe(struct platform_device *pdev)
1993 {
1994 int err;
1995 struct device *dev = &pdev->dev;
1996
1997 /* Perform generic probe */
1998 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1999 if (err)
2000 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
2001
2002 return 0;
2003 }
2004
2005 /**
2006 * ufs_qcom_remove - set driver_data of the device to NULL
2007 * @pdev: pointer to platform device handle
2008 *
2009 * Always returns 0
2010 */
ufs_qcom_remove(struct platform_device * pdev)2011 static void ufs_qcom_remove(struct platform_device *pdev)
2012 {
2013 struct ufs_hba *hba = platform_get_drvdata(pdev);
2014 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
2015
2016 ufshcd_pltfrm_remove(pdev);
2017 if (host->esi_enabled)
2018 platform_device_msi_free_irqs_all(hba->dev);
2019 }
2020
2021 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = {
2022 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP,
2023 .no_phy_retention = true,
2024 };
2025
2026 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
2027 { .compatible = "qcom,ufshc" },
2028 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2029 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2030 {},
2031 };
2032 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
2033
2034 #ifdef CONFIG_ACPI
2035 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
2036 { "QCOM24A5" },
2037 { },
2038 };
2039 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
2040 #endif
2041
2042 static const struct dev_pm_ops ufs_qcom_pm_ops = {
2043 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
2044 .prepare = ufshcd_suspend_prepare,
2045 .complete = ufshcd_resume_complete,
2046 #ifdef CONFIG_PM_SLEEP
2047 .suspend = ufshcd_system_suspend,
2048 .resume = ufshcd_system_resume,
2049 .freeze = ufshcd_system_freeze,
2050 .restore = ufshcd_system_restore,
2051 .thaw = ufshcd_system_thaw,
2052 #endif
2053 };
2054
2055 static struct platform_driver ufs_qcom_pltform = {
2056 .probe = ufs_qcom_probe,
2057 .remove = ufs_qcom_remove,
2058 .driver = {
2059 .name = "ufshcd-qcom",
2060 .pm = &ufs_qcom_pm_ops,
2061 .of_match_table = of_match_ptr(ufs_qcom_of_match),
2062 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
2063 },
2064 };
2065 module_platform_driver(ufs_qcom_pltform);
2066
2067 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");
2068 MODULE_LICENSE("GPL v2");
2069