1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #ifndef HISI_ACC_QM_H
4 #define HISI_ACC_QM_H
5
6 #include <linux/bitfield.h>
7 #include <linux/debugfs.h>
8 #include <linux/iopoll.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #define QM_QNUM_V1 4096
13 #define QM_QNUM_V2 1024
14 #define QM_MAX_VFS_NUM_V2 63
15
16 /* qm user domain */
17 #define QM_ARUSER_M_CFG_1 0x100088
18 #define AXUSER_SNOOP_ENABLE BIT(30)
19 #define AXUSER_CMD_TYPE GENMASK(14, 12)
20 #define AXUSER_CMD_SMMU_NORMAL 1
21 #define AXUSER_NS BIT(6)
22 #define AXUSER_NO BIT(5)
23 #define AXUSER_FP BIT(4)
24 #define AXUSER_SSV BIT(0)
25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
26 FIELD_PREP(AXUSER_CMD_TYPE, \
27 AXUSER_CMD_SMMU_NORMAL) | \
28 AXUSER_NS | AXUSER_NO | AXUSER_FP)
29 #define QM_ARUSER_M_CFG_ENABLE 0x100090
30 #define ARUSER_M_CFG_ENABLE 0xfffffffe
31 #define QM_AWUSER_M_CFG_1 0x100098
32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
33 #define AWUSER_M_CFG_ENABLE 0xfffffffe
34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
35 #define WUSER_M_CFG_ENABLE 0xffffffff
36
37 /* mailbox */
38 #define QM_MB_CMD_SQC 0x0
39 #define QM_MB_CMD_CQC 0x1
40 #define QM_MB_CMD_EQC 0x2
41 #define QM_MB_CMD_AEQC 0x3
42 #define QM_MB_CMD_SQC_BT 0x4
43 #define QM_MB_CMD_CQC_BT 0x5
44 #define QM_MB_CMD_SQC_VFT_V2 0x6
45 #define QM_MB_CMD_STOP_QP 0x8
46 #define QM_MB_CMD_FLUSH_QM 0x9
47 #define QM_MB_CMD_SRC 0xc
48 #define QM_MB_CMD_DST 0xd
49
50 #define QM_MB_CMD_SEND_BASE 0x300
51 #define QM_MB_EVENT_SHIFT 8
52 #define QM_MB_BUSY_SHIFT 13
53 #define QM_MB_OP_SHIFT 14
54 #define QM_MB_CMD_DATA_ADDR_L 0x304
55 #define QM_MB_CMD_DATA_ADDR_H 0x308
56 #define QM_MB_MAX_WAIT_CNT 6000
57
58 /* doorbell */
59 #define QM_DOORBELL_CMD_SQ 0
60 #define QM_DOORBELL_CMD_CQ 1
61 #define QM_DOORBELL_CMD_EQ 2
62 #define QM_DOORBELL_CMD_AEQ 3
63
64 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
65 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
66 #define QM_QP_MAX_NUM_SHIFT 11
67 #define QM_DB_CMD_SHIFT_V2 12
68 #define QM_DB_RAND_SHIFT_V2 16
69 #define QM_DB_INDEX_SHIFT_V2 32
70 #define QM_DB_PRIORITY_SHIFT_V2 48
71 #define QM_VF_STATE 0x60
72
73 /* qm cache */
74 #define QM_CACHE_CTL 0x100050
75 #define SQC_CACHE_ENABLE BIT(0)
76 #define CQC_CACHE_ENABLE BIT(1)
77 #define SQC_CACHE_WB_ENABLE BIT(4)
78 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
79 #define CQC_CACHE_WB_ENABLE BIT(11)
80 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
81 #define QM_AXI_M_CFG 0x1000ac
82 #define AXI_M_CFG 0xffff
83 #define QM_AXI_M_CFG_ENABLE 0x1000b0
84 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
85 #define AXI_M_CFG_ENABLE 0xffffffff
86 #define QM_PEH_AXUSER_CFG 0x1000cc
87 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
88 #define PEH_AXUSER_CFG 0x401001
89 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
90
91 #define QM_MIN_QNUM 2
92 #define HISI_ACC_SGL_SGE_NR_MAX 255
93 #define QM_SHAPER_CFG 0x100164
94 #define QM_SHAPER_ENABLE BIT(30)
95 #define QM_SHAPER_TYPE1_OFFSET 10
96
97 /* page number for queue file region */
98 #define QM_DOORBELL_PAGE_NR 1
99
100 #define QM_DEV_ALG_MAX_LEN 256
101
102 #define QM_MIG_REGION_SEL 0x100198
103 #define QM_MIG_REGION_EN BIT(0)
104
105 #define QM_MAX_CHANNEL_NUM 8
106 #define QM_CHANNEL_USAGE_OFFSET 0x1100
107 #define QM_MAX_DEV_USAGE 100
108 #define QM_DEV_USAGE_RATE 100
109 #define QM_CHANNEL_ADDR_INTRVL 0x4
110
111 /* uacce mode of the driver */
112 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */
113 #define UACCE_MODE_SVA 1 /* use uacce sva mode */
114 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
115
116 #define QM_ECC_MBIT BIT(2)
117
118 enum qm_stop_reason {
119 QM_NORMAL,
120 QM_SOFT_RESET,
121 QM_DOWN,
122 };
123
124 enum qm_state {
125 QM_WORK = 0,
126 QM_STOP,
127 };
128
129 enum qp_state {
130 QP_START = 1,
131 QP_STOP,
132 };
133
134 enum qm_hw_ver {
135 QM_HW_V1 = 0x20,
136 QM_HW_V2 = 0x21,
137 QM_HW_V3 = 0x30,
138 QM_HW_V4 = 0x50,
139 QM_HW_V5 = 0x51,
140 };
141
142 enum qm_fun_type {
143 QM_HW_PF,
144 QM_HW_VF,
145 };
146
147 enum qm_debug_file {
148 CURRENT_QM,
149 CURRENT_Q,
150 CLEAR_ENABLE,
151 DEBUG_FILE_NUM,
152 };
153
154 enum qm_vf_state {
155 QM_READY = 0,
156 QM_NOT_READY,
157 };
158
159 enum qm_misc_ctl_bits {
160 QM_DRIVER_REMOVING = 0x0,
161 QM_RST_SCHED,
162 QM_RESETTING,
163 QM_MODULE_PARAM,
164 };
165
166 enum qm_cap_bits {
167 QM_SUPPORT_DB_ISOLATION = 0x0,
168 QM_SUPPORT_FUNC_QOS,
169 QM_SUPPORT_STOP_QP,
170 QM_SUPPORT_STOP_FUNC,
171 QM_SUPPORT_MB_COMMAND,
172 QM_SUPPORT_SVA_PREFETCH,
173 QM_SUPPORT_RPM,
174 QM_SUPPORT_DAE,
175 };
176
177 struct qm_dev_alg {
178 u64 alg_msk;
179 const char *alg;
180 };
181
182 struct qm_dev_dfx {
183 u32 dev_state;
184 u32 dev_timeout;
185 };
186
187 struct dfx_diff_registers {
188 u32 *regs;
189 u32 reg_offset;
190 u32 reg_len;
191 };
192
193 struct qm_dfx {
194 atomic64_t err_irq_cnt;
195 atomic64_t aeq_irq_cnt;
196 atomic64_t abnormal_irq_cnt;
197 atomic64_t create_qp_err_cnt;
198 atomic64_t mb_err_cnt;
199 };
200
201 struct debugfs_file {
202 enum qm_debug_file index;
203 struct mutex lock;
204 struct qm_debug *debug;
205 };
206
207 struct qm_debug {
208 u32 curr_qm_qp_num;
209 u32 sqe_mask_offset;
210 u32 sqe_mask_len;
211 struct qm_dfx dfx;
212 struct dentry *debug_root;
213 struct dentry *qm_d;
214 struct debugfs_file files[DEBUG_FILE_NUM];
215 struct qm_dev_dfx dev_dfx;
216 unsigned int *qm_last_words;
217 /* ACC engines recoreding last regs */
218 unsigned int *last_words;
219 struct dfx_diff_registers *qm_diff_regs;
220 struct dfx_diff_registers *acc_diff_regs;
221 };
222
223 struct qm_shaper_factor {
224 u32 func_qos;
225 u64 cir_b;
226 u64 cir_u;
227 u64 cir_s;
228 u64 cbs_s;
229 };
230
231 struct qm_dma {
232 void *va;
233 dma_addr_t dma;
234 size_t size;
235 };
236
237 struct hisi_qm_status {
238 u32 eq_head;
239 bool eqc_phase;
240 u32 aeq_head;
241 bool aeqc_phase;
242 atomic_t flags;
243 int stop_reason;
244 };
245
246 struct hisi_qm;
247
248 enum acc_err_result {
249 ACC_ERR_NONE,
250 ACC_ERR_NEED_RESET,
251 ACC_ERR_RECOVERED,
252 };
253
254 struct hisi_qm_err_mask {
255 u32 ecc_2bits_mask;
256 u32 shutdown_mask;
257 u32 reset_mask;
258 u32 ce;
259 u32 nfe;
260 u32 fe;
261 };
262
263 struct hisi_qm_err_info {
264 char *acpi_rst;
265 u32 msi_wr_port;
266 struct hisi_qm_err_mask qm_err;
267 struct hisi_qm_err_mask dev_err;
268 };
269
270 struct hisi_qm_err_status {
271 u32 is_qm_ecc_mbit;
272 u32 is_dev_ecc_mbit;
273 };
274
275 struct hisi_qm_err_ini {
276 int (*hw_init)(struct hisi_qm *qm);
277 void (*hw_err_enable)(struct hisi_qm *qm);
278 void (*hw_err_disable)(struct hisi_qm *qm);
279 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
280 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
281 void (*open_axi_master_ooo)(struct hisi_qm *qm);
282 void (*close_axi_master_ooo)(struct hisi_qm *qm);
283 void (*open_sva_prefetch)(struct hisi_qm *qm);
284 void (*close_sva_prefetch)(struct hisi_qm *qm);
285 void (*show_last_dfx_regs)(struct hisi_qm *qm);
286 void (*err_info_init)(struct hisi_qm *qm);
287 enum acc_err_result (*get_err_result)(struct hisi_qm *qm);
288 bool (*dev_is_abnormal)(struct hisi_qm *qm);
289 int (*set_priv_status)(struct hisi_qm *qm);
290 void (*disable_axi_error)(struct hisi_qm *qm);
291 void (*enable_axi_error)(struct hisi_qm *qm);
292 };
293
294 struct hisi_qm_cap_info {
295 u32 type;
296 /* Register offset */
297 u32 offset;
298 /* Bit offset in register */
299 u32 shift;
300 u32 mask;
301 u32 v1_val;
302 u32 v2_val;
303 u32 v3_val;
304 };
305
306 struct hisi_qm_cap_query_info {
307 u32 type;
308 const char *name;
309 u32 offset;
310 u32 v1_val;
311 u32 v2_val;
312 u32 v3_val;
313 };
314
315 struct hisi_qm_cap_record {
316 u32 type;
317 const char *name;
318 u32 cap_val;
319 };
320
321 struct hisi_qm_cap_tables {
322 u32 qm_cap_size;
323 struct hisi_qm_cap_record *qm_cap_table;
324 u32 dev_cap_size;
325 struct hisi_qm_cap_record *dev_cap_table;
326 };
327
328 struct hisi_qm_list {
329 struct mutex lock;
330 struct list_head list;
331 int (*register_to_crypto)(struct hisi_qm *qm);
332 void (*unregister_from_crypto)(struct hisi_qm *qm);
333 };
334
335 struct hisi_qm_poll_data {
336 struct hisi_qm *qm;
337 struct work_struct work;
338 u16 *qp_finish_id;
339 u16 eqe_num;
340 };
341
342 /**
343 * struct qm_err_isolate
344 * @isolate_lock: protects device error log
345 * @err_threshold: user config error threshold which triggers isolation
346 * @is_isolate: device isolation state
347 * @uacce_hw_errs: index into qm device error list
348 */
349 struct qm_err_isolate {
350 struct mutex isolate_lock;
351 u32 err_threshold;
352 bool is_isolate;
353 struct list_head qm_hw_errs;
354 };
355
356 struct qm_rsv_buf {
357 struct qm_sqc *sqc;
358 struct qm_cqc *cqc;
359 struct qm_eqc *eqc;
360 struct qm_aeqc *aeqc;
361 dma_addr_t sqc_dma;
362 dma_addr_t cqc_dma;
363 dma_addr_t eqc_dma;
364 dma_addr_t aeqc_dma;
365 struct qm_dma qcdma;
366 };
367
368 struct qm_channel {
369 int channel_num;
370 const char *channel_name[QM_MAX_CHANNEL_NUM];
371 };
372
373 struct hisi_qm {
374 enum qm_hw_ver ver;
375 enum qm_fun_type fun_type;
376 const char *dev_name;
377 struct pci_dev *pdev;
378 void __iomem *io_base;
379 void __iomem *db_io_base;
380
381 /* Capbility version, 0: not supports */
382 u32 cap_ver;
383 u32 sqe_size;
384 u32 qp_base;
385 u32 qp_num;
386 u32 qp_in_used;
387 u32 ctrl_qp_num;
388 u32 max_qp_num;
389 u32 vfs_num;
390 u32 db_interval;
391 u16 eq_depth;
392 u16 aeq_depth;
393 struct list_head list;
394 struct hisi_qm_list *qm_list;
395
396 struct qm_dma qdma;
397 struct qm_sqc *sqc;
398 struct qm_cqc *cqc;
399 struct qm_eqe *eqe;
400 struct qm_aeqe *aeqe;
401 dma_addr_t sqc_dma;
402 dma_addr_t cqc_dma;
403 dma_addr_t eqe_dma;
404 dma_addr_t aeqe_dma;
405 struct qm_rsv_buf xqc_buf;
406
407 struct hisi_qm_status status;
408 const struct hisi_qm_err_ini *err_ini;
409 struct hisi_qm_err_info err_info;
410 struct hisi_qm_err_status err_status;
411 /* driver removing and reset sched */
412 unsigned long misc_ctl;
413 /* Device capability bit */
414 unsigned long caps;
415
416 struct rw_semaphore qps_lock;
417 struct idr qp_idr;
418 struct hisi_qp *qp_array;
419 struct hisi_qm_poll_data *poll_data;
420
421 struct mutex mailbox_lock;
422
423 struct mutex ifc_lock;
424
425 const struct hisi_qm_hw_ops *ops;
426
427 struct qm_debug debug;
428
429 u32 error_mask;
430
431 struct workqueue_struct *wq;
432 struct work_struct rst_work;
433 struct work_struct cmd_process;
434
435 bool use_sva;
436
437 resource_size_t phys_base;
438 resource_size_t db_phys_base;
439 struct uacce_device *uacce;
440 int mode;
441 struct qm_shaper_factor *factor;
442 u32 mb_qos;
443 u32 type_rate;
444 struct qm_err_isolate isolate_data;
445
446 struct hisi_qm_cap_tables cap_tables;
447 struct qm_channel channel_data;
448 };
449
450 struct hisi_qp_status {
451 atomic_t used;
452 u16 sq_tail;
453 u16 cq_head;
454 bool cqc_phase;
455 atomic_t flags;
456 };
457
458 struct hisi_qp_ops {
459 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
460 };
461
462 struct instance_backlog {
463 struct list_head list;
464 spinlock_t lock;
465 };
466
467 struct hisi_qp {
468 u32 qp_id;
469 u16 sq_depth;
470 u16 cq_depth;
471 u8 alg_type;
472
473 struct qm_dma qdma;
474 void *sqe;
475 struct qm_cqe *cqe;
476 dma_addr_t sqe_dma;
477 dma_addr_t cqe_dma;
478
479 struct hisi_qp_status qp_status;
480 struct hisi_qp_ops *hw_ops;
481 void (*req_cb)(struct hisi_qp *qp, void *data);
482 void (*event_cb)(struct hisi_qp *qp);
483
484 struct hisi_qm *qm;
485 bool is_resetting;
486 bool is_in_kernel;
487 u16 pasid;
488 struct uacce_queue *uacce_q;
489
490 u32 ref_count;
491 spinlock_t qp_lock;
492 struct instance_backlog backlog;
493 const void **msg;
494 };
495
vfs_num_set(const char * val,const struct kernel_param * kp)496 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
497 {
498 u32 n;
499 int ret;
500
501 if (!val)
502 return -EINVAL;
503
504 ret = kstrtou32(val, 10, &n);
505 if (ret < 0)
506 return ret;
507
508 if (n > QM_MAX_VFS_NUM_V2)
509 return -EINVAL;
510
511 return param_set_int(val, kp);
512 }
513
mode_set(const char * val,const struct kernel_param * kp)514 static inline int mode_set(const char *val, const struct kernel_param *kp)
515 {
516 u32 n;
517 int ret;
518
519 if (!val)
520 return -EINVAL;
521
522 ret = kstrtou32(val, 10, &n);
523 if (ret != 0 || (n != UACCE_MODE_SVA &&
524 n != UACCE_MODE_NOUACCE))
525 return -EINVAL;
526
527 return param_set_int(val, kp);
528 }
529
uacce_mode_set(const char * val,const struct kernel_param * kp)530 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
531 {
532 return mode_set(val, kp);
533 }
534
hisi_qm_init_list(struct hisi_qm_list * qm_list)535 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
536 {
537 INIT_LIST_HEAD(&qm_list->list);
538 mutex_init(&qm_list->lock);
539 }
540
hisi_qm_add_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)541 static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
542 {
543 mutex_lock(&qm_list->lock);
544 list_add_tail(&qm->list, &qm_list->list);
545 mutex_unlock(&qm_list->lock);
546 }
547
hisi_qm_del_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)548 static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
549 {
550 mutex_lock(&qm_list->lock);
551 list_del(&qm->list);
552 mutex_unlock(&qm_list->lock);
553 }
554
555 int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp,
556 unsigned int device);
557 int hisi_qm_init(struct hisi_qm *qm);
558 void hisi_qm_uninit(struct hisi_qm *qm);
559 int hisi_qm_start(struct hisi_qm *qm);
560 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
561 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
562 void hisi_qm_debug_init(struct hisi_qm *qm);
563 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
564 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
565 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
566 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
567 void hisi_qm_dev_err_init(struct hisi_qm *qm);
568 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
569 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
570 struct dfx_diff_registers *dregs, u32 reg_len);
571 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
572 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
573 struct dfx_diff_registers *dregs, u32 regs_len);
574
575 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
576 pci_channel_state_t state);
577 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
578 void hisi_qm_reset_prepare(struct pci_dev *pdev);
579 void hisi_qm_reset_done(struct pci_dev *pdev);
580
581 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
582 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
583 bool op);
584 int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue);
585
586 struct hisi_acc_sgl_pool;
587 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
588 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
589 u32 index, dma_addr_t *hw_sgl_dma, enum dma_data_direction dir);
590 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
591 struct hisi_acc_hw_sgl *hw_sgl, enum dma_data_direction dir);
592 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
593 u32 count, u32 sge_nr);
594 void hisi_acc_free_sgl_pool(struct device *dev,
595 struct hisi_acc_sgl_pool *pool);
596 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
597 u8 *alg_type, int node, struct hisi_qp **qps);
598 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
599 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
600 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
601 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
602 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
603 int hisi_qm_resume(struct device *dev);
604 int hisi_qm_suspend(struct device *dev);
605 void hisi_qm_pm_uninit(struct hisi_qm *qm);
606 void hisi_qm_pm_init(struct hisi_qm *qm);
607 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
608 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
609 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
610 u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
611 const struct hisi_qm_cap_info *info_table,
612 u32 index, bool is_read);
613 u32 hisi_qm_get_cap_value(struct hisi_qm *qm,
614 const struct hisi_qm_cap_query_info *info_table,
615 u32 index, bool is_read);
616 int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
617 u32 dev_algs_size);
618
619 /* Used by VFIO ACC live migration driver */
620 struct pci_driver *hisi_sec_get_pf_driver(void);
621 struct pci_driver *hisi_hpre_get_pf_driver(void);
622 struct pci_driver *hisi_zip_get_pf_driver(void);
623 #endif
624