1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/string.h> 9 #include <linux/etherdevice.h> 10 #include <linux/phylink.h> 11 #include <net/udp_tunnel.h> 12 #include <net/ip.h> 13 #include <linux/if_vlan.h> 14 15 #include "../libwx/wx_type.h" 16 #include "../libwx/wx_lib.h" 17 #include "../libwx/wx_ptp.h" 18 #include "../libwx/wx_hw.h" 19 #include "../libwx/wx_mbx.h" 20 #include "../libwx/wx_sriov.h" 21 #include "txgbe_type.h" 22 #include "txgbe_hw.h" 23 #include "txgbe_phy.h" 24 #include "txgbe_aml.h" 25 #include "txgbe_irq.h" 26 #include "txgbe_fdir.h" 27 #include "txgbe_ethtool.h" 28 29 char txgbe_driver_name[] = "txgbe"; 30 31 /* txgbe_pci_tbl - PCI Device ID Table 32 * 33 * Wildcard entries (PCI_ANY_ID) should come last 34 * Last entry must be all 0s 35 * 36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 37 * Class, Class Mask, private data (not used) } 38 */ 39 static const struct pci_device_id txgbe_pci_tbl[] = { 40 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_SP1000), 0}, 41 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_WX1820), 0}, 42 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5010), 0}, 43 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5110), 0}, 44 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5025), 0}, 45 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5125), 0}, 46 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5040), 0}, 47 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5140), 0}, 48 /* required last entry */ 49 { .device = 0 } 50 }; 51 52 #define DEFAULT_DEBUG_LEVEL_SHIFT 3 53 54 static void txgbe_check_minimum_link(struct wx *wx) 55 { 56 struct pci_dev *pdev; 57 58 pdev = wx->pdev; 59 pcie_print_link_status(pdev); 60 } 61 62 /** 63 * txgbe_enumerate_functions - Get the number of ports this device has 64 * @wx: wx structure 65 * 66 * This function enumerates the phsyical functions co-located on a single slot, 67 * in order to determine how many ports a device has. This is most useful in 68 * determining the required GT/s of PCIe bandwidth necessary for optimal 69 * performance. 70 **/ 71 static int txgbe_enumerate_functions(struct wx *wx) 72 { 73 struct pci_dev *entry, *pdev = wx->pdev; 74 int physfns = 0; 75 76 list_for_each_entry(entry, &pdev->bus->devices, bus_list) { 77 /* When the devices on the bus don't all match our device ID, 78 * we can't reliably determine the correct number of 79 * functions. This can occur if a function has been direct 80 * attached to a virtual machine using VT-d. 81 */ 82 if (entry->vendor != pdev->vendor || 83 entry->device != pdev->device) 84 return -EINVAL; 85 86 physfns++; 87 } 88 89 return physfns; 90 } 91 92 static void txgbe_module_detection_subtask(struct wx *wx) 93 { 94 int err; 95 96 if (!test_bit(WX_FLAG_NEED_MODULE_RESET, wx->flags)) 97 return; 98 99 /* wait for SFF module ready */ 100 msleep(200); 101 102 err = txgbe_identify_module(wx); 103 if (err) 104 return; 105 106 clear_bit(WX_FLAG_NEED_MODULE_RESET, wx->flags); 107 } 108 109 static void txgbe_link_config_subtask(struct wx *wx) 110 { 111 int err; 112 113 if (!test_bit(WX_FLAG_NEED_LINK_CONFIG, wx->flags)) 114 return; 115 116 err = txgbe_set_phy_link(wx); 117 if (err) 118 return; 119 120 clear_bit(WX_FLAG_NEED_LINK_CONFIG, wx->flags); 121 } 122 123 /** 124 * txgbe_service_task - manages and runs subtasks 125 * @work: pointer to work_struct containing our data 126 **/ 127 static void txgbe_service_task(struct work_struct *work) 128 { 129 struct wx *wx = container_of(work, struct wx, service_task); 130 131 txgbe_module_detection_subtask(wx); 132 txgbe_link_config_subtask(wx); 133 wx_update_stats(wx); 134 135 wx_service_event_complete(wx); 136 } 137 138 static void txgbe_init_service(struct wx *wx) 139 { 140 timer_setup(&wx->service_timer, wx_service_timer, 0); 141 INIT_WORK(&wx->service_task, txgbe_service_task); 142 clear_bit(WX_STATE_SERVICE_SCHED, wx->state); 143 } 144 145 static void txgbe_up_complete(struct wx *wx) 146 { 147 struct net_device *netdev = wx->netdev; 148 149 wx_control_hw(wx, true); 150 wx_configure_vectors(wx); 151 152 /* make sure to complete pre-operations */ 153 smp_mb__before_atomic(); 154 wx_napi_enable_all(wx); 155 156 switch (wx->mac.type) { 157 case wx_mac_aml40: 158 txgbe_setup_link(wx); 159 phylink_start(wx->phylink); 160 break; 161 case wx_mac_aml: 162 /* Enable TX laser */ 163 wr32m(wx, WX_GPIO_DR, TXGBE_GPIOBIT_1, 0); 164 txgbe_setup_link(wx); 165 phylink_start(wx->phylink); 166 break; 167 case wx_mac_sp: 168 phylink_start(wx->phylink); 169 break; 170 default: 171 break; 172 } 173 174 /* clear any pending interrupts, may auto mask */ 175 rd32(wx, WX_PX_IC(0)); 176 rd32(wx, WX_PX_IC(1)); 177 rd32(wx, WX_PX_MISC_IC); 178 txgbe_irq_enable(wx, true); 179 180 /* enable transmits */ 181 netif_tx_start_all_queues(netdev); 182 mod_timer(&wx->service_timer, jiffies); 183 184 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 185 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_PFRSTD, 186 WX_CFG_PORT_CTL_PFRSTD); 187 /* update setting rx tx for all active vfs */ 188 wx_set_all_vfs(wx); 189 } 190 191 static void txgbe_reset(struct wx *wx) 192 { 193 struct net_device *netdev = wx->netdev; 194 u8 old_addr[ETH_ALEN]; 195 int err; 196 197 err = txgbe_reset_hw(wx); 198 if (err != 0) 199 wx_err(wx, "Hardware Error: %d\n", err); 200 201 wx_start_hw(wx); 202 /* do not flush user set addresses */ 203 memcpy(old_addr, &wx->mac_table[0].addr, netdev->addr_len); 204 wx_flush_sw_mac_table(wx); 205 wx_mac_set_default_filter(wx, old_addr); 206 207 if (test_bit(WX_STATE_PTP_RUNNING, wx->state)) 208 wx_ptp_reset(wx); 209 } 210 211 static void txgbe_disable_device(struct wx *wx) 212 { 213 struct net_device *netdev = wx->netdev; 214 u32 i; 215 216 wx_disable_pcie_master(wx); 217 /* disable receives */ 218 wx_disable_rx(wx); 219 220 /* disable all enabled rx queues */ 221 for (i = 0; i < wx->num_rx_queues; i++) 222 /* this call also flushes the previous write */ 223 wx_disable_rx_queue(wx, wx->rx_ring[i]); 224 225 netif_tx_stop_all_queues(netdev); 226 netif_tx_disable(netdev); 227 228 wx_irq_disable(wx); 229 wx_napi_disable_all(wx); 230 231 timer_delete_sync(&wx->service_timer); 232 233 if (wx->bus.func < 2) 234 wr32m(wx, TXGBE_MIS_PRB_CTL, TXGBE_MIS_PRB_CTL_LAN_UP(wx->bus.func), 0); 235 else 236 wx_err(wx, "%s: invalid bus lan id %d\n", 237 __func__, wx->bus.func); 238 239 if (wx->num_vfs) { 240 /* Clear EITR Select mapping */ 241 wr32(wx, WX_PX_ITRSEL, 0); 242 /* Mark all the VFs as inactive */ 243 for (i = 0; i < wx->num_vfs; i++) 244 wx->vfinfo[i].clear_to_send = 0; 245 /* update setting rx tx for all active vfs */ 246 wx_set_all_vfs(wx); 247 } 248 249 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 250 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 251 /* disable mac transmiter */ 252 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 253 } 254 255 /* disable transmits in the hardware now that interrupts are off */ 256 for (i = 0; i < wx->num_tx_queues; i++) { 257 u8 reg_idx = wx->tx_ring[i]->reg_idx; 258 259 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); 260 } 261 262 /* Disable the Tx DMA engine */ 263 wr32m(wx, WX_TDM_CTL, WX_TDM_CTL_TE, 0); 264 265 wx_update_stats(wx); 266 } 267 268 void txgbe_down(struct wx *wx) 269 { 270 txgbe_disable_device(wx); 271 txgbe_reset(wx); 272 273 switch (wx->mac.type) { 274 case wx_mac_aml40: 275 phylink_stop(wx->phylink); 276 break; 277 case wx_mac_aml: 278 phylink_stop(wx->phylink); 279 /* Disable TX laser */ 280 wr32m(wx, WX_GPIO_DR, TXGBE_GPIOBIT_1, TXGBE_GPIOBIT_1); 281 break; 282 case wx_mac_sp: 283 phylink_stop(wx->phylink); 284 break; 285 default: 286 break; 287 } 288 289 wx_clean_all_tx_rings(wx); 290 wx_clean_all_rx_rings(wx); 291 } 292 293 void txgbe_up(struct wx *wx) 294 { 295 wx_configure(wx); 296 wx_ptp_init(wx); 297 txgbe_up_complete(wx); 298 } 299 300 /** 301 * txgbe_init_type_code - Initialize the shared code 302 * @wx: pointer to hardware structure 303 **/ 304 static void txgbe_init_type_code(struct wx *wx) 305 { 306 u8 device_type = wx->subsystem_device_id & 0xF0; 307 308 switch (wx->device_id) { 309 case TXGBE_DEV_ID_SP1000: 310 case TXGBE_DEV_ID_WX1820: 311 wx->mac.type = wx_mac_sp; 312 break; 313 case TXGBE_DEV_ID_AML5010: 314 case TXGBE_DEV_ID_AML5110: 315 case TXGBE_DEV_ID_AML5025: 316 case TXGBE_DEV_ID_AML5125: 317 wx->mac.type = wx_mac_aml; 318 break; 319 case TXGBE_DEV_ID_AML5040: 320 case TXGBE_DEV_ID_AML5140: 321 wx->mac.type = wx_mac_aml40; 322 break; 323 default: 324 wx->mac.type = wx_mac_unknown; 325 break; 326 } 327 328 switch (device_type) { 329 case TXGBE_ID_SFP: 330 wx->media_type = wx_media_fiber; 331 break; 332 case TXGBE_ID_XAUI: 333 case TXGBE_ID_SGMII: 334 wx->media_type = wx_media_copper; 335 break; 336 case TXGBE_ID_KR_KX_KX4: 337 case TXGBE_ID_MAC_XAUI: 338 case TXGBE_ID_MAC_SGMII: 339 wx->media_type = wx_media_backplane; 340 break; 341 case TXGBE_ID_SFI_XAUI: 342 if (wx->bus.func == 0) 343 wx->media_type = wx_media_fiber; 344 else 345 wx->media_type = wx_media_copper; 346 break; 347 default: 348 wx->media_type = wx_media_unknown; 349 break; 350 } 351 } 352 353 /** 354 * txgbe_sw_init - Initialize general software structures (struct wx) 355 * @wx: board private structure to initialize 356 **/ 357 static int txgbe_sw_init(struct wx *wx) 358 { 359 u16 msix_count = 0; 360 int err; 361 362 wx->mac.num_rar_entries = TXGBE_RAR_ENTRIES; 363 wx->mac.max_tx_queues = TXGBE_MAX_TXQ; 364 wx->mac.max_rx_queues = TXGBE_MAX_RXQ; 365 wx->mac.mcft_size = TXGBE_MC_TBL_SIZE; 366 wx->mac.vft_size = TXGBE_VFT_TBL_SIZE; 367 wx->mac.rx_pb_size = TXGBE_RX_PB_SIZE; 368 wx->mac.tx_pb_size = TXGBE_TDB_PB_SZ; 369 370 /* PCI config space info */ 371 err = wx_sw_init(wx); 372 if (err < 0) 373 return err; 374 375 txgbe_init_type_code(wx); 376 377 /* Set common capability flags and settings */ 378 wx->max_q_vectors = TXGBE_MAX_MSIX_VECTORS; 379 err = wx_get_pcie_msix_counts(wx, &msix_count, TXGBE_MAX_MSIX_VECTORS); 380 if (err) 381 wx_err(wx, "Do not support MSI-X\n"); 382 wx->mac.max_msix_vectors = msix_count; 383 384 wx->ring_feature[RING_F_RSS].limit = min_t(int, TXGBE_MAX_RSS_INDICES, 385 num_online_cpus()); 386 wx->rss_enabled = true; 387 388 wx->ring_feature[RING_F_FDIR].limit = min_t(int, TXGBE_MAX_FDIR_INDICES, 389 num_online_cpus()); 390 set_bit(WX_FLAG_FDIR_CAPABLE, wx->flags); 391 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 392 wx->atr_sample_rate = TXGBE_DEFAULT_ATR_SAMPLE_RATE; 393 wx->atr = txgbe_atr; 394 wx->configure_fdir = txgbe_configure_fdir; 395 396 set_bit(WX_FLAG_RSC_CAPABLE, wx->flags); 397 set_bit(WX_FLAG_RSC_ENABLED, wx->flags); 398 set_bit(WX_FLAG_MULTI_64_FUNC, wx->flags); 399 400 /* enable itr by default in dynamic mode */ 401 wx->adaptive_itr = true; 402 wx->rx_itr_setting = 1; 403 wx->tx_itr_setting = 1; 404 405 /* set default ring sizes */ 406 wx->tx_ring_count = TXGBE_DEFAULT_TXD; 407 wx->rx_ring_count = TXGBE_DEFAULT_RXD; 408 wx->mbx.size = WX_VXMAILBOX_SIZE; 409 410 /* set default work limits */ 411 wx->tx_work_limit = TXGBE_DEFAULT_TX_WORK; 412 wx->rx_work_limit = TXGBE_DEFAULT_RX_WORK; 413 414 wx->setup_tc = txgbe_setup_tc; 415 wx->do_reset = txgbe_do_reset; 416 set_bit(0, &wx->fwd_bitmask); 417 418 switch (wx->mac.type) { 419 case wx_mac_sp: 420 break; 421 case wx_mac_aml: 422 case wx_mac_aml40: 423 set_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags); 424 set_bit(WX_FLAG_TXHEAD_WB_ENABLED, wx->flags); 425 set_bit(WX_FLAG_SWFW_RING, wx->flags); 426 wx->swfw_index = 0; 427 break; 428 default: 429 break; 430 } 431 432 return 0; 433 } 434 435 static void txgbe_init_fdir(struct txgbe *txgbe) 436 { 437 txgbe->fdir_filter_count = 0; 438 spin_lock_init(&txgbe->fdir_perfect_lock); 439 } 440 441 /** 442 * txgbe_open - Called when a network interface is made active 443 * @netdev: network interface device structure 444 * 445 * Returns 0 on success, negative value on failure 446 * 447 * The open entry point is called when a network interface is made 448 * active by the system (IFF_UP). 449 **/ 450 static int txgbe_open(struct net_device *netdev) 451 { 452 struct wx *wx = netdev_priv(netdev); 453 int err; 454 455 err = wx_setup_resources(wx); 456 if (err) 457 goto err_reset; 458 459 wx_configure(wx); 460 461 err = txgbe_setup_misc_irq(wx->priv); 462 if (err) 463 goto err_free_resources; 464 465 err = txgbe_request_queue_irqs(wx); 466 if (err) 467 goto err_free_misc_irq; 468 469 /* Notify the stack of the actual queue counts. */ 470 err = netif_set_real_num_tx_queues(netdev, wx->num_tx_queues); 471 if (err) 472 goto err_free_irq; 473 474 err = netif_set_real_num_rx_queues(netdev, wx->num_rx_queues); 475 if (err) 476 goto err_free_irq; 477 478 wx_ptp_init(wx); 479 480 txgbe_up_complete(wx); 481 482 return 0; 483 484 err_free_irq: 485 wx_free_irq(wx); 486 err_free_misc_irq: 487 txgbe_free_misc_irq(wx->priv); 488 wx_reset_interrupt_capability(wx); 489 err_free_resources: 490 wx_free_resources(wx); 491 err_reset: 492 txgbe_reset(wx); 493 494 return err; 495 } 496 497 /** 498 * txgbe_close_suspend - actions necessary to both suspend and close flows 499 * @wx: the private wx struct 500 * 501 * This function should contain the necessary work common to both suspending 502 * and closing of the device. 503 */ 504 static void txgbe_close_suspend(struct wx *wx) 505 { 506 wx_ptp_suspend(wx); 507 txgbe_disable_device(wx); 508 wx_free_resources(wx); 509 } 510 511 /** 512 * txgbe_close - Disables a network interface 513 * @netdev: network interface device structure 514 * 515 * Returns 0, this is not allowed to fail 516 * 517 * The close entry point is called when an interface is de-activated 518 * by the OS. The hardware is still under the drivers control, but 519 * needs to be disabled. A global MAC reset is issued to stop the 520 * hardware, and all transmit and receive resources are freed. 521 **/ 522 static int txgbe_close(struct net_device *netdev) 523 { 524 struct wx *wx = netdev_priv(netdev); 525 526 wx_ptp_stop(wx); 527 txgbe_down(wx); 528 wx_free_irq(wx); 529 txgbe_free_misc_irq(wx->priv); 530 wx_free_resources(wx); 531 txgbe_fdir_filter_exit(wx); 532 wx_control_hw(wx, false); 533 534 return 0; 535 } 536 537 static void txgbe_dev_shutdown(struct pci_dev *pdev) 538 { 539 struct wx *wx = pci_get_drvdata(pdev); 540 struct net_device *netdev; 541 542 netdev = wx->netdev; 543 netif_device_detach(netdev); 544 545 rtnl_lock(); 546 if (netif_running(netdev)) 547 txgbe_close_suspend(wx); 548 rtnl_unlock(); 549 550 wx_control_hw(wx, false); 551 552 pci_disable_device(pdev); 553 } 554 555 static void txgbe_shutdown(struct pci_dev *pdev) 556 { 557 txgbe_dev_shutdown(pdev); 558 559 if (system_state == SYSTEM_POWER_OFF) { 560 pci_wake_from_d3(pdev, false); 561 pci_set_power_state(pdev, PCI_D3hot); 562 } 563 } 564 565 /** 566 * txgbe_setup_tc - routine to configure net_device for multiple traffic 567 * classes. 568 * 569 * @dev: net device to configure 570 * @tc: number of traffic classes to enable 571 */ 572 int txgbe_setup_tc(struct net_device *dev, u8 tc) 573 { 574 struct wx *wx = netdev_priv(dev); 575 576 /* Hardware has to reinitialize queues and interrupts to 577 * match packet buffer alignment. Unfortunately, the 578 * hardware is not flexible enough to do this dynamically. 579 */ 580 if (netif_running(dev)) 581 txgbe_close(dev); 582 else 583 txgbe_reset(wx); 584 585 wx_clear_interrupt_scheme(wx); 586 587 if (tc) 588 netdev_set_num_tc(dev, tc); 589 else 590 netdev_reset_tc(dev); 591 592 wx_init_interrupt_scheme(wx); 593 594 if (netif_running(dev)) 595 txgbe_open(dev); 596 597 return 0; 598 } 599 600 static void txgbe_reinit_locked(struct wx *wx) 601 { 602 netif_trans_update(wx->netdev); 603 604 mutex_lock(&wx->reset_lock); 605 set_bit(WX_STATE_RESETTING, wx->state); 606 607 txgbe_down(wx); 608 txgbe_up(wx); 609 610 clear_bit(WX_STATE_RESETTING, wx->state); 611 mutex_unlock(&wx->reset_lock); 612 } 613 614 void txgbe_do_reset(struct net_device *netdev) 615 { 616 struct wx *wx = netdev_priv(netdev); 617 618 if (netif_running(netdev)) 619 txgbe_reinit_locked(wx); 620 else 621 txgbe_reset(wx); 622 } 623 624 static int txgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 625 { 626 struct wx *wx = netdev_priv(dev); 627 struct udp_tunnel_info ti; 628 629 udp_tunnel_nic_get_port(dev, table, 0, &ti); 630 switch (ti.type) { 631 case UDP_TUNNEL_TYPE_VXLAN: 632 wr32(wx, TXGBE_CFG_VXLAN, ntohs(ti.port)); 633 break; 634 case UDP_TUNNEL_TYPE_VXLAN_GPE: 635 wr32(wx, TXGBE_CFG_VXLAN_GPE, ntohs(ti.port)); 636 break; 637 case UDP_TUNNEL_TYPE_GENEVE: 638 wr32(wx, TXGBE_CFG_GENEVE, ntohs(ti.port)); 639 break; 640 default: 641 break; 642 } 643 644 return 0; 645 } 646 647 static const struct udp_tunnel_nic_info txgbe_udp_tunnels = { 648 .sync_table = txgbe_udp_tunnel_sync, 649 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 650 .tables = { 651 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 652 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN_GPE, }, 653 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 654 }, 655 }; 656 657 static const struct net_device_ops txgbe_netdev_ops = { 658 .ndo_open = txgbe_open, 659 .ndo_stop = txgbe_close, 660 .ndo_change_mtu = wx_change_mtu, 661 .ndo_start_xmit = wx_xmit_frame, 662 .ndo_set_rx_mode = wx_set_rx_mode, 663 .ndo_set_features = wx_set_features, 664 .ndo_fix_features = wx_fix_features, 665 .ndo_features_check = wx_features_check, 666 .ndo_validate_addr = eth_validate_addr, 667 .ndo_set_mac_address = wx_set_mac, 668 .ndo_get_stats64 = wx_get_stats64, 669 .ndo_vlan_rx_add_vid = wx_vlan_rx_add_vid, 670 .ndo_vlan_rx_kill_vid = wx_vlan_rx_kill_vid, 671 .ndo_hwtstamp_set = wx_hwtstamp_set, 672 .ndo_hwtstamp_get = wx_hwtstamp_get, 673 }; 674 675 /** 676 * txgbe_probe - Device Initialization Routine 677 * @pdev: PCI device information struct 678 * @ent: entry in txgbe_pci_tbl 679 * 680 * Returns 0 on success, negative on failure 681 * 682 * txgbe_probe initializes an adapter identified by a pci_dev structure. 683 * The OS initialization, configuring of the wx private structure, 684 * and a hardware reset occur. 685 **/ 686 static int txgbe_probe(struct pci_dev *pdev, 687 const struct pci_device_id __always_unused *ent) 688 { 689 struct net_device *netdev; 690 int err, expected_gts; 691 struct wx *wx = NULL; 692 struct txgbe *txgbe; 693 694 u16 eeprom_verh = 0, eeprom_verl = 0, offset = 0; 695 u16 eeprom_cfg_blkh = 0, eeprom_cfg_blkl = 0; 696 u16 build = 0, major = 0, patch = 0; 697 u32 etrack_id = 0; 698 699 err = pci_enable_device_mem(pdev); 700 if (err) 701 return err; 702 703 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 704 if (err) { 705 dev_err(&pdev->dev, 706 "No usable DMA configuration, aborting\n"); 707 goto err_pci_disable_dev; 708 } 709 710 err = pci_request_selected_regions(pdev, 711 pci_select_bars(pdev, IORESOURCE_MEM), 712 txgbe_driver_name); 713 if (err) { 714 dev_err(&pdev->dev, 715 "pci_request_selected_regions failed 0x%x\n", err); 716 goto err_pci_disable_dev; 717 } 718 719 pci_set_master(pdev); 720 721 netdev = devm_alloc_etherdev_mqs(&pdev->dev, 722 sizeof(struct wx), 723 TXGBE_MAX_TX_QUEUES, 724 TXGBE_MAX_RX_QUEUES); 725 if (!netdev) { 726 err = -ENOMEM; 727 goto err_pci_release_regions; 728 } 729 730 SET_NETDEV_DEV(netdev, &pdev->dev); 731 732 wx = netdev_priv(netdev); 733 wx->netdev = netdev; 734 wx->pdev = pdev; 735 736 wx->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; 737 738 wx->hw_addr = devm_ioremap(&pdev->dev, 739 pci_resource_start(pdev, 0), 740 pci_resource_len(pdev, 0)); 741 if (!wx->hw_addr) { 742 err = -EIO; 743 goto err_pci_release_regions; 744 } 745 746 /* The sapphire supports up to 63 VFs per pf, but physical 747 * function also need one pool for basic networking. 748 */ 749 pci_sriov_set_totalvfs(pdev, TXGBE_MAX_VFS_DRV_LIMIT); 750 wx->driver_name = txgbe_driver_name; 751 txgbe_set_ethtool_ops(netdev); 752 netdev->netdev_ops = &txgbe_netdev_ops; 753 netdev->udp_tunnel_nic_info = &txgbe_udp_tunnels; 754 755 /* setup the private structure */ 756 err = txgbe_sw_init(wx); 757 if (err) 758 goto err_pci_release_regions; 759 760 /* check if flash load is done after hw power up */ 761 err = wx_check_flash_load(wx, TXGBE_SPI_ILDR_STATUS_PERST); 762 if (err) 763 goto err_free_mac_table; 764 err = wx_check_flash_load(wx, TXGBE_SPI_ILDR_STATUS_PWRRST); 765 if (err) 766 goto err_free_mac_table; 767 768 err = wx_mng_present(wx); 769 if (err) { 770 dev_err(&pdev->dev, "Management capability is not present\n"); 771 goto err_free_mac_table; 772 } 773 774 err = txgbe_reset_hw(wx); 775 if (err) { 776 dev_err(&pdev->dev, "HW Init failed: %d\n", err); 777 goto err_free_mac_table; 778 } 779 780 netdev->features = NETIF_F_SG | 781 NETIF_F_TSO | 782 NETIF_F_TSO6 | 783 NETIF_F_RXHASH | 784 NETIF_F_RXCSUM | 785 NETIF_F_HW_CSUM; 786 787 netdev->gso_partial_features = NETIF_F_GSO_ENCAP_ALL; 788 netdev->features |= netdev->gso_partial_features; 789 netdev->features |= NETIF_F_SCTP_CRC; 790 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 791 netdev->hw_enc_features |= netdev->vlan_features; 792 netdev->features |= NETIF_F_VLAN_FEATURES; 793 /* copy netdev features into list of user selectable features */ 794 netdev->hw_features |= netdev->features | NETIF_F_RXALL; 795 netdev->hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC; 796 netdev->features |= NETIF_F_HIGHDMA; 797 netdev->hw_features |= NETIF_F_GRO; 798 netdev->features |= NETIF_F_GRO; 799 netdev->hw_features |= NETIF_F_LRO; 800 netdev->features |= NETIF_F_LRO; 801 netdev->features |= NETIF_F_RX_UDP_TUNNEL_PORT; 802 803 netdev->priv_flags |= IFF_UNICAST_FLT; 804 netdev->priv_flags |= IFF_SUPP_NOFCS; 805 netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 806 807 netdev->min_mtu = ETH_MIN_MTU; 808 netdev->max_mtu = WX_MAX_JUMBO_FRAME_SIZE - 809 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 810 811 /* make sure the EEPROM is good */ 812 err = txgbe_validate_eeprom_checksum(wx, NULL); 813 if (err != 0) { 814 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); 815 wr32(wx, WX_MIS_RST, WX_MIS_RST_SW_RST); 816 err = -EIO; 817 goto err_free_mac_table; 818 } 819 820 eth_hw_addr_set(netdev, wx->mac.perm_addr); 821 wx_mac_set_default_filter(wx, wx->mac.perm_addr); 822 823 txgbe_init_service(wx); 824 825 err = wx_init_interrupt_scheme(wx); 826 if (err) 827 goto err_cancel_service; 828 829 /* Save off EEPROM version number and Option Rom version which 830 * together make a unique identify for the eeprom 831 */ 832 wx_read_ee_hostif(wx, 833 wx->eeprom.sw_region_offset + TXGBE_EEPROM_VERSION_H, 834 &eeprom_verh); 835 wx_read_ee_hostif(wx, 836 wx->eeprom.sw_region_offset + TXGBE_EEPROM_VERSION_L, 837 &eeprom_verl); 838 etrack_id = (eeprom_verh << 16) | eeprom_verl; 839 840 wx_read_ee_hostif(wx, 841 wx->eeprom.sw_region_offset + TXGBE_ISCSI_BOOT_CONFIG, 842 &offset); 843 844 /* Make sure offset to SCSI block is valid */ 845 if (!(offset == 0x0) && !(offset == 0xffff)) { 846 wx_read_ee_hostif(wx, offset + 0x84, &eeprom_cfg_blkh); 847 wx_read_ee_hostif(wx, offset + 0x83, &eeprom_cfg_blkl); 848 849 /* Only display Option Rom if exist */ 850 if (eeprom_cfg_blkl && eeprom_cfg_blkh) { 851 major = eeprom_cfg_blkl >> 8; 852 build = (eeprom_cfg_blkl << 8) | (eeprom_cfg_blkh >> 8); 853 patch = eeprom_cfg_blkh & 0x00ff; 854 855 snprintf(wx->eeprom_id, sizeof(wx->eeprom_id), 856 "0x%08x, %d.%d.%d", etrack_id, major, build, 857 patch); 858 } else { 859 snprintf(wx->eeprom_id, sizeof(wx->eeprom_id), 860 "0x%08x", etrack_id); 861 } 862 } else { 863 snprintf(wx->eeprom_id, sizeof(wx->eeprom_id), 864 "0x%08x", etrack_id); 865 } 866 867 if (etrack_id < 0x20010) 868 dev_warn(&pdev->dev, "Please upgrade the firmware to 0x20010 or above.\n"); 869 870 err = txgbe_test_hostif(wx); 871 if (err != 0) { 872 dev_err(&pdev->dev, "Mismatched Firmware version\n"); 873 err = -EIO; 874 goto err_release_hw; 875 } 876 877 txgbe = devm_kzalloc(&pdev->dev, sizeof(*txgbe), GFP_KERNEL); 878 if (!txgbe) { 879 err = -ENOMEM; 880 goto err_release_hw; 881 } 882 883 txgbe->wx = wx; 884 wx->priv = txgbe; 885 886 txgbe_init_fdir(txgbe); 887 888 err = txgbe_init_phy(txgbe); 889 if (err) 890 goto err_release_hw; 891 892 err = register_netdev(netdev); 893 if (err) 894 goto err_remove_phy; 895 896 pci_set_drvdata(pdev, wx); 897 898 netif_tx_stop_all_queues(netdev); 899 900 /* calculate the expected PCIe bandwidth required for optimal 901 * performance. Note that some older parts will never have enough 902 * bandwidth due to being older generation PCIe parts. We clamp these 903 * parts to ensure that no warning is displayed, as this could confuse 904 * users otherwise. 905 */ 906 expected_gts = txgbe_enumerate_functions(wx) * 10; 907 908 /* don't check link if we failed to enumerate functions */ 909 if (expected_gts > 0) 910 txgbe_check_minimum_link(wx); 911 else 912 dev_warn(&pdev->dev, "Failed to enumerate PF devices.\n"); 913 914 return 0; 915 916 err_remove_phy: 917 txgbe_remove_phy(txgbe); 918 err_release_hw: 919 wx_clear_interrupt_scheme(wx); 920 wx_control_hw(wx, false); 921 err_cancel_service: 922 timer_delete_sync(&wx->service_timer); 923 cancel_work_sync(&wx->service_task); 924 err_free_mac_table: 925 kfree(wx->rss_key); 926 kfree(wx->mac_table); 927 err_pci_release_regions: 928 pci_release_selected_regions(pdev, 929 pci_select_bars(pdev, IORESOURCE_MEM)); 930 err_pci_disable_dev: 931 pci_disable_device(pdev); 932 return err; 933 } 934 935 /** 936 * txgbe_remove - Device Removal Routine 937 * @pdev: PCI device information struct 938 * 939 * txgbe_remove is called by the PCI subsystem to alert the driver 940 * that it should release a PCI device. The could be caused by a 941 * Hot-Plug event, or because the driver is going to be removed from 942 * memory. 943 **/ 944 static void txgbe_remove(struct pci_dev *pdev) 945 { 946 struct wx *wx = pci_get_drvdata(pdev); 947 struct txgbe *txgbe = wx->priv; 948 struct net_device *netdev; 949 950 netdev = wx->netdev; 951 wx_disable_sriov(wx); 952 unregister_netdev(netdev); 953 954 timer_shutdown_sync(&wx->service_timer); 955 cancel_work_sync(&wx->service_task); 956 957 txgbe_remove_phy(txgbe); 958 wx_free_isb_resources(wx); 959 960 pci_release_selected_regions(pdev, 961 pci_select_bars(pdev, IORESOURCE_MEM)); 962 963 kfree(wx->rss_key); 964 kfree(wx->mac_table); 965 wx_clear_interrupt_scheme(wx); 966 967 pci_disable_device(pdev); 968 } 969 970 static struct pci_driver txgbe_driver = { 971 .name = txgbe_driver_name, 972 .id_table = txgbe_pci_tbl, 973 .probe = txgbe_probe, 974 .remove = txgbe_remove, 975 .shutdown = txgbe_shutdown, 976 .sriov_configure = wx_pci_sriov_configure, 977 }; 978 979 module_pci_driver(txgbe_driver); 980 981 MODULE_DEVICE_TABLE(pci, txgbe_pci_tbl); 982 MODULE_AUTHOR("Beijing WangXun Technology Co., Ltd, <software@trustnetic.com>"); 983 MODULE_DESCRIPTION("WangXun(R) 10/25/40 Gigabit PCI Express Network Driver"); 984 MODULE_LICENSE("GPL"); 985