1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __QCOM_TSENS_H__
7 #define __QCOM_TSENS_H__
8 
9 #define NO_PT_CALIB		0x0
10 #define ONE_PT_CALIB		0x1
11 #define ONE_PT_CALIB2		0x2
12 #define TWO_PT_CALIB		0x3
13 #define ONE_PT_CALIB2_NO_OFFSET	0x6
14 #define TWO_PT_CALIB_NO_OFFSET	0x7
15 #define CAL_DEGC_PT1		30
16 #define CAL_DEGC_PT2		120
17 #define SLOPE_FACTOR		1000
18 #define SLOPE_DEFAULT		3200
19 #define TIMEOUT_US		100
20 #define THRESHOLD_MAX_ADC_CODE	0x3ff
21 #define THRESHOLD_MIN_ADC_CODE	0x0
22 
23 #define MAX_SENSORS 16
24 
25 #include <linux/interrupt.h>
26 #include <linux/thermal.h>
27 #include <linux/regmap.h>
28 #include <linux/slab.h>
29 
30 struct tsens_priv;
31 
32 /* IP version numbers in ascending order */
33 enum tsens_ver {
34 	VER_0 = 0,
35 	VER_0_1,
36 	VER_1_X,
37 	VER_2_X,
38 	VER_2_X_NO_RPM,
39 };
40 
41 enum tsens_irq_type {
42 	LOWER,
43 	UPPER,
44 	CRITICAL,
45 };
46 
47 /**
48  * struct tsens_sensor - data for each sensor connected to the tsens device
49  * @priv: tsens device instance that this sensor is connected to
50  * @tzd: pointer to the thermal zone that this sensor is in
51  * @offset: offset of temperature adjustment curve
52  * @hw_id: HW ID can be used in case of platform-specific IDs
53  * @slope: slope of temperature adjustment curve
54  * @status: 8960-specific variable to track 8960 and 8660 status register offset
55  */
56 struct tsens_sensor {
57 	struct tsens_priv		*priv;
58 	struct thermal_zone_device	*tzd;
59 	int				offset;
60 	unsigned int			hw_id;
61 	int				slope;
62 	u32				status;
63 	int				p1_calib_offset;
64 	int				p2_calib_offset;
65 };
66 
67 /**
68  * struct tsens_ops - operations as supported by the tsens device
69  * @init: Function to initialize the tsens device
70  * @calibrate: Function to calibrate the tsens device
71  * @get_temp: Function which returns the temp in millidegC
72  * @enable: Function to enable (clocks/power) tsens device
73  * @disable: Function to disable the tsens device
74  * @suspend: Function to suspend the tsens device
75  * @resume: Function to resume the tsens device
76  */
77 struct tsens_ops {
78 	/* mandatory callbacks */
79 	int (*init)(struct tsens_priv *priv);
80 	int (*calibrate)(struct tsens_priv *priv);
81 	int (*get_temp)(const struct tsens_sensor *s, int *temp);
82 	/* optional callbacks */
83 	int (*enable)(struct tsens_priv *priv, int i);
84 	void (*disable)(struct tsens_priv *priv);
85 	int (*suspend)(struct tsens_priv *priv);
86 	int (*resume)(struct tsens_priv *priv);
87 };
88 
89 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
90 	[_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),	\
91 	[_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
92 	[_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
93 	[_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
94 	[_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
95 	[_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
96 	[_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
97 	[_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
98 	[_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
99 	[_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
100 	[_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)
101 
102 #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \
103 	[_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),	\
104 	[_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
105 	[_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
106 	[_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
107 	[_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
108 	[_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
109 	[_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
110 	[_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
111 	[_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
112 	[_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
113 	[_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \
114 	[_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \
115 	[_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \
116 	[_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \
117 	[_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
118 	[_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
119 
120 #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset)		\
121 	[_name##_##0]  = REG_FIELD(_offset,  0,  0),		\
122 	[_name##_##1]  = REG_FIELD(_offset,  1,  1),	\
123 	[_name##_##2]  = REG_FIELD(_offset,  2,  2),	\
124 	[_name##_##3]  = REG_FIELD(_offset,  3,  3),	\
125 	[_name##_##4]  = REG_FIELD(_offset,  4,  4),	\
126 	[_name##_##5]  = REG_FIELD(_offset,  5,  5),	\
127 	[_name##_##6]  = REG_FIELD(_offset,  6,  6),	\
128 	[_name##_##7]  = REG_FIELD(_offset,  7,  7),	\
129 	[_name##_##8]  = REG_FIELD(_offset,  8,  8),	\
130 	[_name##_##9]  = REG_FIELD(_offset,  9,  9),	\
131 	[_name##_##10] = REG_FIELD(_offset, 10, 10),	\
132 	[_name##_##11] = REG_FIELD(_offset, 11, 11),	\
133 	[_name##_##12] = REG_FIELD(_offset, 12, 12),	\
134 	[_name##_##13] = REG_FIELD(_offset, 13, 13),	\
135 	[_name##_##14] = REG_FIELD(_offset, 14, 14),	\
136 	[_name##_##15] = REG_FIELD(_offset, 15, 15)
137 
138 #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset)		\
139 	[_name##_##0]  = REG_FIELD(_offset, 16, 16),		\
140 	[_name##_##1]  = REG_FIELD(_offset, 17, 17),	\
141 	[_name##_##2]  = REG_FIELD(_offset, 18, 18),	\
142 	[_name##_##3]  = REG_FIELD(_offset, 19, 19),	\
143 	[_name##_##4]  = REG_FIELD(_offset, 20, 20),	\
144 	[_name##_##5]  = REG_FIELD(_offset, 21, 21),	\
145 	[_name##_##6]  = REG_FIELD(_offset, 22, 22),	\
146 	[_name##_##7]  = REG_FIELD(_offset, 23, 23),	\
147 	[_name##_##8]  = REG_FIELD(_offset, 24, 24),	\
148 	[_name##_##9]  = REG_FIELD(_offset, 25, 25),	\
149 	[_name##_##10] = REG_FIELD(_offset, 26, 26),	\
150 	[_name##_##11] = REG_FIELD(_offset, 27, 27),	\
151 	[_name##_##12] = REG_FIELD(_offset, 28, 28),	\
152 	[_name##_##13] = REG_FIELD(_offset, 29, 29),	\
153 	[_name##_##14] = REG_FIELD(_offset, 30, 30),	\
154 	[_name##_##15] = REG_FIELD(_offset, 31, 31)
155 
156 /*
157  * reg_field IDs to use as an index into an array
158  * If you change the order of the entries, check the devm_regmap_field_alloc()
159  * calls in init_common()
160  */
161 enum regfield_ids {
162 	/* ----- SROT ------ */
163 	/* HW_VER */
164 	VER_MAJOR,
165 	VER_MINOR,
166 	VER_STEP,
167 	/* CTRL_OFFSET */
168 	TSENS_EN,
169 	TSENS_SW_RST,
170 	SENSOR_EN,
171 	CODE_OR_TEMP,
172 	MAIN_MEASURE_PERIOD,
173 
174 	/* ----- TM ------ */
175 	/* TRDY */
176 	TRDY,
177 	/* INTERRUPT ENABLE */
178 	INT_EN,	/* v2+ has separate enables for crit, upper and lower irq */
179 	/* STATUS */
180 	LAST_TEMP_0,	/* Last temperature reading */
181 	LAST_TEMP_1,
182 	LAST_TEMP_2,
183 	LAST_TEMP_3,
184 	LAST_TEMP_4,
185 	LAST_TEMP_5,
186 	LAST_TEMP_6,
187 	LAST_TEMP_7,
188 	LAST_TEMP_8,
189 	LAST_TEMP_9,
190 	LAST_TEMP_10,
191 	LAST_TEMP_11,
192 	LAST_TEMP_12,
193 	LAST_TEMP_13,
194 	LAST_TEMP_14,
195 	LAST_TEMP_15,
196 	VALID_0,		/* VALID reading or not */
197 	VALID_1,
198 	VALID_2,
199 	VALID_3,
200 	VALID_4,
201 	VALID_5,
202 	VALID_6,
203 	VALID_7,
204 	VALID_8,
205 	VALID_9,
206 	VALID_10,
207 	VALID_11,
208 	VALID_12,
209 	VALID_13,
210 	VALID_14,
211 	VALID_15,
212 	LOWER_STATUS_0,	/* LOWER threshold violated */
213 	LOWER_STATUS_1,
214 	LOWER_STATUS_2,
215 	LOWER_STATUS_3,
216 	LOWER_STATUS_4,
217 	LOWER_STATUS_5,
218 	LOWER_STATUS_6,
219 	LOWER_STATUS_7,
220 	LOWER_STATUS_8,
221 	LOWER_STATUS_9,
222 	LOWER_STATUS_10,
223 	LOWER_STATUS_11,
224 	LOWER_STATUS_12,
225 	LOWER_STATUS_13,
226 	LOWER_STATUS_14,
227 	LOWER_STATUS_15,
228 	LOW_INT_STATUS_0,	/* LOWER interrupt status */
229 	LOW_INT_STATUS_1,
230 	LOW_INT_STATUS_2,
231 	LOW_INT_STATUS_3,
232 	LOW_INT_STATUS_4,
233 	LOW_INT_STATUS_5,
234 	LOW_INT_STATUS_6,
235 	LOW_INT_STATUS_7,
236 	LOW_INT_STATUS_8,
237 	LOW_INT_STATUS_9,
238 	LOW_INT_STATUS_10,
239 	LOW_INT_STATUS_11,
240 	LOW_INT_STATUS_12,
241 	LOW_INT_STATUS_13,
242 	LOW_INT_STATUS_14,
243 	LOW_INT_STATUS_15,
244 	LOW_INT_CLEAR_0,	/* LOWER interrupt clear */
245 	LOW_INT_CLEAR_1,
246 	LOW_INT_CLEAR_2,
247 	LOW_INT_CLEAR_3,
248 	LOW_INT_CLEAR_4,
249 	LOW_INT_CLEAR_5,
250 	LOW_INT_CLEAR_6,
251 	LOW_INT_CLEAR_7,
252 	LOW_INT_CLEAR_8,
253 	LOW_INT_CLEAR_9,
254 	LOW_INT_CLEAR_10,
255 	LOW_INT_CLEAR_11,
256 	LOW_INT_CLEAR_12,
257 	LOW_INT_CLEAR_13,
258 	LOW_INT_CLEAR_14,
259 	LOW_INT_CLEAR_15,
260 	LOW_INT_MASK_0,	/* LOWER interrupt mask */
261 	LOW_INT_MASK_1,
262 	LOW_INT_MASK_2,
263 	LOW_INT_MASK_3,
264 	LOW_INT_MASK_4,
265 	LOW_INT_MASK_5,
266 	LOW_INT_MASK_6,
267 	LOW_INT_MASK_7,
268 	LOW_INT_MASK_8,
269 	LOW_INT_MASK_9,
270 	LOW_INT_MASK_10,
271 	LOW_INT_MASK_11,
272 	LOW_INT_MASK_12,
273 	LOW_INT_MASK_13,
274 	LOW_INT_MASK_14,
275 	LOW_INT_MASK_15,
276 	LOW_THRESH_0,		/* LOWER threshold values */
277 	LOW_THRESH_1,
278 	LOW_THRESH_2,
279 	LOW_THRESH_3,
280 	LOW_THRESH_4,
281 	LOW_THRESH_5,
282 	LOW_THRESH_6,
283 	LOW_THRESH_7,
284 	LOW_THRESH_8,
285 	LOW_THRESH_9,
286 	LOW_THRESH_10,
287 	LOW_THRESH_11,
288 	LOW_THRESH_12,
289 	LOW_THRESH_13,
290 	LOW_THRESH_14,
291 	LOW_THRESH_15,
292 	UPPER_STATUS_0,	/* UPPER threshold violated */
293 	UPPER_STATUS_1,
294 	UPPER_STATUS_2,
295 	UPPER_STATUS_3,
296 	UPPER_STATUS_4,
297 	UPPER_STATUS_5,
298 	UPPER_STATUS_6,
299 	UPPER_STATUS_7,
300 	UPPER_STATUS_8,
301 	UPPER_STATUS_9,
302 	UPPER_STATUS_10,
303 	UPPER_STATUS_11,
304 	UPPER_STATUS_12,
305 	UPPER_STATUS_13,
306 	UPPER_STATUS_14,
307 	UPPER_STATUS_15,
308 	UP_INT_STATUS_0,	/* UPPER interrupt status */
309 	UP_INT_STATUS_1,
310 	UP_INT_STATUS_2,
311 	UP_INT_STATUS_3,
312 	UP_INT_STATUS_4,
313 	UP_INT_STATUS_5,
314 	UP_INT_STATUS_6,
315 	UP_INT_STATUS_7,
316 	UP_INT_STATUS_8,
317 	UP_INT_STATUS_9,
318 	UP_INT_STATUS_10,
319 	UP_INT_STATUS_11,
320 	UP_INT_STATUS_12,
321 	UP_INT_STATUS_13,
322 	UP_INT_STATUS_14,
323 	UP_INT_STATUS_15,
324 	UP_INT_CLEAR_0,	/* UPPER interrupt clear */
325 	UP_INT_CLEAR_1,
326 	UP_INT_CLEAR_2,
327 	UP_INT_CLEAR_3,
328 	UP_INT_CLEAR_4,
329 	UP_INT_CLEAR_5,
330 	UP_INT_CLEAR_6,
331 	UP_INT_CLEAR_7,
332 	UP_INT_CLEAR_8,
333 	UP_INT_CLEAR_9,
334 	UP_INT_CLEAR_10,
335 	UP_INT_CLEAR_11,
336 	UP_INT_CLEAR_12,
337 	UP_INT_CLEAR_13,
338 	UP_INT_CLEAR_14,
339 	UP_INT_CLEAR_15,
340 	UP_INT_MASK_0,		/* UPPER interrupt mask */
341 	UP_INT_MASK_1,
342 	UP_INT_MASK_2,
343 	UP_INT_MASK_3,
344 	UP_INT_MASK_4,
345 	UP_INT_MASK_5,
346 	UP_INT_MASK_6,
347 	UP_INT_MASK_7,
348 	UP_INT_MASK_8,
349 	UP_INT_MASK_9,
350 	UP_INT_MASK_10,
351 	UP_INT_MASK_11,
352 	UP_INT_MASK_12,
353 	UP_INT_MASK_13,
354 	UP_INT_MASK_14,
355 	UP_INT_MASK_15,
356 	UP_THRESH_0,		/* UPPER threshold values */
357 	UP_THRESH_1,
358 	UP_THRESH_2,
359 	UP_THRESH_3,
360 	UP_THRESH_4,
361 	UP_THRESH_5,
362 	UP_THRESH_6,
363 	UP_THRESH_7,
364 	UP_THRESH_8,
365 	UP_THRESH_9,
366 	UP_THRESH_10,
367 	UP_THRESH_11,
368 	UP_THRESH_12,
369 	UP_THRESH_13,
370 	UP_THRESH_14,
371 	UP_THRESH_15,
372 	CRITICAL_STATUS_0,	/* CRITICAL threshold violated */
373 	CRITICAL_STATUS_1,
374 	CRITICAL_STATUS_2,
375 	CRITICAL_STATUS_3,
376 	CRITICAL_STATUS_4,
377 	CRITICAL_STATUS_5,
378 	CRITICAL_STATUS_6,
379 	CRITICAL_STATUS_7,
380 	CRITICAL_STATUS_8,
381 	CRITICAL_STATUS_9,
382 	CRITICAL_STATUS_10,
383 	CRITICAL_STATUS_11,
384 	CRITICAL_STATUS_12,
385 	CRITICAL_STATUS_13,
386 	CRITICAL_STATUS_14,
387 	CRITICAL_STATUS_15,
388 	CRIT_INT_STATUS_0,	/* CRITICAL interrupt status */
389 	CRIT_INT_STATUS_1,
390 	CRIT_INT_STATUS_2,
391 	CRIT_INT_STATUS_3,
392 	CRIT_INT_STATUS_4,
393 	CRIT_INT_STATUS_5,
394 	CRIT_INT_STATUS_6,
395 	CRIT_INT_STATUS_7,
396 	CRIT_INT_STATUS_8,
397 	CRIT_INT_STATUS_9,
398 	CRIT_INT_STATUS_10,
399 	CRIT_INT_STATUS_11,
400 	CRIT_INT_STATUS_12,
401 	CRIT_INT_STATUS_13,
402 	CRIT_INT_STATUS_14,
403 	CRIT_INT_STATUS_15,
404 	CRIT_INT_CLEAR_0,	/* CRITICAL interrupt clear */
405 	CRIT_INT_CLEAR_1,
406 	CRIT_INT_CLEAR_2,
407 	CRIT_INT_CLEAR_3,
408 	CRIT_INT_CLEAR_4,
409 	CRIT_INT_CLEAR_5,
410 	CRIT_INT_CLEAR_6,
411 	CRIT_INT_CLEAR_7,
412 	CRIT_INT_CLEAR_8,
413 	CRIT_INT_CLEAR_9,
414 	CRIT_INT_CLEAR_10,
415 	CRIT_INT_CLEAR_11,
416 	CRIT_INT_CLEAR_12,
417 	CRIT_INT_CLEAR_13,
418 	CRIT_INT_CLEAR_14,
419 	CRIT_INT_CLEAR_15,
420 	CRIT_INT_MASK_0,	/* CRITICAL interrupt mask */
421 	CRIT_INT_MASK_1,
422 	CRIT_INT_MASK_2,
423 	CRIT_INT_MASK_3,
424 	CRIT_INT_MASK_4,
425 	CRIT_INT_MASK_5,
426 	CRIT_INT_MASK_6,
427 	CRIT_INT_MASK_7,
428 	CRIT_INT_MASK_8,
429 	CRIT_INT_MASK_9,
430 	CRIT_INT_MASK_10,
431 	CRIT_INT_MASK_11,
432 	CRIT_INT_MASK_12,
433 	CRIT_INT_MASK_13,
434 	CRIT_INT_MASK_14,
435 	CRIT_INT_MASK_15,
436 	CRIT_THRESH_0,		/* CRITICAL threshold values */
437 	CRIT_THRESH_1,
438 	CRIT_THRESH_2,
439 	CRIT_THRESH_3,
440 	CRIT_THRESH_4,
441 	CRIT_THRESH_5,
442 	CRIT_THRESH_6,
443 	CRIT_THRESH_7,
444 	CRIT_THRESH_8,
445 	CRIT_THRESH_9,
446 	CRIT_THRESH_10,
447 	CRIT_THRESH_11,
448 	CRIT_THRESH_12,
449 	CRIT_THRESH_13,
450 	CRIT_THRESH_14,
451 	CRIT_THRESH_15,
452 
453 	/* WATCHDOG */
454 	WDOG_BARK_STATUS,
455 	WDOG_BARK_CLEAR,
456 	WDOG_BARK_MASK,
457 	WDOG_BARK_COUNT,
458 
459 	/* CYCLE COMPLETION MONITOR */
460 	CC_MON_STATUS,
461 	CC_MON_CLEAR,
462 	CC_MON_MASK,
463 
464 	MIN_STATUS_0,		/* MIN threshold violated */
465 	MIN_STATUS_1,
466 	MIN_STATUS_2,
467 	MIN_STATUS_3,
468 	MIN_STATUS_4,
469 	MIN_STATUS_5,
470 	MIN_STATUS_6,
471 	MIN_STATUS_7,
472 	MIN_STATUS_8,
473 	MIN_STATUS_9,
474 	MIN_STATUS_10,
475 	MIN_STATUS_11,
476 	MIN_STATUS_12,
477 	MIN_STATUS_13,
478 	MIN_STATUS_14,
479 	MIN_STATUS_15,
480 	MAX_STATUS_0,		/* MAX threshold violated */
481 	MAX_STATUS_1,
482 	MAX_STATUS_2,
483 	MAX_STATUS_3,
484 	MAX_STATUS_4,
485 	MAX_STATUS_5,
486 	MAX_STATUS_6,
487 	MAX_STATUS_7,
488 	MAX_STATUS_8,
489 	MAX_STATUS_9,
490 	MAX_STATUS_10,
491 	MAX_STATUS_11,
492 	MAX_STATUS_12,
493 	MAX_STATUS_13,
494 	MAX_STATUS_14,
495 	MAX_STATUS_15,
496 
497 	/* Keep last */
498 	MAX_REGFIELDS
499 };
500 
501 /**
502  * struct tsens_features - Features supported by the IP
503  * @ver_major: Major number of IP version
504  * @crit_int: does the IP support critical interrupts?
505  * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
506  * @adc:      do the sensors only output adc code (instead of temperature)?
507  * @srot_split: does the IP neatly splits the register space into SROT and TM,
508  *              with SROT only being available to secure boot firmware?
509  * @has_watchdog: does this IP support watchdog functionality?
510  * @max_sensors: maximum sensors supported by this version of the IP
511  * @trip_min_temp: minimum trip temperature supported by this version of the IP
512  * @trip_max_temp: maximum trip temperature supported by this version of the IP
513  */
514 struct tsens_features {
515 	unsigned int ver_major;
516 	unsigned int crit_int:1;
517 	unsigned int combo_int:1;
518 	unsigned int adc:1;
519 	unsigned int srot_split:1;
520 	unsigned int has_watchdog:1;
521 	unsigned int max_sensors;
522 	int trip_min_temp;
523 	int trip_max_temp;
524 };
525 
526 /**
527  * struct tsens_plat_data - tsens compile-time platform data
528  * @num_sensors: Number of sensors supported by platform
529  * @ops: operations the tsens instance supports
530  * @hw_ids: Subset of sensors ids supported by platform, if not the first n
531  * @feat: features of the IP
532  * @fields: bitfield locations
533  */
534 struct tsens_plat_data {
535 	const u32		num_sensors;
536 	const struct tsens_ops	*ops;
537 	unsigned int		*hw_ids;
538 	struct tsens_features	*feat;
539 	const struct reg_field		*fields;
540 };
541 
542 /**
543  * struct tsens_context - Registers to be saved/restored across a context loss
544  * @threshold: Threshold register value
545  * @control: Control register value
546  */
547 struct tsens_context {
548 	int	threshold;
549 	int	control;
550 };
551 
552 /**
553  * struct tsens_priv - private data for each instance of the tsens IP
554  * @dev: pointer to struct device
555  * @num_sensors: number of sensors enabled on this device
556  * @tm_map: pointer to TM register address space
557  * @srot_map: pointer to SROT register address space
558  * @tm_offset: deal with old device trees that don't address TM and SROT
559  *             address space separately
560  * @ul_lock: lock while processing upper/lower threshold interrupts
561  * @crit_lock: lock while processing critical threshold interrupts
562  * @rf: array of regmap_fields used to store value of the field
563  * @ctx: registers to be saved and restored during suspend/resume
564  * @feat: features of the IP
565  * @fields: bitfield locations
566  * @ops: pointer to list of callbacks supported by this device
567  * @debug_root: pointer to debugfs dentry for all tsens
568  * @debug: pointer to debugfs dentry for tsens controller
569  * @sensor: list of sensors attached to this device
570  */
571 struct tsens_priv {
572 	struct device			*dev;
573 	u32				num_sensors;
574 	struct regmap			*tm_map;
575 	struct regmap			*srot_map;
576 	u32				tm_offset;
577 
578 	/* lock for upper/lower threshold interrupts */
579 	spinlock_t			ul_lock;
580 
581 	struct regmap_field		*rf[MAX_REGFIELDS];
582 	struct tsens_context		ctx;
583 	struct tsens_features		*feat;
584 	const struct reg_field		*fields;
585 	const struct tsens_ops		*ops;
586 
587 	struct dentry			*debug_root;
588 	struct dentry			*debug;
589 
590 	struct tsens_sensor		sensor[] __counted_by(num_sensors);
591 };
592 
593 /**
594  * struct tsens_single_value - internal representation of a single field inside nvmem calibration data
595  * @idx: index into the u32 data array
596  * @shift: the shift of the first bit in the value
597  * @blob: index of the data blob to use for this cell
598  */
599 struct tsens_single_value {
600 	u8 idx;
601 	u8 shift;
602 	u8 blob;
603 };
604 
605 /**
606  * struct tsens_legacy_calibration_format - description of calibration data used when parsing the legacy nvmem blob
607  * @base_len: the length of the base fields inside calibration data
608  * @base_shift: the shift to be applied to base data
609  * @sp_len: the length of the sN_pM fields inside calibration data
610  * @mode: descriptor of the calibration mode field
611  * @invalid: descriptor of the calibration mode invalid field
612  * @base: descriptors of the base0 and base1 fields
613  * @sp: descriptors of the sN_pM fields
614  */
615 struct tsens_legacy_calibration_format {
616 	unsigned int base_len;
617 	unsigned int base_shift;
618 	unsigned int sp_len;
619 	/* just two bits */
620 	struct tsens_single_value mode;
621 	/* on all platforms except 8974 invalid is the third bit of what downstream calls 'mode' */
622 	struct tsens_single_value invalid;
623 	struct tsens_single_value base[2];
624 	struct tsens_single_value sp[][2];
625 };
626 
627 char *qfprom_read(struct device *dev, const char *cname);
628 int tsens_read_calibration_legacy(struct tsens_priv *priv,
629 				  const struct tsens_legacy_calibration_format *format,
630 				  u32 *p1, u32 *p2,
631 				  u32 *cdata, u32 *csel);
632 int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup);
633 int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift);
634 int tsens_calibrate_common(struct tsens_priv *priv);
635 void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);
636 int init_common(struct tsens_priv *priv);
637 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
638 int get_temp_common(const struct tsens_sensor *s, int *temp);
639 #ifdef CONFIG_SUSPEND
640 int tsens_resume_common(struct tsens_priv *priv);
641 #else
642 #define tsens_resume_common            NULL
643 #endif
644 
645 /* TSENS target */
646 extern struct tsens_plat_data data_8960;
647 
648 /* TSENS v0.1 targets */
649 extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607;
650 
651 /* TSENS v1 targets */
652 extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956;
653 
654 /* TSENS v2 targets */
655 extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
656 extern const struct tsens_plat_data data_ipq5332, data_ipq5424;
657 
658 #endif /* __QCOM_TSENS_H__ */
659