1 /*
2 * S/390 virtual CPU header
3 *
4 * For details on the s390x architecture and used definitions (e.g.,
5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to
6 * the "z/Architecture Principles of Operations" - a.k.a. PoP.
7 *
8 * Copyright (c) 2009 Ulrich Hecht
9 * Copyright IBM Corp. 2012, 2018
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #ifndef S390X_CPU_H
26 #define S390X_CPU_H
27
28 #include "cpu-qom.h"
29 #include "cpu_models.h"
30 #include "exec/cpu-common.h"
31 #include "exec/cpu-defs.h"
32 #include "exec/cpu-interrupt.h"
33 #include "qemu/cpu-float.h"
34 #include "qapi/qapi-types-machine-common.h"
35
36 #define ELF_MACHINE_UNAME "S390X"
37
38 #define MMU_USER_IDX 0
39
40 #define S390_MAX_CPUS 248
41
42 #ifndef CONFIG_KVM
43 #define S390_ADAPTER_SUPPRESSIBLE 0x01
44 #else
45 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
46 #endif
47
48 typedef struct PSW {
49 uint64_t mask;
50 uint64_t addr;
51 } PSW;
52
53 typedef struct CPUArchState {
54 uint64_t regs[16]; /* GP registers */
55 /*
56 * The floating point registers are part of the vector registers.
57 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
58 */
59 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
60 uint32_t aregs[16]; /* access registers */
61 uint64_t gscb[4]; /* guarded storage control */
62 uint64_t etoken; /* etoken */
63 uint64_t etoken_extension; /* etoken extension */
64
65 uint64_t diag318_info;
66
67 /* Fields up to this point are not cleared by initial CPU reset */
68 struct {} start_initial_reset_fields;
69
70 uint32_t fpc; /* floating-point control register */
71 uint32_t cc_op;
72 bool bpbc; /* branch prediction blocking */
73
74 float_status fpu_status; /* passed to softfloat lib */
75
76 PSW psw;
77
78 S390CrashReason crash_reason;
79
80 uint64_t cc_src;
81 uint64_t cc_dst;
82 uint64_t cc_vr;
83
84 uint64_t ex_value;
85 uint64_t ex_target;
86
87 uint64_t __excp_addr;
88 uint64_t psa;
89
90 uint32_t int_pgm_code;
91 uint32_t int_pgm_ilen;
92
93 uint32_t int_svc_code;
94 uint32_t int_svc_ilen;
95
96 uint64_t per_address;
97 uint16_t per_perc_atmid;
98
99 uint64_t cregs[16]; /* control registers */
100
101 uint64_t ckc;
102 uint64_t cputm;
103 uint32_t todpr;
104
105 uint64_t pfault_token;
106 uint64_t pfault_compare;
107 uint64_t pfault_select;
108
109 uint64_t gbea;
110 uint64_t pp;
111
112 /* Fields up to this point are not cleared by normal CPU reset */
113 struct {} start_normal_reset_fields;
114 uint8_t riccb[64]; /* runtime instrumentation control */
115
116 int pending_int;
117 uint16_t external_call_addr;
118 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
119
120 #if !defined(CONFIG_USER_ONLY)
121 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */
122 int tlb_fill_exc; /* exception number seen during tlb_fill */
123 #endif
124
125 /* Fields up to this point are cleared by a CPU reset */
126 struct {} end_reset_fields;
127
128 #if !defined(CONFIG_USER_ONLY)
129 uint32_t core_id; /* PoP "CPU address", same as cpu_index */
130 int32_t socket_id;
131 int32_t book_id;
132 int32_t drawer_id;
133 bool dedicated;
134 S390CpuEntitlement entitlement; /* Used only for vertical polarization */
135 uint64_t cpuid;
136 #endif
137
138 QEMUTimer *tod_timer;
139
140 QEMUTimer *cpu_timer;
141
142 /*
143 * The cpu state represents the logical state of a cpu. In contrast to other
144 * architectures, there is a difference between a halt and a stop on s390.
145 * If all cpus are either stopped (including check stop) or in the disabled
146 * wait state, the vm can be shut down.
147 * The acceptable cpu_state values are defined in the CpuInfoS390State
148 * enum.
149 */
150 uint8_t cpu_state;
151
152 /* currently processed sigp order */
153 uint8_t sigp_order;
154
155 } CPUS390XState;
156
get_freg(CPUS390XState * cs,int nr)157 static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
158 {
159 return &cs->vregs[nr][0];
160 }
161
162 /**
163 * S390CPU:
164 * @env: #CPUS390XState.
165 *
166 * An S/390 CPU.
167 */
168 struct ArchCPU {
169 CPUState parent_obj;
170
171 CPUS390XState env;
172 S390CPUModel *model;
173 /* needed for live migration */
174 void *irqstate;
175 uint32_t irqstate_saved_size;
176 };
177
178 /**
179 * S390CPUClass:
180 * @parent_realize: The parent class' realize handler.
181 * @parent_phases: The parent class' reset phase handlers.
182 * @load_normal: Performs a load normal.
183 *
184 * An S/390 CPU model.
185 */
186 struct S390CPUClass {
187 CPUClass parent_class;
188
189 const S390CPUDef *cpu_def;
190 bool kvm_required;
191 bool is_static;
192 bool is_migration_safe;
193 const char *desc;
194
195 DeviceRealize parent_realize;
196 ResettablePhases parent_phases;
197 void (*load_normal)(CPUState *cpu);
198 };
199
200 #ifndef CONFIG_USER_ONLY
201 extern const VMStateDescription vmstate_s390_cpu;
202 #endif
203
204 /* distinguish between 24 bit and 31 bit addressing */
205 #define HIGH_ORDER_BIT 0x80000000
206
207 /* Interrupt Codes */
208 /* Program Interrupts */
209 #define PGM_OPERATION 0x0001
210 #define PGM_PRIVILEGED 0x0002
211 #define PGM_EXECUTE 0x0003
212 #define PGM_PROTECTION 0x0004
213 #define PGM_ADDRESSING 0x0005
214 #define PGM_SPECIFICATION 0x0006
215 #define PGM_DATA 0x0007
216 #define PGM_FIXPT_OVERFLOW 0x0008
217 #define PGM_FIXPT_DIVIDE 0x0009
218 #define PGM_DEC_OVERFLOW 0x000a
219 #define PGM_DEC_DIVIDE 0x000b
220 #define PGM_HFP_EXP_OVERFLOW 0x000c
221 #define PGM_HFP_EXP_UNDERFLOW 0x000d
222 #define PGM_HFP_SIGNIFICANCE 0x000e
223 #define PGM_HFP_DIVIDE 0x000f
224 #define PGM_SEGMENT_TRANS 0x0010
225 #define PGM_PAGE_TRANS 0x0011
226 #define PGM_TRANS_SPEC 0x0012
227 #define PGM_SPECIAL_OP 0x0013
228 #define PGM_OPERAND 0x0015
229 #define PGM_TRACE_TABLE 0x0016
230 #define PGM_VECTOR_PROCESSING 0x001b
231 #define PGM_SPACE_SWITCH 0x001c
232 #define PGM_HFP_SQRT 0x001d
233 #define PGM_PC_TRANS_SPEC 0x001f
234 #define PGM_AFX_TRANS 0x0020
235 #define PGM_ASX_TRANS 0x0021
236 #define PGM_LX_TRANS 0x0022
237 #define PGM_EX_TRANS 0x0023
238 #define PGM_PRIM_AUTH 0x0024
239 #define PGM_SEC_AUTH 0x0025
240 #define PGM_ALET_SPEC 0x0028
241 #define PGM_ALEN_SPEC 0x0029
242 #define PGM_ALE_SEQ 0x002a
243 #define PGM_ASTE_VALID 0x002b
244 #define PGM_ASTE_SEQ 0x002c
245 #define PGM_EXT_AUTH 0x002d
246 #define PGM_STACK_FULL 0x0030
247 #define PGM_STACK_EMPTY 0x0031
248 #define PGM_STACK_SPEC 0x0032
249 #define PGM_STACK_TYPE 0x0033
250 #define PGM_STACK_OP 0x0034
251 #define PGM_ASCE_TYPE 0x0038
252 #define PGM_REG_FIRST_TRANS 0x0039
253 #define PGM_REG_SEC_TRANS 0x003a
254 #define PGM_REG_THIRD_TRANS 0x003b
255 #define PGM_MONITOR 0x0040
256 #define PGM_PER 0x0080
257 #define PGM_CRYPTO 0x0119
258
259 /* External Interrupts */
260 #define EXT_INTERRUPT_KEY 0x0040
261 #define EXT_CLOCK_COMP 0x1004
262 #define EXT_CPU_TIMER 0x1005
263 #define EXT_MALFUNCTION 0x1200
264 #define EXT_EMERGENCY 0x1201
265 #define EXT_EXTERNAL_CALL 0x1202
266 #define EXT_ETR 0x1406
267 #define EXT_SERVICE 0x2401
268 #define EXT_VIRTIO 0x2603
269
270 /* PSW defines */
271 #undef PSW_MASK_PER
272 #undef PSW_MASK_UNUSED_2
273 #undef PSW_MASK_UNUSED_3
274 #undef PSW_MASK_DAT
275 #undef PSW_MASK_IO
276 #undef PSW_MASK_EXT
277 #undef PSW_MASK_KEY
278 #undef PSW_SHIFT_KEY
279 #undef PSW_MASK_MCHECK
280 #undef PSW_MASK_WAIT
281 #undef PSW_MASK_PSTATE
282 #undef PSW_MASK_ASC
283 #undef PSW_SHIFT_ASC
284 #undef PSW_MASK_CC
285 #undef PSW_MASK_PM
286 #undef PSW_MASK_RI
287 #undef PSW_SHIFT_MASK_PM
288 #undef PSW_MASK_64
289 #undef PSW_MASK_32
290 #undef PSW_MASK_ESA_ADDR
291
292 #define PSW_MASK_PER 0x4000000000000000ULL
293 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL
294 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL
295 #define PSW_MASK_DAT 0x0400000000000000ULL
296 #define PSW_MASK_IO 0x0200000000000000ULL
297 #define PSW_MASK_EXT 0x0100000000000000ULL
298 #define PSW_MASK_KEY 0x00F0000000000000ULL
299 #define PSW_SHIFT_KEY 52
300 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
301 #define PSW_MASK_MCHECK 0x0004000000000000ULL
302 #define PSW_MASK_WAIT 0x0002000000000000ULL
303 #define PSW_MASK_PSTATE 0x0001000000000000ULL
304 #define PSW_MASK_ASC 0x0000C00000000000ULL
305 #define PSW_SHIFT_ASC 46
306 #define PSW_MASK_CC 0x0000300000000000ULL
307 #define PSW_MASK_PM 0x00000F0000000000ULL
308 #define PSW_SHIFT_MASK_PM 40
309 #define PSW_MASK_RI 0x0000008000000000ULL
310 #define PSW_MASK_64 0x0000000100000000ULL
311 #define PSW_MASK_32 0x0000000080000000ULL
312 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
313 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
314 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL
315
316 #undef PSW_ASC_PRIMARY
317 #undef PSW_ASC_ACCREG
318 #undef PSW_ASC_SECONDARY
319 #undef PSW_ASC_HOME
320
321 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
322 #define PSW_ASC_ACCREG 0x0000400000000000ULL
323 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
324 #define PSW_ASC_HOME 0x0000C00000000000ULL
325
326 /* the address space values shifted */
327 #define AS_PRIMARY 0
328 #define AS_ACCREG 1
329 #define AS_SECONDARY 2
330 #define AS_HOME 3
331
332 /* tb flags */
333
334 #define FLAG_MASK_PSW_SHIFT 31
335 #define FLAG_MASK_32 0x00000001u
336 #define FLAG_MASK_64 0x00000002u
337 #define FLAG_MASK_AFP 0x00000004u
338 #define FLAG_MASK_VECTOR 0x00000008u
339 #define FLAG_MASK_ASC 0x00018000u
340 #define FLAG_MASK_PSTATE 0x00020000u
341 #define FLAG_MASK_PER_IFETCH_NULLIFY 0x01000000u
342 #define FLAG_MASK_DAT 0x08000000u
343 #define FLAG_MASK_PER_STORE_REAL 0x20000000u
344 #define FLAG_MASK_PER_IFETCH 0x40000000u
345 #define FLAG_MASK_PER_BRANCH 0x80000000u
346
347 QEMU_BUILD_BUG_ON(FLAG_MASK_32 != PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT);
348 QEMU_BUILD_BUG_ON(FLAG_MASK_64 != PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT);
349 QEMU_BUILD_BUG_ON(FLAG_MASK_ASC != PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT);
350 QEMU_BUILD_BUG_ON(FLAG_MASK_PSTATE != PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT);
351 QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT);
352
353 #define FLAG_MASK_PSW (FLAG_MASK_DAT | FLAG_MASK_PSTATE | \
354 FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
355 #define FLAG_MASK_CR9 (FLAG_MASK_PER_BRANCH | FLAG_MASK_PER_IFETCH)
356 #define FLAG_MASK_PER (FLAG_MASK_PER_BRANCH | \
357 FLAG_MASK_PER_IFETCH | \
358 FLAG_MASK_PER_IFETCH_NULLIFY | \
359 FLAG_MASK_PER_STORE_REAL)
360
361 /* Control register 0 bits */
362 #define CR0_LOWPROT 0x0000000010000000ULL
363 #define CR0_SECONDARY 0x0000000004000000ULL
364 #define CR0_EDAT 0x0000000000800000ULL
365 #define CR0_AFP 0x0000000000040000ULL
366 #define CR0_VECTOR 0x0000000000020000ULL
367 #define CR0_IEP 0x0000000000100000ULL
368 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
369 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
370 #define CR0_CKC_SC 0x0000000000000800ULL
371 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
372 #define CR0_SERVICE_SC 0x0000000000000200ULL
373
374 /* Control register 14 bits */
375 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
376
377 /* MMU */
378 #define MMU_PRIMARY_IDX 0
379 #define MMU_SECONDARY_IDX 1
380 #define MMU_HOME_IDX 2
381 #define MMU_REAL_IDX 3
382
s390x_env_mmu_index(CPUS390XState * env,bool ifetch)383 static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch)
384 {
385 #ifdef CONFIG_USER_ONLY
386 return MMU_USER_IDX;
387 #else
388 if (!(env->psw.mask & PSW_MASK_DAT)) {
389 return MMU_REAL_IDX;
390 }
391
392 if (ifetch) {
393 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
394 return MMU_HOME_IDX;
395 }
396 return MMU_PRIMARY_IDX;
397 }
398
399 switch (env->psw.mask & PSW_MASK_ASC) {
400 case PSW_ASC_PRIMARY:
401 return MMU_PRIMARY_IDX;
402 case PSW_ASC_SECONDARY:
403 return MMU_SECONDARY_IDX;
404 case PSW_ASC_HOME:
405 return MMU_HOME_IDX;
406 case PSW_ASC_ACCREG:
407 /* Fallthrough: access register mode is not yet supported */
408 default:
409 abort();
410 }
411 #endif
412 }
413
414 /* PER bits from control register 9 */
415 #define PER_CR9_EVENT_BRANCH 0x80000000
416 #define PER_CR9_EVENT_IFETCH 0x40000000
417 #define PER_CR9_EVENT_STORE 0x20000000
418 #define PER_CR9_EVENT_STORAGE_KEY_ALTERATION 0x10000000
419 #define PER_CR9_EVENT_STORE_REAL 0x08000000
420 #define PER_CR9_EVENT_ZERO_ADDRESS_DETECTION 0x04000000
421 #define PER_CR9_EVENT_TRANSACTION_END 0x02000000
422 #define PER_CR9_EVENT_IFETCH_NULLIFICATION 0x01000000
423 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
424 #define PER_CR9_CONTROL_TRANSACTION_SUPRESS 0x00400000
425 #define PER_CR9_CONTROL_STORAGE_ALTERATION 0x00200000
426
427 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_BRANCH != PER_CR9_EVENT_BRANCH);
428 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH != PER_CR9_EVENT_IFETCH);
429 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH_NULLIFY !=
430 PER_CR9_EVENT_IFETCH_NULLIFICATION);
431
432 /* PER bits from the PER CODE/ATMID/AI in lowcore */
433 #define PER_CODE_EVENT_BRANCH 0x8000
434 #define PER_CODE_EVENT_IFETCH 0x4000
435 #define PER_CODE_EVENT_STORE 0x2000
436 #define PER_CODE_EVENT_STORE_REAL 0x0800
437 #define PER_CODE_EVENT_NULLIFICATION 0x0100
438
439 #define EXCP_EXT 1 /* external interrupt */
440 #define EXCP_SVC 2 /* supervisor call (syscall) */
441 #define EXCP_PGM 3 /* program interruption */
442 #define EXCP_RESTART 4 /* restart interrupt */
443 #define EXCP_STOP 5 /* stop interrupt */
444 #define EXCP_IO 7 /* I/O interrupt */
445 #define EXCP_MCHK 8 /* machine check */
446
447 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
448 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
449 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
450 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
451 #define INTERRUPT_RESTART (1 << 7)
452 #define INTERRUPT_STOP (1 << 8)
453
454 /* Program Status Word. */
455 #define S390_PSWM_REGNUM 0
456 #define S390_PSWA_REGNUM 1
457 /* General Purpose Registers. */
458 #define S390_R0_REGNUM 2
459 #define S390_R1_REGNUM 3
460 #define S390_R2_REGNUM 4
461 #define S390_R3_REGNUM 5
462 #define S390_R4_REGNUM 6
463 #define S390_R5_REGNUM 7
464 #define S390_R6_REGNUM 8
465 #define S390_R7_REGNUM 9
466 #define S390_R8_REGNUM 10
467 #define S390_R9_REGNUM 11
468 #define S390_R10_REGNUM 12
469 #define S390_R11_REGNUM 13
470 #define S390_R12_REGNUM 14
471 #define S390_R13_REGNUM 15
472 #define S390_R14_REGNUM 16
473 #define S390_R15_REGNUM 17
474
setcc(S390CPU * cpu,uint64_t cc)475 static inline void setcc(S390CPU *cpu, uint64_t cc)
476 {
477 CPUS390XState *env = &cpu->env;
478
479 env->psw.mask &= ~(3ull << 44);
480 env->psw.mask |= (cc & 3) << 44;
481 env->cc_op = cc;
482 }
483
484 /* STSI */
485 #define STSI_R0_FC_MASK 0x00000000f0000000ULL
486 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL
487 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
488 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
489 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
490 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
491 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
492 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
493 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
494
495 /* Basic Machine Configuration */
496 typedef struct SysIB_111 {
497 uint8_t res1[32];
498 uint8_t manuf[16];
499 uint8_t type[4];
500 uint8_t res2[12];
501 uint8_t model[16];
502 uint8_t sequence[16];
503 uint8_t plant[4];
504 uint8_t res3[3996];
505 } SysIB_111;
506 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
507
508 /* Basic Machine CPU */
509 typedef struct SysIB_121 {
510 uint8_t res1[80];
511 uint8_t sequence[16];
512 uint8_t plant[4];
513 uint8_t res2[2];
514 uint16_t cpu_addr;
515 uint8_t res3[3992];
516 } SysIB_121;
517 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
518
519 /* Basic Machine CPUs */
520 typedef struct SysIB_122 {
521 uint8_t res1[32];
522 uint32_t capability;
523 uint16_t total_cpus;
524 uint16_t conf_cpus;
525 uint16_t standby_cpus;
526 uint16_t reserved_cpus;
527 uint16_t adjustments[2026];
528 } SysIB_122;
529 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
530
531 /* LPAR CPU */
532 typedef struct SysIB_221 {
533 uint8_t res1[80];
534 uint8_t sequence[16];
535 uint8_t plant[4];
536 uint16_t cpu_id;
537 uint16_t cpu_addr;
538 uint8_t res3[3992];
539 } SysIB_221;
540 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
541
542 /* LPAR CPUs */
543 typedef struct SysIB_222 {
544 uint8_t res1[32];
545 uint16_t lpar_num;
546 uint8_t res2;
547 uint8_t lcpuc;
548 uint16_t total_cpus;
549 uint16_t conf_cpus;
550 uint16_t standby_cpus;
551 uint16_t reserved_cpus;
552 uint8_t name[8];
553 uint32_t caf;
554 uint8_t res3[16];
555 uint16_t dedicated_cpus;
556 uint16_t shared_cpus;
557 uint8_t res4[4020];
558 } SysIB_222;
559 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
560
561 /* VM CPUs */
562 typedef struct SysIB_322 {
563 uint8_t res1[31];
564 uint8_t count;
565 struct {
566 uint8_t res2[4];
567 uint16_t total_cpus;
568 uint16_t conf_cpus;
569 uint16_t standby_cpus;
570 uint16_t reserved_cpus;
571 uint8_t name[8];
572 uint32_t caf;
573 uint8_t cpi[16];
574 uint8_t res5[3];
575 uint8_t ext_name_encoding;
576 uint32_t res3;
577 uint8_t uuid[16];
578 } vm[8];
579 uint8_t res4[1504];
580 uint8_t ext_names[8][256];
581 } SysIB_322;
582 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
583
584 /*
585 * Topology Magnitude fields (MAG) indicates the maximum number of
586 * topology list entries (TLE) at the corresponding nesting level.
587 */
588 #define S390_TOPOLOGY_MAG 6
589 #define S390_TOPOLOGY_MAG6 0
590 #define S390_TOPOLOGY_MAG5 1
591 #define S390_TOPOLOGY_MAG4 2
592 #define S390_TOPOLOGY_MAG3 3
593 #define S390_TOPOLOGY_MAG2 4
594 #define S390_TOPOLOGY_MAG1 5
595 /* Configuration topology */
596 typedef struct SysIB_151x {
597 uint8_t reserved0[2];
598 uint16_t length;
599 uint8_t mag[S390_TOPOLOGY_MAG];
600 uint8_t reserved1;
601 uint8_t mnest;
602 uint32_t reserved2;
603 char tle[];
604 } SysIB_151x;
605 QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16);
606
607 typedef union SysIB {
608 SysIB_111 sysib_111;
609 SysIB_121 sysib_121;
610 SysIB_122 sysib_122;
611 SysIB_221 sysib_221;
612 SysIB_222 sysib_222;
613 SysIB_322 sysib_322;
614 SysIB_151x sysib_151x;
615 } SysIB;
616 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
617
618 /*
619 * CPU Topology List provided by STSI with fc=15 provides a list
620 * of two different Topology List Entries (TLE) types to specify
621 * the topology hierarchy.
622 *
623 * - Container Topology List Entry
624 * Defines a container to contain other Topology List Entries
625 * of any type, nested containers or CPU.
626 * - CPU Topology List Entry
627 * Specifies the CPUs position, type, entitlement and polarization
628 * of the CPUs contained in the last container TLE.
629 *
630 * There can be theoretically up to five levels of containers, QEMU
631 * uses only three levels, the drawer's, book's and socket's level.
632 *
633 * A container with a nesting level (NL) greater than 1 can only
634 * contain another container of nesting level NL-1.
635 *
636 * A container of nesting level 1 (socket), contains as many CPU TLE
637 * as needed to describe the position and qualities of all CPUs inside
638 * the container.
639 * The qualities of a CPU are polarization, entitlement and type.
640 *
641 * The CPU TLE defines the position of the CPUs of identical qualities
642 * using a 64bits mask which first bit has its offset defined by
643 * the CPU address origin field of the CPU TLE like in:
644 * CPU address = origin * 64 + bit position within the mask
645 */
646 /* Container type Topology List Entry */
647 typedef struct SYSIBContainerListEntry {
648 uint8_t nl;
649 uint8_t reserved[6];
650 uint8_t id;
651 } SYSIBContainerListEntry;
652 QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry) != 8);
653
654 /* CPU type Topology List Entry */
655 typedef struct SysIBCPUListEntry {
656 uint8_t nl;
657 uint8_t reserved0[3];
658 #define SYSIB_TLE_POLARITY_MASK 0x03
659 #define SYSIB_TLE_DEDICATED 0x04
660 uint8_t flags;
661 uint8_t type;
662 uint16_t origin;
663 uint64_t mask;
664 } SysIBCPUListEntry;
665 QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry) != 16);
666
667 void insert_stsi_15_1_x(S390CPU *cpu, int sel2, uint64_t addr, uint8_t ar, uintptr_t ra);
668 void s390_cpu_topology_set_changed(bool changed);
669
670 /* MMU defines */
671 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
672 #define ASCE_SUBSPACE 0x200 /* subspace group control */
673 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */
674 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
675 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */
676 #define ASCE_REAL_SPACE 0x20 /* real space control */
677 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */
678 #define ASCE_TYPE_REGION1 0x0c /* region first table type */
679 #define ASCE_TYPE_REGION2 0x08 /* region second table type */
680 #define ASCE_TYPE_REGION3 0x04 /* region third table type */
681 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
682 #define ASCE_TABLE_LENGTH 0x03 /* region table length */
683
684 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL
685 #define REGION_ENTRY_P 0x0000000000000200ULL
686 #define REGION_ENTRY_TF 0x00000000000000c0ULL
687 #define REGION_ENTRY_I 0x0000000000000020ULL
688 #define REGION_ENTRY_TT 0x000000000000000cULL
689 #define REGION_ENTRY_TL 0x0000000000000003ULL
690
691 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL
692 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL
693 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL
694
695 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL
696 #define REGION3_ENTRY_AV 0x0000000000010000ULL
697 #define REGION3_ENTRY_ACC 0x000000000000f000ULL
698 #define REGION3_ENTRY_F 0x0000000000000800ULL
699 #define REGION3_ENTRY_FC 0x0000000000000400ULL
700 #define REGION3_ENTRY_IEP 0x0000000000000100ULL
701 #define REGION3_ENTRY_CR 0x0000000000000010ULL
702
703 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL
704 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL
705 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL
706 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL
707 #define SEGMENT_ENTRY_F 0x0000000000000800ULL
708 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL
709 #define SEGMENT_ENTRY_P 0x0000000000000200ULL
710 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL
711 #define SEGMENT_ENTRY_I 0x0000000000000020ULL
712 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL
713 #define SEGMENT_ENTRY_TT 0x000000000000000cULL
714
715 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL
716
717 #define PAGE_ENTRY_0 0x0000000000000800ULL
718 #define PAGE_ENTRY_I 0x0000000000000400ULL
719 #define PAGE_ENTRY_P 0x0000000000000200ULL
720 #define PAGE_ENTRY_IEP 0x0000000000000100ULL
721
722 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL
723 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL
724 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL
725 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL
726 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL
727
728 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
729 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
730 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
731 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
732 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
733
734 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62)
735 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51)
736 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40)
737 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29)
738
739 #define SK_C (0x1 << 1)
740 #define SK_R (0x1 << 2)
741 #define SK_F (0x1 << 3)
742 #define SK_ACC_MASK (0xf << 4)
743
744 /* SIGP order codes */
745 #define SIGP_SENSE 0x01
746 #define SIGP_EXTERNAL_CALL 0x02
747 #define SIGP_EMERGENCY 0x03
748 #define SIGP_START 0x04
749 #define SIGP_STOP 0x05
750 #define SIGP_RESTART 0x06
751 #define SIGP_STOP_STORE_STATUS 0x09
752 #define SIGP_INITIAL_CPU_RESET 0x0b
753 #define SIGP_CPU_RESET 0x0c
754 #define SIGP_SET_PREFIX 0x0d
755 #define SIGP_STORE_STATUS_ADDR 0x0e
756 #define SIGP_SET_ARCH 0x12
757 #define SIGP_COND_EMERGENCY 0x13
758 #define SIGP_SENSE_RUNNING 0x15
759 #define SIGP_STORE_ADTL_STATUS 0x17
760
761 /* SIGP condition codes */
762 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
763 #define SIGP_CC_STATUS_STORED 1
764 #define SIGP_CC_BUSY 2
765 #define SIGP_CC_NOT_OPERATIONAL 3
766
767 /* SIGP status bits */
768 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
769 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
770 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
771 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
772 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
773 #define SIGP_STAT_STOPPED 0x00000040UL
774 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
775 #define SIGP_STAT_CHECK_STOP 0x00000010UL
776 #define SIGP_STAT_INOPERATIVE 0x00000004UL
777 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
778 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
779
780 /* SIGP order code mask corresponding to bit positions 56-63 */
781 #define SIGP_ORDER_MASK 0x000000ff
782
783 /* machine check interruption code */
784
785 /* subclasses */
786 #define MCIC_SC_SD 0x8000000000000000ULL
787 #define MCIC_SC_PD 0x4000000000000000ULL
788 #define MCIC_SC_SR 0x2000000000000000ULL
789 #define MCIC_SC_CD 0x0800000000000000ULL
790 #define MCIC_SC_ED 0x0400000000000000ULL
791 #define MCIC_SC_DG 0x0100000000000000ULL
792 #define MCIC_SC_W 0x0080000000000000ULL
793 #define MCIC_SC_CP 0x0040000000000000ULL
794 #define MCIC_SC_SP 0x0020000000000000ULL
795 #define MCIC_SC_CK 0x0010000000000000ULL
796
797 /* subclass modifiers */
798 #define MCIC_SCM_B 0x0002000000000000ULL
799 #define MCIC_SCM_DA 0x0000000020000000ULL
800 #define MCIC_SCM_AP 0x0000000000080000ULL
801
802 /* storage errors */
803 #define MCIC_SE_SE 0x0000800000000000ULL
804 #define MCIC_SE_SC 0x0000400000000000ULL
805 #define MCIC_SE_KE 0x0000200000000000ULL
806 #define MCIC_SE_DS 0x0000100000000000ULL
807 #define MCIC_SE_IE 0x0000000080000000ULL
808
809 /* validity bits */
810 #define MCIC_VB_WP 0x0000080000000000ULL
811 #define MCIC_VB_MS 0x0000040000000000ULL
812 #define MCIC_VB_PM 0x0000020000000000ULL
813 #define MCIC_VB_IA 0x0000010000000000ULL
814 #define MCIC_VB_FA 0x0000008000000000ULL
815 #define MCIC_VB_VR 0x0000004000000000ULL
816 #define MCIC_VB_EC 0x0000002000000000ULL
817 #define MCIC_VB_FP 0x0000001000000000ULL
818 #define MCIC_VB_GR 0x0000000800000000ULL
819 #define MCIC_VB_CR 0x0000000400000000ULL
820 #define MCIC_VB_ST 0x0000000100000000ULL
821 #define MCIC_VB_AR 0x0000000040000000ULL
822 #define MCIC_VB_GS 0x0000000008000000ULL
823 #define MCIC_VB_PR 0x0000000000200000ULL
824 #define MCIC_VB_FC 0x0000000000100000ULL
825 #define MCIC_VB_CT 0x0000000000020000ULL
826 #define MCIC_VB_CC 0x0000000000010000ULL
827
s390_build_validity_mcic(void)828 static inline uint64_t s390_build_validity_mcic(void)
829 {
830 uint64_t mcic;
831
832 /*
833 * Indicate all validity bits (no damage) only. Other bits have to be
834 * added by the caller. (storage errors, subclasses and subclass modifiers)
835 */
836 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
837 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
838 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
839 if (s390_has_feat(S390_FEAT_VECTOR)) {
840 mcic |= MCIC_VB_VR;
841 }
842 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
843 mcic |= MCIC_VB_GS;
844 }
845 return mcic;
846 }
847
s390_do_cpu_full_reset(CPUState * cs,run_on_cpu_data arg)848 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
849 {
850 cpu_reset(cs);
851 }
852
s390_do_cpu_reset(CPUState * cs,run_on_cpu_data arg)853 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
854 {
855 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_NORMAL);
856 }
857
s390_do_cpu_initial_reset(CPUState * cs,run_on_cpu_data arg)858 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
859 {
860 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_INITIAL);
861 }
862
s390_do_cpu_load_normal(CPUState * cs,run_on_cpu_data arg)863 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
864 {
865 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
866
867 scc->load_normal(cs);
868 }
869
870
871 /* cpu.c */
872 void s390_crypto_reset(void);
873 void s390_cmma_reset(void);
874 void s390_enable_css_support(S390CPU *cpu);
875 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg);
876 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
877 int vq, bool assign);
878 #ifndef CONFIG_USER_ONLY
879 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
880 #else
s390_cpu_set_state(uint8_t cpu_state,S390CPU * cpu)881 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
882 {
883 return 0;
884 }
885 #endif /* CONFIG_USER_ONLY */
s390_cpu_get_state(S390CPU * cpu)886 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
887 {
888 return cpu->env.cpu_state;
889 }
890
891
892 /* helper.c */
893 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
894
895 /* interrupt.c */
896 #define RA_IGNORED 0
897 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);
898 /* service interrupts are floating therefore we must not pass an cpustate */
899 void s390_sclp_extint(uint32_t parm);
900
901 /* mmu_helper.c */
902 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
903 int len, bool is_write);
904 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
905 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
906 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
907 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
908 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
909 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
910 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
911 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
912 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
913 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
914 int len, bool is_write);
915 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \
916 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
917 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \
918 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
919
920 /* sigp.c */
921 int s390_cpu_restart(S390CPU *cpu);
922 void s390_init_sigp(void);
923
924 /* helper.c */
925 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
926 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
927
928 /* outside of target/s390x/ */
929 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
930
931 #endif
932