1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/maple_tree.h>
20 #include <linux/percpu.h>
21 #include <linux/psci.h>
22 #include <asm/arch_gicv3.h>
23 #include <asm/barrier.h>
24 #include <asm/cpufeature.h>
25 #include <asm/cputype.h>
26 #include <asm/daifflags.h>
27 #include <asm/fpsimd.h>
28 #include <asm/kvm.h>
29 #include <asm/kvm_asm.h>
30 #include <asm/vncr_mapping.h>
31
32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
33
34 #define KVM_HALT_POLL_NS_DEFAULT 500000
35
36 #include <kvm/arm_vgic.h>
37 #include <kvm/arm_arch_timer.h>
38 #include <kvm/arm_pmu.h>
39
40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
41
42 #define KVM_VCPU_MAX_FEATURES 7
43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
44
45 #define KVM_REQ_SLEEP \
46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7)
54
55 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
56 KVM_DIRTY_LOG_INITIALLY_SET)
57
58 #define KVM_HAVE_MMU_RWLOCK
59
60 /*
61 * Mode of operation configurable with kvm-arm.mode early param.
62 * See Documentation/admin-guide/kernel-parameters.txt for more information.
63 */
64 enum kvm_mode {
65 KVM_MODE_DEFAULT,
66 KVM_MODE_PROTECTED,
67 KVM_MODE_NV,
68 KVM_MODE_NONE,
69 };
70 #ifdef CONFIG_KVM
71 enum kvm_mode kvm_get_mode(void);
72 #else
kvm_get_mode(void)73 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
74 #endif
75
76 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
77
78 extern unsigned int __ro_after_init kvm_sve_max_vl;
79 int __init kvm_arm_init_sve(void);
80
81 u32 __attribute_const__ kvm_target_cpu(void);
82 void kvm_reset_vcpu(struct kvm_vcpu *vcpu);
83 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
84
85 struct kvm_hyp_memcache {
86 phys_addr_t head;
87 unsigned long nr_pages;
88 };
89
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))90 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
91 phys_addr_t *p,
92 phys_addr_t (*to_pa)(void *virt))
93 {
94 *p = mc->head;
95 mc->head = to_pa(p);
96 mc->nr_pages++;
97 }
98
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))99 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
100 void *(*to_va)(phys_addr_t phys))
101 {
102 phys_addr_t *p = to_va(mc->head);
103
104 if (!mc->nr_pages)
105 return NULL;
106
107 mc->head = *p;
108 mc->nr_pages--;
109
110 return p;
111 }
112
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)113 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
114 unsigned long min_pages,
115 void *(*alloc_fn)(void *arg),
116 phys_addr_t (*to_pa)(void *virt),
117 void *arg)
118 {
119 while (mc->nr_pages < min_pages) {
120 phys_addr_t *p = alloc_fn(arg);
121
122 if (!p)
123 return -ENOMEM;
124 push_hyp_memcache(mc, p, to_pa);
125 }
126
127 return 0;
128 }
129
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)130 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
131 void (*free_fn)(void *virt, void *arg),
132 void *(*to_va)(phys_addr_t phys),
133 void *arg)
134 {
135 while (mc->nr_pages)
136 free_fn(pop_hyp_memcache(mc, to_va), arg);
137 }
138
139 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
140 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
141
142 struct kvm_vmid {
143 atomic64_t id;
144 };
145
146 struct kvm_s2_mmu {
147 struct kvm_vmid vmid;
148
149 /*
150 * stage2 entry level table
151 *
152 * Two kvm_s2_mmu structures in the same VM can point to the same
153 * pgd here. This happens when running a guest using a
154 * translation regime that isn't affected by its own stage-2
155 * translation, such as a non-VHE hypervisor running at vEL2, or
156 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
157 * canonical stage-2 page tables.
158 */
159 phys_addr_t pgd_phys;
160 struct kvm_pgtable *pgt;
161
162 /*
163 * VTCR value used on the host. For a non-NV guest (or a NV
164 * guest that runs in a context where its own S2 doesn't
165 * apply), its T0SZ value reflects that of the IPA size.
166 *
167 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to
168 * the guest.
169 */
170 u64 vtcr;
171
172 /* The last vcpu id that ran on each physical CPU */
173 int __percpu *last_vcpu_ran;
174
175 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
176 /*
177 * Memory cache used to split
178 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
179 * is used to allocate stage2 page tables while splitting huge
180 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
181 * influences both the capacity of the split page cache, and
182 * how often KVM reschedules. Be wary of raising CHUNK_SIZE
183 * too high.
184 *
185 * Protected by kvm->slots_lock.
186 */
187 struct kvm_mmu_memory_cache split_page_cache;
188 uint64_t split_page_chunk_size;
189
190 struct kvm_arch *arch;
191 };
192
193 struct kvm_arch_memory_slot {
194 };
195
196 /**
197 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
198 *
199 * @std_bmap: Bitmap of standard secure service calls
200 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
201 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
202 */
203 struct kvm_smccc_features {
204 unsigned long std_bmap;
205 unsigned long std_hyp_bmap;
206 unsigned long vendor_hyp_bmap;
207 };
208
209 typedef unsigned int pkvm_handle_t;
210
211 struct kvm_protected_vm {
212 pkvm_handle_t handle;
213 struct kvm_hyp_memcache teardown_mc;
214 };
215
216 struct kvm_mpidr_data {
217 u64 mpidr_mask;
218 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx);
219 };
220
kvm_mpidr_index(struct kvm_mpidr_data * data,u64 mpidr)221 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr)
222 {
223 unsigned long mask = data->mpidr_mask;
224 u64 aff = mpidr & MPIDR_HWID_BITMASK;
225 int nbits, bit, bit_idx = 0;
226 u16 index = 0;
227
228 /*
229 * If this looks like RISC-V's BEXT or x86's PEXT
230 * instructions, it isn't by accident.
231 */
232 nbits = fls(mask);
233 for_each_set_bit(bit, &mask, nbits) {
234 index |= (aff & BIT(bit)) >> (bit - bit_idx);
235 bit_idx++;
236 }
237
238 return index;
239 }
240
241 struct kvm_arch {
242 struct kvm_s2_mmu mmu;
243
244 /* Interrupt controller */
245 struct vgic_dist vgic;
246
247 /* Timers */
248 struct arch_timer_vm_data timer_data;
249
250 /* Mandated version of PSCI */
251 u32 psci_version;
252
253 /* Protects VM-scoped configuration data */
254 struct mutex config_lock;
255
256 /*
257 * If we encounter a data abort without valid instruction syndrome
258 * information, report this to user space. User space can (and
259 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
260 * supported.
261 */
262 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
263 /* Memory Tagging Extension enabled for the guest */
264 #define KVM_ARCH_FLAG_MTE_ENABLED 1
265 /* At least one vCPU has ran in the VM */
266 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
267 /* The vCPU feature set for the VM is configured */
268 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3
269 /* PSCI SYSTEM_SUSPEND enabled for the guest */
270 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4
271 /* VM counter offset */
272 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5
273 /* Timer PPIs made immutable */
274 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6
275 /* Initial ID reg values loaded */
276 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7
277 unsigned long flags;
278
279 /* VM-wide vCPU feature set */
280 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
281
282 /* MPIDR to vcpu index mapping, optional */
283 struct kvm_mpidr_data *mpidr_data;
284
285 /*
286 * VM-wide PMU filter, implemented as a bitmap and big enough for
287 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
288 */
289 unsigned long *pmu_filter;
290 struct arm_pmu *arm_pmu;
291
292 cpumask_var_t supported_cpus;
293
294 /* PMCR_EL0.N value for the guest */
295 u8 pmcr_n;
296
297 /* Hypercall features firmware registers' descriptor */
298 struct kvm_smccc_features smccc_feat;
299 struct maple_tree smccc_filter;
300
301 /*
302 * Emulated CPU ID registers per VM
303 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
304 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
305 *
306 * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
307 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
308 */
309 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
310 #define IDX_IDREG(idx) sys_reg(3, 0, 0, ((idx) >> 3) + 1, (idx) & Op2_mask)
311 #define IDREG(kvm, id) ((kvm)->arch.id_regs[IDREG_IDX(id)])
312 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
313 u64 id_regs[KVM_ARM_ID_REG_NUM];
314
315 /*
316 * For an untrusted host VM, 'pkvm.handle' is used to lookup
317 * the associated pKVM instance in the hypervisor.
318 */
319 struct kvm_protected_vm pkvm;
320 };
321
322 struct kvm_vcpu_fault_info {
323 u64 esr_el2; /* Hyp Syndrom Register */
324 u64 far_el2; /* Hyp Fault Address Register */
325 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
326 u64 disr_el1; /* Deferred [SError] Status Register */
327 };
328
329 /*
330 * VNCR() just places the VNCR_capable registers in the enum after
331 * __VNCR_START__, and the value (after correction) to be an 8-byte offset
332 * from the VNCR base. As we don't require the enum to be otherwise ordered,
333 * we need the terrible hack below to ensure that we correctly size the
334 * sys_regs array, no matter what.
335 *
336 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful
337 * treasure trove of bit hacks:
338 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax
339 */
340 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y))))
341 #define VNCR(r) \
342 __before_##r, \
343 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \
344 __after_##r = __MAX__(__before_##r - 1, r)
345
346 enum vcpu_sysreg {
347 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
348 MPIDR_EL1, /* MultiProcessor Affinity Register */
349 CLIDR_EL1, /* Cache Level ID Register */
350 CSSELR_EL1, /* Cache Size Selection Register */
351 TPIDR_EL0, /* Thread ID, User R/W */
352 TPIDRRO_EL0, /* Thread ID, User R/O */
353 TPIDR_EL1, /* Thread ID, Privileged */
354 CNTKCTL_EL1, /* Timer Control Register (EL1) */
355 PAR_EL1, /* Physical Address Register */
356 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
357 OSLSR_EL1, /* OS Lock Status Register */
358 DISR_EL1, /* Deferred Interrupt Status Register */
359
360 /* Performance Monitors Registers */
361 PMCR_EL0, /* Control Register */
362 PMSELR_EL0, /* Event Counter Selection Register */
363 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
364 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
365 PMCCNTR_EL0, /* Cycle Counter Register */
366 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
367 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
368 PMCCFILTR_EL0, /* Cycle Count Filter Register */
369 PMCNTENSET_EL0, /* Count Enable Set Register */
370 PMINTENSET_EL1, /* Interrupt Enable Set Register */
371 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
372 PMUSERENR_EL0, /* User Enable Register */
373
374 /* Pointer Authentication Registers in a strict increasing order. */
375 APIAKEYLO_EL1,
376 APIAKEYHI_EL1,
377 APIBKEYLO_EL1,
378 APIBKEYHI_EL1,
379 APDAKEYLO_EL1,
380 APDAKEYHI_EL1,
381 APDBKEYLO_EL1,
382 APDBKEYHI_EL1,
383 APGAKEYLO_EL1,
384 APGAKEYHI_EL1,
385
386 /* Memory Tagging Extension registers */
387 RGSR_EL1, /* Random Allocation Tag Seed Register */
388 GCR_EL1, /* Tag Control Register */
389 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
390
391 /* 32bit specific registers. */
392 DACR32_EL2, /* Domain Access Control Register */
393 IFSR32_EL2, /* Instruction Fault Status Register */
394 FPEXC32_EL2, /* Floating-Point Exception Control Register */
395 DBGVCR32_EL2, /* Debug Vector Catch Register */
396
397 /* EL2 registers */
398 SCTLR_EL2, /* System Control Register (EL2) */
399 ACTLR_EL2, /* Auxiliary Control Register (EL2) */
400 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
401 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
402 HACR_EL2, /* Hypervisor Auxiliary Control Register */
403 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
404 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
405 TCR_EL2, /* Translation Control Register (EL2) */
406 SPSR_EL2, /* EL2 saved program status register */
407 ELR_EL2, /* EL2 exception link register */
408 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
409 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */
410 ESR_EL2, /* Exception Syndrome Register (EL2) */
411 FAR_EL2, /* Fault Address Register (EL2) */
412 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */
413 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */
414 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */
415 VBAR_EL2, /* Vector Base Address Register (EL2) */
416 RVBAR_EL2, /* Reset Vector Base Address Register */
417 CONTEXTIDR_EL2, /* Context ID Register (EL2) */
418 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
419 SP_EL2, /* EL2 Stack Pointer */
420 CNTHP_CTL_EL2,
421 CNTHP_CVAL_EL2,
422 CNTHV_CTL_EL2,
423 CNTHV_CVAL_EL2,
424
425 __VNCR_START__, /* Any VNCR-capable reg goes after this point */
426
427 VNCR(SCTLR_EL1),/* System Control Register */
428 VNCR(ACTLR_EL1),/* Auxiliary Control Register */
429 VNCR(CPACR_EL1),/* Coprocessor Access Control */
430 VNCR(ZCR_EL1), /* SVE Control */
431 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
432 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
433 VNCR(TCR_EL1), /* Translation Control Register */
434 VNCR(TCR2_EL1), /* Extended Translation Control Register */
435 VNCR(ESR_EL1), /* Exception Syndrome Register */
436 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */
437 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */
438 VNCR(FAR_EL1), /* Fault Address Register */
439 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */
440 VNCR(VBAR_EL1), /* Vector Base Address Register */
441 VNCR(CONTEXTIDR_EL1), /* Context ID Register */
442 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */
443 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */
444 VNCR(ELR_EL1),
445 VNCR(SP_EL1),
446 VNCR(SPSR_EL1),
447 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */
448 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */
449 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */
450 VNCR(HCR_EL2), /* Hypervisor Configuration Register */
451 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */
452 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */
453 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */
454 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */
455 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */
456
457 /* Permission Indirection Extension registers */
458 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */
459 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */
460
461 VNCR(HFGRTR_EL2),
462 VNCR(HFGWTR_EL2),
463 VNCR(HFGITR_EL2),
464 VNCR(HDFGRTR_EL2),
465 VNCR(HDFGWTR_EL2),
466 VNCR(HAFGRTR_EL2),
467
468 VNCR(CNTVOFF_EL2),
469 VNCR(CNTV_CVAL_EL0),
470 VNCR(CNTV_CTL_EL0),
471 VNCR(CNTP_CVAL_EL0),
472 VNCR(CNTP_CTL_EL0),
473
474 NR_SYS_REGS /* Nothing after this line! */
475 };
476
477 struct kvm_cpu_context {
478 struct user_pt_regs regs; /* sp = sp_el0 */
479
480 u64 spsr_abt;
481 u64 spsr_und;
482 u64 spsr_irq;
483 u64 spsr_fiq;
484
485 struct user_fpsimd_state fp_regs;
486
487 u64 sys_regs[NR_SYS_REGS];
488
489 struct kvm_vcpu *__hyp_running_vcpu;
490
491 /* This pointer has to be 4kB aligned. */
492 u64 *vncr_array;
493 };
494
495 struct kvm_host_data {
496 struct kvm_cpu_context host_ctxt;
497 };
498
499 struct kvm_host_psci_config {
500 /* PSCI version used by host. */
501 u32 version;
502 u32 smccc_version;
503
504 /* Function IDs used by host if version is v0.1. */
505 struct psci_0_1_function_ids function_ids_0_1;
506
507 bool psci_0_1_cpu_suspend_implemented;
508 bool psci_0_1_cpu_on_implemented;
509 bool psci_0_1_cpu_off_implemented;
510 bool psci_0_1_migrate_implemented;
511 };
512
513 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
514 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
515
516 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
517 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
518
519 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
520 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
521
522 struct vcpu_reset_state {
523 unsigned long pc;
524 unsigned long r0;
525 bool be;
526 bool reset;
527 };
528
529 struct kvm_vcpu_arch {
530 struct kvm_cpu_context ctxt;
531
532 /*
533 * Guest floating point state
534 *
535 * The architecture has two main floating point extensions,
536 * the original FPSIMD and SVE. These have overlapping
537 * register views, with the FPSIMD V registers occupying the
538 * low 128 bits of the SVE Z registers. When the core
539 * floating point code saves the register state of a task it
540 * records which view it saved in fp_type.
541 */
542 void *sve_state;
543 enum fp_type fp_type;
544 unsigned int sve_max_vl;
545 u64 svcr;
546
547 /* Stage 2 paging state used by the hardware on next switch */
548 struct kvm_s2_mmu *hw_mmu;
549
550 /* Values of trap registers for the guest. */
551 u64 hcr_el2;
552 u64 mdcr_el2;
553 u64 cptr_el2;
554
555 /* Values of trap registers for the host before guest entry. */
556 u64 mdcr_el2_host;
557
558 /* Exception Information */
559 struct kvm_vcpu_fault_info fault;
560
561 /* Ownership of the FP regs */
562 enum {
563 FP_STATE_FREE,
564 FP_STATE_HOST_OWNED,
565 FP_STATE_GUEST_OWNED,
566 } fp_state;
567
568 /* Configuration flags, set once and for all before the vcpu can run */
569 u8 cflags;
570
571 /* Input flags to the hypervisor code, potentially cleared after use */
572 u8 iflags;
573
574 /* State flags for kernel bookkeeping, unused by the hypervisor code */
575 u8 sflags;
576
577 /*
578 * Don't run the guest (internal implementation need).
579 *
580 * Contrary to the flags above, this is set/cleared outside of
581 * a vcpu context, and thus cannot be mixed with the flags
582 * themselves (or the flag accesses need to be made atomic).
583 */
584 bool pause;
585
586 /*
587 * We maintain more than a single set of debug registers to support
588 * debugging the guest from the host and to maintain separate host and
589 * guest state during world switches. vcpu_debug_state are the debug
590 * registers of the vcpu as the guest sees them. host_debug_state are
591 * the host registers which are saved and restored during
592 * world switches. external_debug_state contains the debug
593 * values we want to debug the guest. This is set via the
594 * KVM_SET_GUEST_DEBUG ioctl.
595 *
596 * debug_ptr points to the set of debug registers that should be loaded
597 * onto the hardware when running the guest.
598 */
599 struct kvm_guest_debug_arch *debug_ptr;
600 struct kvm_guest_debug_arch vcpu_debug_state;
601 struct kvm_guest_debug_arch external_debug_state;
602
603 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
604 struct task_struct *parent_task;
605
606 struct {
607 /* {Break,watch}point registers */
608 struct kvm_guest_debug_arch regs;
609 /* Statistical profiling extension */
610 u64 pmscr_el1;
611 /* Self-hosted trace */
612 u64 trfcr_el1;
613 } host_debug_state;
614
615 /* VGIC state */
616 struct vgic_cpu vgic_cpu;
617 struct arch_timer_cpu timer_cpu;
618 struct kvm_pmu pmu;
619
620 /*
621 * Guest registers we preserve during guest debugging.
622 *
623 * These shadow registers are updated by the kvm_handle_sys_reg
624 * trap handler if the guest accesses or updates them while we
625 * are using guest debug.
626 */
627 struct {
628 u32 mdscr_el1;
629 bool pstate_ss;
630 } guest_debug_preserved;
631
632 /* vcpu power state */
633 struct kvm_mp_state mp_state;
634 spinlock_t mp_state_lock;
635
636 /* Cache some mmu pages needed inside spinlock regions */
637 struct kvm_mmu_memory_cache mmu_page_cache;
638
639 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
640 u64 vsesr_el2;
641
642 /* Additional reset state */
643 struct vcpu_reset_state reset_state;
644
645 /* Guest PV state */
646 struct {
647 u64 last_steal;
648 gpa_t base;
649 } steal;
650
651 /* Per-vcpu CCSIDR override or NULL */
652 u32 *ccsidr;
653 };
654
655 /*
656 * Each 'flag' is composed of a comma-separated triplet:
657 *
658 * - the flag-set it belongs to in the vcpu->arch structure
659 * - the value for that flag
660 * - the mask for that flag
661 *
662 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
663 * unpack_vcpu_flag() extract the flag value from the triplet for
664 * direct use outside of the flag accessors.
665 */
666 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
667
668 #define __unpack_flag(_set, _f, _m) _f
669 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
670
671 #define __build_check_flag(v, flagset, f, m) \
672 do { \
673 typeof(v->arch.flagset) *_fset; \
674 \
675 /* Check that the flags fit in the mask */ \
676 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
677 /* Check that the flags fit in the type */ \
678 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
679 } while (0)
680
681 #define __vcpu_get_flag(v, flagset, f, m) \
682 ({ \
683 __build_check_flag(v, flagset, f, m); \
684 \
685 READ_ONCE(v->arch.flagset) & (m); \
686 })
687
688 /*
689 * Note that the set/clear accessors must be preempt-safe in order to
690 * avoid nesting them with load/put which also manipulate flags...
691 */
692 #ifdef __KVM_NVHE_HYPERVISOR__
693 /* the nVHE hypervisor is always non-preemptible */
694 #define __vcpu_flags_preempt_disable()
695 #define __vcpu_flags_preempt_enable()
696 #else
697 #define __vcpu_flags_preempt_disable() preempt_disable()
698 #define __vcpu_flags_preempt_enable() preempt_enable()
699 #endif
700
701 #define __vcpu_set_flag(v, flagset, f, m) \
702 do { \
703 typeof(v->arch.flagset) *fset; \
704 \
705 __build_check_flag(v, flagset, f, m); \
706 \
707 fset = &v->arch.flagset; \
708 __vcpu_flags_preempt_disable(); \
709 if (HWEIGHT(m) > 1) \
710 *fset &= ~(m); \
711 *fset |= (f); \
712 __vcpu_flags_preempt_enable(); \
713 } while (0)
714
715 #define __vcpu_clear_flag(v, flagset, f, m) \
716 do { \
717 typeof(v->arch.flagset) *fset; \
718 \
719 __build_check_flag(v, flagset, f, m); \
720 \
721 fset = &v->arch.flagset; \
722 __vcpu_flags_preempt_disable(); \
723 *fset &= ~(m); \
724 __vcpu_flags_preempt_enable(); \
725 } while (0)
726
727 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
728 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
729 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
730
731 /* SVE exposed to guest */
732 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0))
733 /* SVE config completed */
734 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
735 /* PTRAUTH exposed to guest */
736 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2))
737 /* KVM_ARM_VCPU_INIT completed */
738 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(3))
739
740 /* Exception pending */
741 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
742 /*
743 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
744 * be set together with an exception...
745 */
746 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
747 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
748 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
749
750 /* Helpers to encode exceptions with minimum fuss */
751 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
752 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
753 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
754
755 /*
756 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
757 * values:
758 *
759 * For AArch32 EL1:
760 */
761 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
762 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
763 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
764 /* For AArch64: */
765 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
766 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
767 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
768 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
769 /* For AArch64 with NV: */
770 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
771 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
772 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
773 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
774 /* Guest debug is live */
775 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4))
776 /* Save SPE context if active */
777 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5))
778 /* Save TRBE context if active */
779 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6))
780 /* vcpu running in HYP context */
781 #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7))
782
783 /* SVE enabled for host EL0 */
784 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0))
785 /* SME enabled for EL0 */
786 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1))
787 /* Physical CPU not in supported_cpus */
788 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2))
789 /* WFIT instruction trapped */
790 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3))
791 /* vcpu system registers loaded on physical CPU */
792 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4))
793 /* Software step state is Active-pending */
794 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5))
795 /* PMUSERENR for the guest EL0 is on physical CPU */
796 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6))
797 /* WFI instruction trapped */
798 #define IN_WFI __vcpu_single_flag(sflags, BIT(7))
799
800
801 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
802 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
803 sve_ffr_offset((vcpu)->arch.sve_max_vl))
804
805 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
806
807 #define vcpu_sve_state_size(vcpu) ({ \
808 size_t __size_ret; \
809 unsigned int __vcpu_vq; \
810 \
811 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
812 __size_ret = 0; \
813 } else { \
814 __vcpu_vq = vcpu_sve_max_vq(vcpu); \
815 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
816 } \
817 \
818 __size_ret; \
819 })
820
821 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
822 KVM_GUESTDBG_USE_SW_BP | \
823 KVM_GUESTDBG_USE_HW | \
824 KVM_GUESTDBG_SINGLESTEP)
825
826 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
827 vcpu_get_flag(vcpu, GUEST_HAS_SVE))
828
829 #ifdef CONFIG_ARM64_PTR_AUTH
830 #define vcpu_has_ptrauth(vcpu) \
831 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
832 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
833 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
834 #else
835 #define vcpu_has_ptrauth(vcpu) false
836 #endif
837
838 #define vcpu_on_unsupported_cpu(vcpu) \
839 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
840
841 #define vcpu_set_on_unsupported_cpu(vcpu) \
842 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
843
844 #define vcpu_clear_on_unsupported_cpu(vcpu) \
845 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
846
847 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
848
849 /*
850 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
851 * memory backed version of a register, and not the one most recently
852 * accessed by a running VCPU. For example, for userspace access or
853 * for system registers that are never context switched, but only
854 * emulated.
855 *
856 * Don't bother with VNCR-based accesses in the nVHE code, it has no
857 * business dealing with NV.
858 */
__ctxt_sys_reg(const struct kvm_cpu_context * ctxt,int r)859 static inline u64 *__ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
860 {
861 #if !defined (__KVM_NVHE_HYPERVISOR__)
862 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
863 r >= __VNCR_START__ && ctxt->vncr_array))
864 return &ctxt->vncr_array[r - __VNCR_START__];
865 #endif
866 return (u64 *)&ctxt->sys_regs[r];
867 }
868
869 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
870
871 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
872
873 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
874 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
875
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)876 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
877 {
878 /*
879 * *** VHE ONLY ***
880 *
881 * System registers listed in the switch are not saved on every
882 * exit from the guest but are only saved on vcpu_put.
883 *
884 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
885 * should never be listed below, because the guest cannot modify its
886 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
887 * thread when emulating cross-VCPU communication.
888 */
889 if (!has_vhe())
890 return false;
891
892 switch (reg) {
893 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
894 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
895 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
896 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
897 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
898 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
899 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
900 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
901 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
902 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
903 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
904 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
905 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
906 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
907 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
908 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
909 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
910 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
911 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break;
912 case PAR_EL1: *val = read_sysreg_par(); break;
913 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
914 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
915 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
916 default: return false;
917 }
918
919 return true;
920 }
921
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)922 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
923 {
924 /*
925 * *** VHE ONLY ***
926 *
927 * System registers listed in the switch are not restored on every
928 * entry to the guest but are only restored on vcpu_load.
929 *
930 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
931 * should never be listed below, because the MPIDR should only be set
932 * once, before running the VCPU, and never changed later.
933 */
934 if (!has_vhe())
935 return false;
936
937 switch (reg) {
938 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
939 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
940 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
941 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
942 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
943 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
944 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
945 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
946 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
947 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
948 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
949 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
950 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
951 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
952 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
953 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
954 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
955 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
956 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
957 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
958 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
959 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
960 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
961 default: return false;
962 }
963
964 return true;
965 }
966
967 struct kvm_vm_stat {
968 struct kvm_vm_stat_generic generic;
969 };
970
971 struct kvm_vcpu_stat {
972 struct kvm_vcpu_stat_generic generic;
973 u64 hvc_exit_stat;
974 u64 wfe_exit_stat;
975 u64 wfi_exit_stat;
976 u64 mmio_exit_user;
977 u64 mmio_exit_kernel;
978 u64 signal_exits;
979 u64 exits;
980 };
981
982 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
983 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
984 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
985 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
986
987 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
988 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
989
990 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
991 struct kvm_vcpu_events *events);
992
993 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
994 struct kvm_vcpu_events *events);
995
996 void kvm_arm_halt_guest(struct kvm *kvm);
997 void kvm_arm_resume_guest(struct kvm *kvm);
998
999 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
1000
1001 #ifndef __KVM_NVHE_HYPERVISOR__
1002 #define kvm_call_hyp_nvhe(f, ...) \
1003 ({ \
1004 struct arm_smccc_res res; \
1005 \
1006 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
1007 ##__VA_ARGS__, &res); \
1008 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
1009 \
1010 res.a1; \
1011 })
1012
1013 /*
1014 * The couple of isb() below are there to guarantee the same behaviour
1015 * on VHE as on !VHE, where the eret to EL1 acts as a context
1016 * synchronization event.
1017 */
1018 #define kvm_call_hyp(f, ...) \
1019 do { \
1020 if (has_vhe()) { \
1021 f(__VA_ARGS__); \
1022 isb(); \
1023 } else { \
1024 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1025 } \
1026 } while(0)
1027
1028 #define kvm_call_hyp_ret(f, ...) \
1029 ({ \
1030 typeof(f(__VA_ARGS__)) ret; \
1031 \
1032 if (has_vhe()) { \
1033 ret = f(__VA_ARGS__); \
1034 isb(); \
1035 } else { \
1036 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1037 } \
1038 \
1039 ret; \
1040 })
1041 #else /* __KVM_NVHE_HYPERVISOR__ */
1042 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
1043 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
1044 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
1045 #endif /* __KVM_NVHE_HYPERVISOR__ */
1046
1047 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
1048 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
1049
1050 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
1051 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
1052 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
1053 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
1054 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
1055 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
1056 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
1057
1058 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
1059
1060 int __init kvm_sys_reg_table_init(void);
1061 int __init populate_nv_trap_config(void);
1062
1063 bool lock_all_vcpus(struct kvm *kvm);
1064 void unlock_all_vcpus(struct kvm *kvm);
1065
1066 /* MMIO helpers */
1067 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
1068 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
1069
1070 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
1071 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
1072
1073 /*
1074 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
1075 * arrived in guest context. For arm64, any event that arrives while a vCPU is
1076 * loaded is considered to be "in guest".
1077 */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1078 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1079 {
1080 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1081 }
1082
1083 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1084 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1085 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1086
1087 bool kvm_arm_pvtime_supported(void);
1088 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1089 struct kvm_device_attr *attr);
1090 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1091 struct kvm_device_attr *attr);
1092 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1093 struct kvm_device_attr *attr);
1094
1095 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1096 int __init kvm_arm_vmid_alloc_init(void);
1097 void __init kvm_arm_vmid_alloc_free(void);
1098 bool kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1099 void kvm_arm_vmid_clear_active(void);
1100
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1101 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1102 {
1103 vcpu_arch->steal.base = INVALID_GPA;
1104 }
1105
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1106 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1107 {
1108 return (vcpu_arch->steal.base != INVALID_GPA);
1109 }
1110
1111 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1112
1113 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1114
1115 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1116
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1117 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1118 {
1119 /* The host's MPIDR is immutable, so let's set it up at boot time */
1120 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1121 }
1122
kvm_system_needs_idmapped_vectors(void)1123 static inline bool kvm_system_needs_idmapped_vectors(void)
1124 {
1125 return cpus_have_final_cap(ARM64_SPECTRE_V3A);
1126 }
1127
kvm_arch_sync_events(struct kvm * kvm)1128 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)1129 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1130
1131 void kvm_arm_init_debug(void);
1132 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1133 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1134 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1135 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1136
1137 #define kvm_vcpu_os_lock_enabled(vcpu) \
1138 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK))
1139
1140 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1141 struct kvm_device_attr *attr);
1142 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1143 struct kvm_device_attr *attr);
1144 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1145 struct kvm_device_attr *attr);
1146
1147 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1148 struct kvm_arm_copy_mte_tags *copy_tags);
1149 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1150 struct kvm_arm_counter_offset *offset);
1151 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm,
1152 struct reg_mask_range *range);
1153
1154 /* Guest/host FPSIMD coordination helpers */
1155 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1156 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1157 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1158 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1159 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1160 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1161
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1162 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1163 {
1164 return (!has_vhe() && attr->exclude_host);
1165 }
1166
1167 /* Flags for host debug state */
1168 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1169 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1170
1171 #ifdef CONFIG_KVM
1172 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1173 void kvm_clr_pmu_events(u32 clr);
1174 bool kvm_set_pmuserenr(u64 val);
1175 #else
kvm_set_pmu_events(u32 set,struct perf_event_attr * attr)1176 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u32 clr)1177 static inline void kvm_clr_pmu_events(u32 clr) {}
kvm_set_pmuserenr(u64 val)1178 static inline bool kvm_set_pmuserenr(u64 val)
1179 {
1180 return false;
1181 }
1182 #endif
1183
1184 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu);
1185 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu);
1186
1187 int __init kvm_set_ipa_limit(void);
1188
1189 #define __KVM_HAVE_ARCH_VM_ALLOC
1190 struct kvm *kvm_arch_alloc_vm(void);
1191
1192 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
1193
1194 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
1195
kvm_vm_is_protected(struct kvm * kvm)1196 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1197 {
1198 return false;
1199 }
1200
1201 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1202 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1203
1204 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1205
1206 #define kvm_has_mte(kvm) \
1207 (system_supports_mte() && \
1208 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1209
1210 #define kvm_supports_32bit_el0() \
1211 (system_supports_32bit_el0() && \
1212 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1213
1214 #define kvm_vm_has_ran_once(kvm) \
1215 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1216
__vcpu_has_feature(const struct kvm_arch * ka,int feature)1217 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature)
1218 {
1219 return test_bit(feature, ka->vcpu_features);
1220 }
1221
1222 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f))
1223
1224 int kvm_trng_call(struct kvm_vcpu *vcpu);
1225 #ifdef CONFIG_KVM
1226 extern phys_addr_t hyp_mem_base;
1227 extern phys_addr_t hyp_mem_size;
1228 void __init kvm_hyp_reserve(void);
1229 #else
kvm_hyp_reserve(void)1230 static inline void kvm_hyp_reserve(void) { }
1231 #endif
1232
1233 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1234 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1235
1236 #endif /* __ARM64_KVM_HOST_H__ */
1237