xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision f0bf3eac92b2be5f34b944cb82f1c23db642c7f5) ! 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88 	MLX5_OBJ_TYPE_STC = 0x0040,
89 	MLX5_OBJ_TYPE_RTC = 0x0041,
90 	MLX5_OBJ_TYPE_STE = 0x0042,
91 	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 	MLX5_OBJ_TYPE_MKEY = 0xff01,
94 	MLX5_OBJ_TYPE_QP = 0xff02,
95 	MLX5_OBJ_TYPE_PSV = 0xff03,
96 	MLX5_OBJ_TYPE_RMP = 0xff04,
97 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 	MLX5_OBJ_TYPE_RQ = 0xff06,
99 	MLX5_OBJ_TYPE_SQ = 0xff07,
100 	MLX5_OBJ_TYPE_TIR = 0xff08,
101 	MLX5_OBJ_TYPE_TIS = 0xff09,
102 	MLX5_OBJ_TYPE_DCT = 0xff0a,
103 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 	MLX5_OBJ_TYPE_RQT = 0xff0e,
105 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 	MLX5_OBJ_TYPE_CQ = 0xff10,
107 	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108 };
109 
110 enum {
111 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117 };
118 
119 enum {
120 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192 	MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA      = 0x732,
193 	MLX5_CMD_OPCODE_CREATE_ESW_VPORT          = 0x733,
194 	MLX5_CMD_OPCODE_DESTROY_ESW_VPORT         = 0x734,
195 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
196 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
197 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
198 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
199 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
200 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
201 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
202 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
203 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
204 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
205 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
206 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
207 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
208 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
209 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
210 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
211 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
212 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
213 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
214 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
215 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
216 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
217 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
218 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
219 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
220 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
221 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
222 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
223 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
224 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
225 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
226 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
227 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
228 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
229 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
230 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
231 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
232 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
233 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
234 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
235 	MLX5_CMD_OP_NOP                           = 0x80d,
236 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
237 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
238 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
239 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
240 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
241 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
242 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
243 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
244 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
245 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
246 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
247 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
248 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
249 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
250 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
251 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
252 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
253 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
254 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
255 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
256 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
257 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
258 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
259 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
260 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
261 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
262 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
263 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
264 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
265 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
266 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
267 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
268 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
269 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
270 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
271 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
272 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
273 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
274 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
275 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
276 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
277 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
278 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
279 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
280 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
281 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
282 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
283 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
284 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
285 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
286 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
287 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
288 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
289 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
290 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
291 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
292 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
293 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
294 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
295 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
296 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
297 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
298 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
299 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
300 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
301 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
302 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
303 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
304 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
305 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
306 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
307 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
308 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
309 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
310 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
311 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
312 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
313 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
314 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
315 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
316 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
317 	MLX5_CMD_OP_PSP_GEN_SPI                   = 0xb10,
318 	MLX5_CMD_OP_PSP_ROTATE_KEY                = 0xb11,
319 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
320 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
321 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
322 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
323 	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
324 	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
325 	MLX5_CMD_OP_MAX
326 };
327 
328 /* Valid range for general commands that don't work over an object */
329 enum {
330 	MLX5_CMD_OP_GENERAL_START = 0xb00,
331 	MLX5_CMD_OP_GENERAL_END = 0xd00,
332 };
333 
334 enum {
335 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
336 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
337 };
338 
339 enum {
340 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
341 };
342 
343 struct mlx5_ifc_flow_table_fields_supported_bits {
344 	u8         outer_dmac[0x1];
345 	u8         outer_smac[0x1];
346 	u8         outer_ether_type[0x1];
347 	u8         outer_ip_version[0x1];
348 	u8         outer_first_prio[0x1];
349 	u8         outer_first_cfi[0x1];
350 	u8         outer_first_vid[0x1];
351 	u8         outer_ipv4_ttl[0x1];
352 	u8         outer_second_prio[0x1];
353 	u8         outer_second_cfi[0x1];
354 	u8         outer_second_vid[0x1];
355 	u8         reserved_at_b[0x1];
356 	u8         outer_sip[0x1];
357 	u8         outer_dip[0x1];
358 	u8         outer_frag[0x1];
359 	u8         outer_ip_protocol[0x1];
360 	u8         outer_ip_ecn[0x1];
361 	u8         outer_ip_dscp[0x1];
362 	u8         outer_udp_sport[0x1];
363 	u8         outer_udp_dport[0x1];
364 	u8         outer_tcp_sport[0x1];
365 	u8         outer_tcp_dport[0x1];
366 	u8         outer_tcp_flags[0x1];
367 	u8         outer_gre_protocol[0x1];
368 	u8         outer_gre_key[0x1];
369 	u8         outer_vxlan_vni[0x1];
370 	u8         outer_geneve_vni[0x1];
371 	u8         outer_geneve_oam[0x1];
372 	u8         outer_geneve_protocol_type[0x1];
373 	u8         outer_geneve_opt_len[0x1];
374 	u8         source_vhca_port[0x1];
375 	u8         source_eswitch_port[0x1];
376 
377 	u8         inner_dmac[0x1];
378 	u8         inner_smac[0x1];
379 	u8         inner_ether_type[0x1];
380 	u8         inner_ip_version[0x1];
381 	u8         inner_first_prio[0x1];
382 	u8         inner_first_cfi[0x1];
383 	u8         inner_first_vid[0x1];
384 	u8         reserved_at_27[0x1];
385 	u8         inner_second_prio[0x1];
386 	u8         inner_second_cfi[0x1];
387 	u8         inner_second_vid[0x1];
388 	u8         reserved_at_2b[0x1];
389 	u8         inner_sip[0x1];
390 	u8         inner_dip[0x1];
391 	u8         inner_frag[0x1];
392 	u8         inner_ip_protocol[0x1];
393 	u8         inner_ip_ecn[0x1];
394 	u8         inner_ip_dscp[0x1];
395 	u8         inner_udp_sport[0x1];
396 	u8         inner_udp_dport[0x1];
397 	u8         inner_tcp_sport[0x1];
398 	u8         inner_tcp_dport[0x1];
399 	u8         inner_tcp_flags[0x1];
400 	u8         reserved_at_37[0x9];
401 
402 	u8         geneve_tlv_option_0_data[0x1];
403 	u8         geneve_tlv_option_0_exist[0x1];
404 	u8         reserved_at_42[0x3];
405 	u8         outer_first_mpls_over_udp[0x4];
406 	u8         outer_first_mpls_over_gre[0x4];
407 	u8         inner_first_mpls[0x4];
408 	u8         outer_first_mpls[0x4];
409 	u8         reserved_at_55[0x2];
410 	u8	   outer_esp_spi[0x1];
411 	u8         reserved_at_58[0x2];
412 	u8         bth_dst_qp[0x1];
413 	u8         reserved_at_5b[0x5];
414 
415 	u8         reserved_at_60[0x18];
416 	u8         metadata_reg_c_7[0x1];
417 	u8         metadata_reg_c_6[0x1];
418 	u8         metadata_reg_c_5[0x1];
419 	u8         metadata_reg_c_4[0x1];
420 	u8         metadata_reg_c_3[0x1];
421 	u8         metadata_reg_c_2[0x1];
422 	u8         metadata_reg_c_1[0x1];
423 	u8         metadata_reg_c_0[0x1];
424 };
425 
426 /* Table 2170 - Flow Table Fields Supported 2 Format */
427 struct mlx5_ifc_flow_table_fields_supported_2_bits {
428 	u8         inner_l4_type_ext[0x1];
429 	u8         outer_l4_type_ext[0x1];
430 	u8         inner_l4_type[0x1];
431 	u8         outer_l4_type[0x1];
432 	u8         reserved_at_4[0xa];
433 	u8         bth_opcode[0x1];
434 	u8         reserved_at_f[0x1];
435 	u8         tunnel_header_0_1[0x1];
436 	u8         reserved_at_11[0xf];
437 
438 	u8         reserved_at_20[0xf];
439 	u8         ipsec_next_header[0x1];
440 	u8         reserved_at_30[0x10];
441 
442 	u8         reserved_at_40[0x40];
443 };
444 
445 struct mlx5_ifc_flow_table_prop_layout_bits {
446 	u8         ft_support[0x1];
447 	u8         reserved_at_1[0x1];
448 	u8         flow_counter[0x1];
449 	u8	   flow_modify_en[0x1];
450 	u8         modify_root[0x1];
451 	u8         identified_miss_table_mode[0x1];
452 	u8         flow_table_modify[0x1];
453 	u8         reformat[0x1];
454 	u8         decap[0x1];
455 	u8         reset_root_to_default[0x1];
456 	u8         pop_vlan[0x1];
457 	u8         push_vlan[0x1];
458 	u8         reserved_at_c[0x1];
459 	u8         pop_vlan_2[0x1];
460 	u8         push_vlan_2[0x1];
461 	u8	   reformat_and_vlan_action[0x1];
462 	u8	   reserved_at_10[0x1];
463 	u8         sw_owner[0x1];
464 	u8	   reformat_l3_tunnel_to_l2[0x1];
465 	u8	   reformat_l2_to_l3_tunnel[0x1];
466 	u8	   reformat_and_modify_action[0x1];
467 	u8	   ignore_flow_level[0x1];
468 	u8         reserved_at_16[0x1];
469 	u8	   table_miss_action_domain[0x1];
470 	u8         termination_table[0x1];
471 	u8         reformat_and_fwd_to_table[0x1];
472 	u8         forward_vhca_rx[0x1];
473 	u8         reserved_at_1b[0x1];
474 	u8         ipsec_encrypt[0x1];
475 	u8         ipsec_decrypt[0x1];
476 	u8         sw_owner_v2[0x1];
477 	u8         reserved_at_1f[0x1];
478 
479 	u8         termination_table_raw_traffic[0x1];
480 	u8         reserved_at_21[0x1];
481 	u8         log_max_ft_size[0x6];
482 	u8         log_max_modify_header_context[0x8];
483 	u8         max_modify_header_actions[0x8];
484 	u8         max_ft_level[0x8];
485 
486 	u8         reformat_add_esp_trasport[0x1];
487 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
488 	u8         reformat_add_esp_transport_over_udp[0x1];
489 	u8         reformat_del_esp_trasport[0x1];
490 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
491 	u8         reformat_del_esp_transport_over_udp[0x1];
492 	u8         execute_aso[0x1];
493 	u8         reserved_at_47[0x19];
494 
495 	u8         reformat_l2_to_l3_psp_tunnel[0x1];
496 	u8         reformat_l3_psp_tunnel_to_l2[0x1];
497 	u8         reformat_insert[0x1];
498 	u8         reformat_remove[0x1];
499 	u8         macsec_encrypt[0x1];
500 	u8         macsec_decrypt[0x1];
501 	u8         psp_encrypt[0x1];
502 	u8         psp_decrypt[0x1];
503 	u8         reformat_add_macsec[0x1];
504 	u8         reformat_remove_macsec[0x1];
505 	u8         reparse[0x1];
506 	u8         reserved_at_6b[0x1];
507 	u8         cross_vhca_object[0x1];
508 	u8         reformat_l2_to_l3_audp_tunnel[0x1];
509 	u8         reformat_l3_audp_tunnel_to_l2[0x1];
510 	u8         ignore_flow_level_rtc_valid[0x1];
511 	u8         reserved_at_70[0x8];
512 	u8         log_max_ft_num[0x8];
513 
514 	u8         reserved_at_80[0x10];
515 	u8         log_max_flow_counter[0x8];
516 	u8         log_max_destination[0x8];
517 
518 	u8         reserved_at_a0[0x18];
519 	u8         log_max_flow[0x8];
520 
521 	u8         reserved_at_c0[0x40];
522 
523 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
524 
525 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
526 };
527 
528 struct mlx5_ifc_odp_per_transport_service_cap_bits {
529 	u8         send[0x1];
530 	u8         receive[0x1];
531 	u8         write[0x1];
532 	u8         read[0x1];
533 	u8         atomic[0x1];
534 	u8         srq_receive[0x1];
535 	u8         reserved_at_6[0x1a];
536 };
537 
538 struct mlx5_ifc_ipv4_layout_bits {
539 	u8         reserved_at_0[0x60];
540 
541 	u8         ipv4[0x20];
542 };
543 
544 struct mlx5_ifc_ipv6_layout_bits {
545 	u8         ipv6[16][0x8];
546 };
547 
548 struct mlx5_ifc_ipv6_simple_layout_bits {
549 	u8         ipv6_127_96[0x20];
550 	u8         ipv6_95_64[0x20];
551 	u8         ipv6_63_32[0x20];
552 	u8         ipv6_31_0[0x20];
553 };
554 
555 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
556 	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
557 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
558 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
559 	u8         reserved_at_0[0x80];
560 };
561 
562 enum {
563 	MLX5_PACKET_L4_TYPE_NONE,
564 	MLX5_PACKET_L4_TYPE_TCP,
565 	MLX5_PACKET_L4_TYPE_UDP,
566 };
567 
568 enum {
569 	MLX5_PACKET_L4_TYPE_EXT_NONE,
570 	MLX5_PACKET_L4_TYPE_EXT_TCP,
571 	MLX5_PACKET_L4_TYPE_EXT_UDP,
572 	MLX5_PACKET_L4_TYPE_EXT_ICMP,
573 };
574 
575 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
576 	u8         smac_47_16[0x20];
577 
578 	u8         smac_15_0[0x10];
579 	u8         ethertype[0x10];
580 
581 	u8         dmac_47_16[0x20];
582 
583 	u8         dmac_15_0[0x10];
584 	u8         first_prio[0x3];
585 	u8         first_cfi[0x1];
586 	u8         first_vid[0xc];
587 
588 	u8         ip_protocol[0x8];
589 	u8         ip_dscp[0x6];
590 	u8         ip_ecn[0x2];
591 	u8         cvlan_tag[0x1];
592 	u8         svlan_tag[0x1];
593 	u8         frag[0x1];
594 	u8         ip_version[0x4];
595 	u8         tcp_flags[0x9];
596 
597 	u8         tcp_sport[0x10];
598 	u8         tcp_dport[0x10];
599 
600 	u8         l4_type[0x2];
601 	u8         l4_type_ext[0x4];
602 	u8         reserved_at_c6[0xa];
603 	u8         ipv4_ihl[0x4];
604 	u8         reserved_at_d4[0x4];
605 	u8         ttl_hoplimit[0x8];
606 
607 	u8         udp_sport[0x10];
608 	u8         udp_dport[0x10];
609 
610 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
611 
612 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
613 };
614 
615 struct mlx5_ifc_nvgre_key_bits {
616 	u8 hi[0x18];
617 	u8 lo[0x8];
618 };
619 
620 union mlx5_ifc_gre_key_bits {
621 	struct mlx5_ifc_nvgre_key_bits nvgre;
622 	u8 key[0x20];
623 };
624 
625 struct mlx5_ifc_fte_match_set_misc_bits {
626 	u8         gre_c_present[0x1];
627 	u8         reserved_at_1[0x1];
628 	u8         gre_k_present[0x1];
629 	u8         gre_s_present[0x1];
630 	u8         source_vhca_port[0x4];
631 	u8         source_sqn[0x18];
632 
633 	u8         source_eswitch_owner_vhca_id[0x10];
634 	u8         source_port[0x10];
635 
636 	u8         outer_second_prio[0x3];
637 	u8         outer_second_cfi[0x1];
638 	u8         outer_second_vid[0xc];
639 	u8         inner_second_prio[0x3];
640 	u8         inner_second_cfi[0x1];
641 	u8         inner_second_vid[0xc];
642 
643 	u8         outer_second_cvlan_tag[0x1];
644 	u8         inner_second_cvlan_tag[0x1];
645 	u8         outer_second_svlan_tag[0x1];
646 	u8         inner_second_svlan_tag[0x1];
647 	u8         reserved_at_64[0xc];
648 	u8         gre_protocol[0x10];
649 
650 	union mlx5_ifc_gre_key_bits gre_key;
651 
652 	u8         vxlan_vni[0x18];
653 	u8         bth_opcode[0x8];
654 
655 	u8         geneve_vni[0x18];
656 	u8         reserved_at_d8[0x6];
657 	u8         geneve_tlv_option_0_exist[0x1];
658 	u8         geneve_oam[0x1];
659 
660 	u8         reserved_at_e0[0xc];
661 	u8         outer_ipv6_flow_label[0x14];
662 
663 	u8         reserved_at_100[0xc];
664 	u8         inner_ipv6_flow_label[0x14];
665 
666 	u8         reserved_at_120[0xa];
667 	u8         geneve_opt_len[0x6];
668 	u8         geneve_protocol_type[0x10];
669 
670 	u8         reserved_at_140[0x8];
671 	u8         bth_dst_qp[0x18];
672 	u8	   inner_esp_spi[0x20];
673 	u8	   outer_esp_spi[0x20];
674 	u8         reserved_at_1a0[0x60];
675 };
676 
677 struct mlx5_ifc_fte_match_mpls_bits {
678 	u8         mpls_label[0x14];
679 	u8         mpls_exp[0x3];
680 	u8         mpls_s_bos[0x1];
681 	u8         mpls_ttl[0x8];
682 };
683 
684 struct mlx5_ifc_fte_match_set_misc2_bits {
685 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
686 
687 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
688 
689 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
690 
691 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
692 
693 	u8         metadata_reg_c_7[0x20];
694 
695 	u8         metadata_reg_c_6[0x20];
696 
697 	u8         metadata_reg_c_5[0x20];
698 
699 	u8         metadata_reg_c_4[0x20];
700 
701 	u8         metadata_reg_c_3[0x20];
702 
703 	u8         metadata_reg_c_2[0x20];
704 
705 	u8         metadata_reg_c_1[0x20];
706 
707 	u8         metadata_reg_c_0[0x20];
708 
709 	u8         metadata_reg_a[0x20];
710 
711 	u8         psp_syndrome[0x8];
712 	u8         macsec_syndrome[0x8];
713 	u8         ipsec_syndrome[0x8];
714 	u8         ipsec_next_header[0x8];
715 
716 	u8         reserved_at_1c0[0x40];
717 };
718 
719 struct mlx5_ifc_fte_match_set_misc3_bits {
720 	u8         inner_tcp_seq_num[0x20];
721 
722 	u8         outer_tcp_seq_num[0x20];
723 
724 	u8         inner_tcp_ack_num[0x20];
725 
726 	u8         outer_tcp_ack_num[0x20];
727 
728 	u8	   reserved_at_80[0x8];
729 	u8         outer_vxlan_gpe_vni[0x18];
730 
731 	u8         outer_vxlan_gpe_next_protocol[0x8];
732 	u8         outer_vxlan_gpe_flags[0x8];
733 	u8	   reserved_at_b0[0x10];
734 
735 	u8	   icmp_header_data[0x20];
736 
737 	u8	   icmpv6_header_data[0x20];
738 
739 	u8	   icmp_type[0x8];
740 	u8	   icmp_code[0x8];
741 	u8	   icmpv6_type[0x8];
742 	u8	   icmpv6_code[0x8];
743 
744 	u8         geneve_tlv_option_0_data[0x20];
745 
746 	u8	   gtpu_teid[0x20];
747 
748 	u8	   gtpu_msg_type[0x8];
749 	u8	   gtpu_msg_flags[0x8];
750 	u8	   reserved_at_170[0x10];
751 
752 	u8	   gtpu_dw_2[0x20];
753 
754 	u8	   gtpu_first_ext_dw_0[0x20];
755 
756 	u8	   gtpu_dw_0[0x20];
757 
758 	u8	   reserved_at_1e0[0x20];
759 };
760 
761 struct mlx5_ifc_fte_match_set_misc4_bits {
762 	u8         prog_sample_field_value_0[0x20];
763 
764 	u8         prog_sample_field_id_0[0x20];
765 
766 	u8         prog_sample_field_value_1[0x20];
767 
768 	u8         prog_sample_field_id_1[0x20];
769 
770 	u8         prog_sample_field_value_2[0x20];
771 
772 	u8         prog_sample_field_id_2[0x20];
773 
774 	u8         prog_sample_field_value_3[0x20];
775 
776 	u8         prog_sample_field_id_3[0x20];
777 
778 	u8         reserved_at_100[0x100];
779 };
780 
781 struct mlx5_ifc_fte_match_set_misc5_bits {
782 	u8         macsec_tag_0[0x20];
783 
784 	u8         macsec_tag_1[0x20];
785 
786 	u8         macsec_tag_2[0x20];
787 
788 	u8         macsec_tag_3[0x20];
789 
790 	u8         tunnel_header_0[0x20];
791 
792 	u8         tunnel_header_1[0x20];
793 
794 	u8         tunnel_header_2[0x20];
795 
796 	u8         tunnel_header_3[0x20];
797 
798 	u8         reserved_at_100[0x100];
799 };
800 
801 struct mlx5_ifc_cmd_pas_bits {
802 	u8         pa_h[0x20];
803 
804 	u8         pa_l[0x14];
805 	u8         reserved_at_34[0xc];
806 };
807 
808 struct mlx5_ifc_uint64_bits {
809 	u8         hi[0x20];
810 
811 	u8         lo[0x20];
812 };
813 
814 enum {
815 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
816 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
817 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
818 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
819 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
820 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
821 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
822 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
823 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
824 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
825 };
826 
827 struct mlx5_ifc_ads_bits {
828 	u8         fl[0x1];
829 	u8         free_ar[0x1];
830 	u8         reserved_at_2[0xe];
831 	u8         pkey_index[0x10];
832 
833 	u8         plane_index[0x8];
834 	u8         grh[0x1];
835 	u8         mlid[0x7];
836 	u8         rlid[0x10];
837 
838 	u8         ack_timeout[0x5];
839 	u8         reserved_at_45[0x3];
840 	u8         src_addr_index[0x8];
841 	u8         reserved_at_50[0x4];
842 	u8         stat_rate[0x4];
843 	u8         hop_limit[0x8];
844 
845 	u8         reserved_at_60[0x4];
846 	u8         tclass[0x8];
847 	u8         flow_label[0x14];
848 
849 	u8         rgid_rip[16][0x8];
850 
851 	u8         reserved_at_100[0x4];
852 	u8         f_dscp[0x1];
853 	u8         f_ecn[0x1];
854 	u8         reserved_at_106[0x1];
855 	u8         f_eth_prio[0x1];
856 	u8         ecn[0x2];
857 	u8         dscp[0x6];
858 	u8         udp_sport[0x10];
859 
860 	u8         dei_cfi[0x1];
861 	u8         eth_prio[0x3];
862 	u8         sl[0x4];
863 	u8         vhca_port_num[0x8];
864 	u8         rmac_47_32[0x10];
865 
866 	u8         rmac_31_0[0x20];
867 };
868 
869 struct mlx5_ifc_flow_table_nic_cap_bits {
870 	u8         nic_rx_multi_path_tirs[0x1];
871 	u8         nic_rx_multi_path_tirs_fts[0x1];
872 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
873 	u8	   reserved_at_3[0x4];
874 	u8	   sw_owner_reformat_supported[0x1];
875 	u8	   reserved_at_8[0x18];
876 
877 	u8	   encap_general_header[0x1];
878 	u8	   reserved_at_21[0xa];
879 	u8	   log_max_packet_reformat_context[0x5];
880 	u8	   reserved_at_30[0x6];
881 	u8	   max_encap_header_size[0xa];
882 	u8	   reserved_at_40[0x1c0];
883 
884 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
885 
886 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
887 
888 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
889 
890 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
891 
892 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
893 
894 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
895 
896 	u8         reserved_at_e00[0x600];
897 
898 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
899 
900 	u8         reserved_at_1480[0x80];
901 
902 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
903 
904 	u8         reserved_at_1580[0x280];
905 
906 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
907 
908 	u8         reserved_at_1880[0x780];
909 
910 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
911 
912 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
913 
914 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
915 
916 	u8         reserved_at_20c0[0x5f40];
917 };
918 
919 struct mlx5_ifc_port_selection_cap_bits {
920 	u8         reserved_at_0[0x10];
921 	u8         port_select_flow_table[0x1];
922 	u8         reserved_at_11[0x1];
923 	u8         port_select_flow_table_bypass[0x1];
924 	u8         reserved_at_13[0xd];
925 
926 	u8         reserved_at_20[0x1e0];
927 
928 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
929 
930 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
931 
932 	u8         reserved_at_480[0x7b80];
933 };
934 
935 enum {
936 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
937 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
938 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
939 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
940 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
941 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
942 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
943 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
944 };
945 
946 struct mlx5_ifc_flow_table_eswitch_cap_bits {
947 	u8      fdb_to_vport_reg_c_id[0x8];
948 	u8      reserved_at_8[0x5];
949 	u8      fdb_uplink_hairpin[0x1];
950 	u8      fdb_multi_path_any_table_limit_regc[0x1];
951 	u8      reserved_at_f[0x1];
952 	u8      fdb_dynamic_tunnel[0x1];
953 	u8      reserved_at_11[0x1];
954 	u8      fdb_multi_path_any_table[0x1];
955 	u8      reserved_at_13[0x2];
956 	u8      fdb_modify_header_fwd_to_table[0x1];
957 	u8      fdb_ipv4_ttl_modify[0x1];
958 	u8      flow_source[0x1];
959 	u8      reserved_at_18[0x2];
960 	u8      multi_fdb_encap[0x1];
961 	u8      egress_acl_forward_to_vport[0x1];
962 	u8      fdb_multi_path_to_table[0x1];
963 	u8      reserved_at_1d[0x3];
964 
965 	u8      reserved_at_20[0x1e0];
966 
967 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
968 
969 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
970 
971 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
972 
973 	u8      reserved_at_800[0xC00];
974 
975 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
976 
977 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
978 
979 	u8      reserved_at_1500[0x300];
980 
981 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
982 
983 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
984 
985 	u8      sw_steering_uplink_icm_address_rx[0x40];
986 
987 	u8      sw_steering_uplink_icm_address_tx[0x40];
988 
989 	u8      reserved_at_1900[0x6700];
990 };
991 
992 struct mlx5_ifc_wqe_based_flow_table_cap_bits {
993 	u8         reserved_at_0[0x3];
994 	u8         log_max_num_ste[0x5];
995 	u8         reserved_at_8[0x3];
996 	u8         log_max_num_stc[0x5];
997 	u8         reserved_at_10[0x3];
998 	u8         log_max_num_rtc[0x5];
999 	u8         reserved_at_18[0x3];
1000 	u8         log_max_num_header_modify_pattern[0x5];
1001 
1002 	u8         rtc_hash_split_table[0x1];
1003 	u8         rtc_linear_lookup_table[0x1];
1004 	u8         reserved_at_22[0x1];
1005 	u8         stc_alloc_log_granularity[0x5];
1006 	u8         reserved_at_28[0x3];
1007 	u8         stc_alloc_log_max[0x5];
1008 	u8         reserved_at_30[0x3];
1009 	u8         ste_alloc_log_granularity[0x5];
1010 	u8         reserved_at_38[0x3];
1011 	u8         ste_alloc_log_max[0x5];
1012 
1013 	u8         reserved_at_40[0xb];
1014 	u8         rtc_reparse_mode[0x5];
1015 	u8         reserved_at_50[0x3];
1016 	u8         rtc_index_mode[0x5];
1017 	u8         reserved_at_58[0x3];
1018 	u8         rtc_log_depth_max[0x5];
1019 
1020 	u8         reserved_at_60[0x10];
1021 	u8         ste_format[0x10];
1022 
1023 	u8         stc_action_type[0x80];
1024 
1025 	u8         header_insert_type[0x10];
1026 	u8         header_remove_type[0x10];
1027 
1028 	u8         trivial_match_definer[0x20];
1029 
1030 	u8         reserved_at_140[0x1b];
1031 	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1032 
1033 	u8         reserved_at_160[0x18];
1034 	u8         access_index_mode[0x8];
1035 
1036 	u8         reserved_at_180[0x10];
1037 	u8         ste_format_gen_wqe[0x10];
1038 
1039 	u8         linear_match_definer_reg_c3[0x20];
1040 
1041 	u8         fdb_jump_to_tir_stc[0x1];
1042 	u8         reserved_at_1c1[0x1f];
1043 };
1044 
1045 struct mlx5_ifc_esw_cap_bits {
1046 	u8         reserved_at_0[0x1d];
1047 	u8         merged_eswitch[0x1];
1048 	u8         reserved_at_1e[0x2];
1049 
1050 	u8         reserved_at_20[0x40];
1051 
1052 	u8         esw_manager_vport_number_valid[0x1];
1053 	u8         reserved_at_61[0xf];
1054 	u8         esw_manager_vport_number[0x10];
1055 
1056 	u8         reserved_at_80[0x780];
1057 };
1058 
1059 enum {
1060 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1061 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1062 };
1063 
1064 struct mlx5_ifc_e_switch_cap_bits {
1065 	u8         vport_svlan_strip[0x1];
1066 	u8         vport_cvlan_strip[0x1];
1067 	u8         vport_svlan_insert[0x1];
1068 	u8         vport_cvlan_insert_if_not_exist[0x1];
1069 	u8         vport_cvlan_insert_overwrite[0x1];
1070 	u8         reserved_at_5[0x1];
1071 	u8         vport_cvlan_insert_always[0x1];
1072 	u8         esw_shared_ingress_acl[0x1];
1073 	u8         esw_uplink_ingress_acl[0x1];
1074 	u8         root_ft_on_other_esw[0x1];
1075 	u8         reserved_at_a[0x1];
1076 	u8         esw_vport_state_max_tx_speed[0x1];
1077 	u8         reserved_at_c[0xd];
1078 	u8         esw_functions_changed[0x1];
1079 	u8         reserved_at_1a[0x1];
1080 	u8         ecpf_vport_exists[0x1];
1081 	u8         counter_eswitch_affinity[0x1];
1082 	u8         merged_eswitch[0x1];
1083 	u8         nic_vport_node_guid_modify[0x1];
1084 	u8         nic_vport_port_guid_modify[0x1];
1085 
1086 	u8         vxlan_encap_decap[0x1];
1087 	u8         nvgre_encap_decap[0x1];
1088 	u8         reserved_at_22[0x1];
1089 	u8         log_max_fdb_encap_uplink[0x5];
1090 	u8         reserved_at_21[0x3];
1091 	u8         log_max_packet_reformat_context[0x5];
1092 	u8         reserved_2b[0x6];
1093 	u8         max_encap_header_size[0xa];
1094 
1095 	u8         reserved_at_40[0xb];
1096 	u8         log_max_esw_sf[0x5];
1097 	u8         esw_sf_base_id[0x10];
1098 
1099 	u8         reserved_at_60[0x7a0];
1100 
1101 };
1102 
1103 struct mlx5_ifc_qos_cap_bits {
1104 	u8         packet_pacing[0x1];
1105 	u8         esw_scheduling[0x1];
1106 	u8         esw_bw_share[0x1];
1107 	u8         esw_rate_limit[0x1];
1108 	u8         reserved_at_4[0x1];
1109 	u8         packet_pacing_burst_bound[0x1];
1110 	u8         packet_pacing_typical_size[0x1];
1111 	u8         reserved_at_7[0x1];
1112 	u8         nic_sq_scheduling[0x1];
1113 	u8         nic_bw_share[0x1];
1114 	u8         nic_rate_limit[0x1];
1115 	u8         packet_pacing_uid[0x1];
1116 	u8         log_esw_max_sched_depth[0x4];
1117 	u8         reserved_at_10[0x10];
1118 
1119 	u8         reserved_at_20[0x9];
1120 	u8         esw_cross_esw_sched[0x1];
1121 	u8         reserved_at_2a[0x1];
1122 	u8         log_max_qos_nic_queue_group[0x5];
1123 	u8         reserved_at_30[0x10];
1124 
1125 	u8         packet_pacing_max_rate[0x20];
1126 
1127 	u8         packet_pacing_min_rate[0x20];
1128 
1129 	u8         reserved_at_80[0xb];
1130 	u8         log_esw_max_rate_limit[0x5];
1131 	u8         packet_pacing_rate_table_size[0x10];
1132 
1133 	u8         esw_element_type[0x10];
1134 	u8         esw_tsar_type[0x10];
1135 
1136 	u8         reserved_at_c0[0x10];
1137 	u8         max_qos_para_vport[0x10];
1138 
1139 	u8         max_tsar_bw_share[0x20];
1140 
1141 	u8         nic_element_type[0x10];
1142 	u8         nic_tsar_type[0x10];
1143 
1144 	u8         reserved_at_120[0x3];
1145 	u8         log_meter_aso_granularity[0x5];
1146 	u8         reserved_at_128[0x3];
1147 	u8         log_meter_aso_max_alloc[0x5];
1148 	u8         reserved_at_130[0x3];
1149 	u8         log_max_num_meter_aso[0x5];
1150 	u8         reserved_at_138[0x8];
1151 
1152 	u8         reserved_at_140[0x6c0];
1153 };
1154 
1155 struct mlx5_ifc_debug_cap_bits {
1156 	u8         core_dump_general[0x1];
1157 	u8         core_dump_qp[0x1];
1158 	u8         reserved_at_2[0x7];
1159 	u8         resource_dump[0x1];
1160 	u8         reserved_at_a[0x16];
1161 
1162 	u8         reserved_at_20[0x2];
1163 	u8         stall_detect[0x1];
1164 	u8         reserved_at_23[0x1d];
1165 
1166 	u8         reserved_at_40[0x7c0];
1167 };
1168 
1169 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1170 	u8         csum_cap[0x1];
1171 	u8         vlan_cap[0x1];
1172 	u8         lro_cap[0x1];
1173 	u8         lro_psh_flag[0x1];
1174 	u8         lro_time_stamp[0x1];
1175 	u8         reserved_at_5[0x2];
1176 	u8         wqe_vlan_insert[0x1];
1177 	u8         self_lb_en_modifiable[0x1];
1178 	u8         reserved_at_9[0x2];
1179 	u8         max_lso_cap[0x5];
1180 	u8         multi_pkt_send_wqe[0x2];
1181 	u8	   wqe_inline_mode[0x2];
1182 	u8         rss_ind_tbl_cap[0x4];
1183 	u8         reg_umr_sq[0x1];
1184 	u8         scatter_fcs[0x1];
1185 	u8         enhanced_multi_pkt_send_wqe[0x1];
1186 	u8         tunnel_lso_const_out_ip_id[0x1];
1187 	u8         tunnel_lro_gre[0x1];
1188 	u8         tunnel_lro_vxlan[0x1];
1189 	u8         tunnel_stateless_gre[0x1];
1190 	u8         tunnel_stateless_vxlan[0x1];
1191 
1192 	u8         swp[0x1];
1193 	u8         swp_csum[0x1];
1194 	u8         swp_lso[0x1];
1195 	u8         cqe_checksum_full[0x1];
1196 	u8         tunnel_stateless_geneve_tx[0x1];
1197 	u8         tunnel_stateless_mpls_over_udp[0x1];
1198 	u8         tunnel_stateless_mpls_over_gre[0x1];
1199 	u8         tunnel_stateless_vxlan_gpe[0x1];
1200 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1201 	u8         tunnel_stateless_ip_over_ip[0x1];
1202 	u8         insert_trailer[0x1];
1203 	u8         reserved_at_2b[0x1];
1204 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1205 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1206 	u8         reserved_at_2e[0x2];
1207 	u8         max_vxlan_udp_ports[0x8];
1208 	u8         swp_csum_l4_partial[0x1];
1209 	u8         reserved_at_39[0x5];
1210 	u8         max_geneve_opt_len[0x1];
1211 	u8         tunnel_stateless_geneve_rx[0x1];
1212 
1213 	u8         reserved_at_40[0x10];
1214 	u8         lro_min_mss_size[0x10];
1215 
1216 	u8         reserved_at_60[0x120];
1217 
1218 	u8         lro_timer_supported_periods[4][0x20];
1219 
1220 	u8         reserved_at_200[0x600];
1221 };
1222 
1223 enum {
1224 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1225 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1226 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1227 };
1228 
1229 struct mlx5_ifc_roce_cap_bits {
1230 	u8         roce_apm[0x1];
1231 	u8         reserved_at_1[0x3];
1232 	u8         sw_r_roce_src_udp_port[0x1];
1233 	u8         fl_rc_qp_when_roce_disabled[0x1];
1234 	u8         fl_rc_qp_when_roce_enabled[0x1];
1235 	u8         roce_cc_general[0x1];
1236 	u8	   qp_ooo_transmit_default[0x1];
1237 	u8         reserved_at_9[0x15];
1238 	u8	   qp_ts_format[0x2];
1239 
1240 	u8         reserved_at_20[0x60];
1241 
1242 	u8         reserved_at_80[0xc];
1243 	u8         l3_type[0x4];
1244 	u8         reserved_at_90[0x8];
1245 	u8         roce_version[0x8];
1246 
1247 	u8         reserved_at_a0[0x10];
1248 	u8         r_roce_dest_udp_port[0x10];
1249 
1250 	u8         r_roce_max_src_udp_port[0x10];
1251 	u8         r_roce_min_src_udp_port[0x10];
1252 
1253 	u8         reserved_at_e0[0x10];
1254 	u8         roce_address_table_size[0x10];
1255 
1256 	u8         reserved_at_100[0x700];
1257 };
1258 
1259 struct mlx5_ifc_sync_steering_in_bits {
1260 	u8         opcode[0x10];
1261 	u8         uid[0x10];
1262 
1263 	u8         reserved_at_20[0x10];
1264 	u8         op_mod[0x10];
1265 
1266 	u8         reserved_at_40[0xc0];
1267 };
1268 
1269 struct mlx5_ifc_sync_steering_out_bits {
1270 	u8         status[0x8];
1271 	u8         reserved_at_8[0x18];
1272 
1273 	u8         syndrome[0x20];
1274 
1275 	u8         reserved_at_40[0x40];
1276 };
1277 
1278 struct mlx5_ifc_sync_crypto_in_bits {
1279 	u8         opcode[0x10];
1280 	u8         uid[0x10];
1281 
1282 	u8         reserved_at_20[0x10];
1283 	u8         op_mod[0x10];
1284 
1285 	u8         reserved_at_40[0x20];
1286 
1287 	u8         reserved_at_60[0x10];
1288 	u8         crypto_type[0x10];
1289 
1290 	u8         reserved_at_80[0x80];
1291 };
1292 
1293 struct mlx5_ifc_sync_crypto_out_bits {
1294 	u8         status[0x8];
1295 	u8         reserved_at_8[0x18];
1296 
1297 	u8         syndrome[0x20];
1298 
1299 	u8         reserved_at_40[0x40];
1300 };
1301 
1302 struct mlx5_ifc_device_mem_cap_bits {
1303 	u8         memic[0x1];
1304 	u8         reserved_at_1[0x1f];
1305 
1306 	u8         reserved_at_20[0xb];
1307 	u8         log_min_memic_alloc_size[0x5];
1308 	u8         reserved_at_30[0x8];
1309 	u8	   log_max_memic_addr_alignment[0x8];
1310 
1311 	u8         memic_bar_start_addr[0x40];
1312 
1313 	u8         memic_bar_size[0x20];
1314 
1315 	u8         max_memic_size[0x20];
1316 
1317 	u8         steering_sw_icm_start_address[0x40];
1318 
1319 	u8         reserved_at_100[0x8];
1320 	u8         log_header_modify_sw_icm_size[0x8];
1321 	u8         reserved_at_110[0x2];
1322 	u8         log_sw_icm_alloc_granularity[0x6];
1323 	u8         log_steering_sw_icm_size[0x8];
1324 
1325 	u8         log_indirect_encap_sw_icm_size[0x8];
1326 	u8         reserved_at_128[0x10];
1327 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1328 
1329 	u8         header_modify_sw_icm_start_address[0x40];
1330 
1331 	u8         reserved_at_180[0x40];
1332 
1333 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1334 
1335 	u8         memic_operations[0x20];
1336 
1337 	u8         reserved_at_220[0x20];
1338 
1339 	u8         indirect_encap_sw_icm_start_address[0x40];
1340 
1341 	u8         reserved_at_280[0x580];
1342 };
1343 
1344 struct mlx5_ifc_device_event_cap_bits {
1345 	u8         user_affiliated_events[4][0x40];
1346 
1347 	u8         user_unaffiliated_events[4][0x40];
1348 };
1349 
1350 struct mlx5_ifc_virtio_emulation_cap_bits {
1351 	u8         desc_tunnel_offload_type[0x1];
1352 	u8         eth_frame_offload_type[0x1];
1353 	u8         virtio_version_1_0[0x1];
1354 	u8         device_features_bits_mask[0xd];
1355 	u8         event_mode[0x8];
1356 	u8         virtio_queue_type[0x8];
1357 
1358 	u8         max_tunnel_desc[0x10];
1359 	u8         reserved_at_30[0x3];
1360 	u8         log_doorbell_stride[0x5];
1361 	u8         reserved_at_38[0x3];
1362 	u8         log_doorbell_bar_size[0x5];
1363 
1364 	u8         doorbell_bar_offset[0x40];
1365 
1366 	u8         max_emulated_devices[0x8];
1367 	u8         max_num_virtio_queues[0x18];
1368 
1369 	u8         reserved_at_a0[0x20];
1370 
1371 	u8	   reserved_at_c0[0x13];
1372 	u8         desc_group_mkey_supported[0x1];
1373 	u8         freeze_to_rdy_supported[0x1];
1374 	u8         reserved_at_d5[0xb];
1375 
1376 	u8         reserved_at_e0[0x20];
1377 
1378 	u8         umem_1_buffer_param_a[0x20];
1379 
1380 	u8         umem_1_buffer_param_b[0x20];
1381 
1382 	u8         umem_2_buffer_param_a[0x20];
1383 
1384 	u8         umem_2_buffer_param_b[0x20];
1385 
1386 	u8         umem_3_buffer_param_a[0x20];
1387 
1388 	u8         umem_3_buffer_param_b[0x20];
1389 
1390 	u8         reserved_at_1c0[0x640];
1391 };
1392 
1393 struct mlx5_ifc_tlp_dev_emu_capabilities_bits {
1394 	u8         reserved_at_0[0x20];
1395 
1396 	u8         reserved_at_20[0x13];
1397 	u8         log_tlp_rsp_gw_page_stride[0x5];
1398 	u8         reserved_at_38[0x8];
1399 
1400 	u8         reserved_at_40[0xc0];
1401 
1402 	u8         reserved_at_100[0xc];
1403 	u8         tlp_rsp_gw_num_pages[0x4];
1404 	u8         reserved_at_110[0x10];
1405 
1406 	u8         reserved_at_120[0xa0];
1407 
1408 	u8         tlp_rsp_gw_pages_bar_offset[0x40];
1409 
1410 	u8         reserved_at_200[0x600];
1411 };
1412 
1413 enum {
1414 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1415 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1416 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1417 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1418 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1419 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1420 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1421 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1422 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1423 };
1424 
1425 enum {
1426 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1427 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1428 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1429 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1430 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1431 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1432 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1433 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1434 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1435 };
1436 
1437 struct mlx5_ifc_atomic_caps_bits {
1438 	u8         reserved_at_0[0x40];
1439 
1440 	u8         atomic_req_8B_endianness_mode[0x2];
1441 	u8         reserved_at_42[0x4];
1442 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1443 
1444 	u8         reserved_at_47[0x19];
1445 
1446 	u8         reserved_at_60[0x20];
1447 
1448 	u8         reserved_at_80[0x10];
1449 	u8         atomic_operations[0x10];
1450 
1451 	u8         reserved_at_a0[0x10];
1452 	u8         atomic_size_qp[0x10];
1453 
1454 	u8         reserved_at_c0[0x10];
1455 	u8         atomic_size_dc[0x10];
1456 
1457 	u8         reserved_at_e0[0x720];
1458 };
1459 
1460 struct mlx5_ifc_odp_scheme_cap_bits {
1461 	u8         reserved_at_0[0x40];
1462 
1463 	u8         sig[0x1];
1464 	u8         reserved_at_41[0x4];
1465 	u8         page_prefetch[0x1];
1466 	u8         reserved_at_46[0x1a];
1467 
1468 	u8         reserved_at_60[0x20];
1469 
1470 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1471 
1472 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1473 
1474 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1475 
1476 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1477 
1478 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1479 
1480 	u8         reserved_at_120[0xe0];
1481 };
1482 
1483 struct mlx5_ifc_odp_cap_bits {
1484 	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1485 
1486 	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1487 
1488 	u8         reserved_at_400[0x200];
1489 
1490 	u8         mem_page_fault[0x1];
1491 	u8         reserved_at_601[0x1f];
1492 
1493 	u8         reserved_at_620[0x1e0];
1494 };
1495 
1496 struct mlx5_ifc_tls_cap_bits {
1497 	u8         tls_1_2_aes_gcm_128[0x1];
1498 	u8         tls_1_3_aes_gcm_128[0x1];
1499 	u8         tls_1_2_aes_gcm_256[0x1];
1500 	u8         tls_1_3_aes_gcm_256[0x1];
1501 	u8         reserved_at_4[0x1c];
1502 
1503 	u8         reserved_at_20[0x7e0];
1504 };
1505 
1506 struct mlx5_ifc_ipsec_cap_bits {
1507 	u8         ipsec_full_offload[0x1];
1508 	u8         ipsec_crypto_offload[0x1];
1509 	u8         ipsec_esn[0x1];
1510 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1511 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1512 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1513 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1514 	u8         reserved_at_7[0x4];
1515 	u8         log_max_ipsec_offload[0x5];
1516 	u8         reserved_at_10[0x10];
1517 
1518 	u8         min_log_ipsec_full_replay_window[0x8];
1519 	u8         max_log_ipsec_full_replay_window[0x8];
1520 	u8         reserved_at_30[0x7d0];
1521 };
1522 
1523 struct mlx5_ifc_macsec_cap_bits {
1524 	u8    macsec_epn[0x1];
1525 	u8    reserved_at_1[0x2];
1526 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1527 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1528 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1529 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1530 	u8    reserved_at_7[0x4];
1531 	u8    log_max_macsec_offload[0x5];
1532 	u8    reserved_at_10[0x10];
1533 
1534 	u8    min_log_macsec_full_replay_window[0x8];
1535 	u8    max_log_macsec_full_replay_window[0x8];
1536 	u8    reserved_at_30[0x10];
1537 
1538 	u8    reserved_at_40[0x7c0];
1539 };
1540 
1541 struct mlx5_ifc_psp_cap_bits {
1542 	u8         reserved_at_0[0x1];
1543 	u8         psp_crypto_offload[0x1];
1544 	u8         reserved_at_2[0x1];
1545 	u8         psp_crypto_esp_aes_gcm_256_encrypt[0x1];
1546 	u8         psp_crypto_esp_aes_gcm_128_encrypt[0x1];
1547 	u8         psp_crypto_esp_aes_gcm_256_decrypt[0x1];
1548 	u8         psp_crypto_esp_aes_gcm_128_decrypt[0x1];
1549 	u8         reserved_at_7[0x4];
1550 	u8         log_max_num_of_psp_spi[0x5];
1551 	u8         reserved_at_10[0x10];
1552 
1553 	u8         reserved_at_20[0x7e0];
1554 };
1555 
1556 enum {
1557 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1558 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1559 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1560 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1561 };
1562 
1563 enum {
1564 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1565 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1566 };
1567 
1568 enum {
1569 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1570 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1571 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1572 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1573 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1574 };
1575 
1576 enum {
1577 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1578 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1579 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1580 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1581 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1582 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1583 };
1584 
1585 enum {
1586 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1587 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1588 };
1589 
1590 enum {
1591 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1592 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1593 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1594 };
1595 
1596 enum {
1597 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1598 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1599 };
1600 
1601 enum {
1602 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1603 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1604 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1605 };
1606 
1607 enum {
1608 	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1609 	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1610 	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1611 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1612 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1613 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1614 	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1615 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1616 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1617 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1618 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1619 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1620 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1621 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1622 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1623 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1624 };
1625 
1626 enum {
1627 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1628 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1629 	MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
1630 	MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
1631 };
1632 
1633 #define MLX5_FC_BULK_SIZE_FACTOR 128
1634 
1635 enum mlx5_fc_bulk_alloc_bitmask {
1636 	MLX5_FC_BULK_128   = (1 << 0),
1637 	MLX5_FC_BULK_256   = (1 << 1),
1638 	MLX5_FC_BULK_512   = (1 << 2),
1639 	MLX5_FC_BULK_1024  = (1 << 3),
1640 	MLX5_FC_BULK_2048  = (1 << 4),
1641 	MLX5_FC_BULK_4096  = (1 << 5),
1642 	MLX5_FC_BULK_8192  = (1 << 6),
1643 	MLX5_FC_BULK_16384 = (1 << 7),
1644 };
1645 
1646 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1647 
1648 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1649 
1650 enum {
1651 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1652 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1653 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1654 	MLX5_STEERING_FORMAT_CONNECTX_8   = 3,
1655 };
1656 
1657 enum {
1658 	MLX5_ID_MODE_FUNCTION_INDEX   = 0,
1659 	MLX5_ID_MODE_FUNCTION_VHCA_ID = 1,
1660 };
1661 
1662 struct mlx5_ifc_cmd_hca_cap_bits {
1663 	u8         reserved_at_0[0x6];
1664 	u8         page_request_disable[0x1];
1665 	u8         abs_native_port_num[0x1];
1666 	u8         reserved_at_8[0x8];
1667 	u8         shared_object_to_user_object_allowed[0x1];
1668 	u8         reserved_at_13[0xe];
1669 	u8         vhca_resource_manager[0x1];
1670 
1671 	u8         hca_cap_2[0x1];
1672 	u8         create_lag_when_not_master_up[0x1];
1673 	u8         dtor[0x1];
1674 	u8         event_on_vhca_state_teardown_request[0x1];
1675 	u8         event_on_vhca_state_in_use[0x1];
1676 	u8         event_on_vhca_state_active[0x1];
1677 	u8         event_on_vhca_state_allocated[0x1];
1678 	u8         event_on_vhca_state_invalid[0x1];
1679 	u8         reserved_at_28[0x8];
1680 	u8         vhca_id[0x10];
1681 
1682 	u8         reserved_at_40[0x40];
1683 
1684 	u8         log_max_srq_sz[0x8];
1685 	u8         log_max_qp_sz[0x8];
1686 	u8         event_cap[0x1];
1687 	u8         reserved_at_91[0x2];
1688 	u8         isolate_vl_tc_new[0x1];
1689 	u8         reserved_at_94[0x4];
1690 	u8         prio_tag_required[0x1];
1691 	u8         reserved_at_99[0x2];
1692 	u8         log_max_qp[0x5];
1693 
1694 	u8         reserved_at_a0[0x3];
1695 	u8	   ece_support[0x1];
1696 	u8	   reserved_at_a4[0x5];
1697 	u8         reg_c_preserve[0x1];
1698 	u8         reserved_at_aa[0x1];
1699 	u8         log_max_srq[0x5];
1700 	u8         reserved_at_b0[0x1];
1701 	u8         uplink_follow[0x1];
1702 	u8         ts_cqe_to_dest_cqn[0x1];
1703 	u8         reserved_at_b3[0x6];
1704 	u8         go_back_n[0x1];
1705 	u8         reserved_at_ba[0x6];
1706 
1707 	u8         max_sgl_for_optimized_performance[0x8];
1708 	u8         log_max_cq_sz[0x8];
1709 	u8         relaxed_ordering_write_umr[0x1];
1710 	u8         relaxed_ordering_read_umr[0x1];
1711 	u8         reserved_at_d2[0x7];
1712 	u8         virtio_net_device_emualtion_manager[0x1];
1713 	u8         virtio_blk_device_emualtion_manager[0x1];
1714 	u8         log_max_cq[0x5];
1715 
1716 	u8         log_max_eq_sz[0x8];
1717 	u8         relaxed_ordering_write[0x1];
1718 	u8         relaxed_ordering_read_pci_enabled[0x1];
1719 	u8         log_max_mkey[0x6];
1720 	u8         reserved_at_f0[0x6];
1721 	u8	   terminate_scatter_list_mkey[0x1];
1722 	u8	   repeated_mkey[0x1];
1723 	u8         dump_fill_mkey[0x1];
1724 	u8         reserved_at_f9[0x2];
1725 	u8         fast_teardown[0x1];
1726 	u8         log_max_eq[0x4];
1727 
1728 	u8         max_indirection[0x8];
1729 	u8         fixed_buffer_size[0x1];
1730 	u8         log_max_mrw_sz[0x7];
1731 	u8         force_teardown[0x1];
1732 	u8         reserved_at_111[0x1];
1733 	u8         log_max_bsf_list_size[0x6];
1734 	u8         umr_extended_translation_offset[0x1];
1735 	u8         null_mkey[0x1];
1736 	u8         log_max_klm_list_size[0x6];
1737 
1738 	u8         reserved_at_120[0x2];
1739 	u8	   qpc_extension[0x1];
1740 	u8	   reserved_at_123[0x7];
1741 	u8         log_max_ra_req_dc[0x6];
1742 	u8         reserved_at_130[0x2];
1743 	u8         eth_wqe_too_small[0x1];
1744 	u8         reserved_at_133[0x6];
1745 	u8         vnic_env_cq_overrun[0x1];
1746 	u8         log_max_ra_res_dc[0x6];
1747 
1748 	u8         reserved_at_140[0x5];
1749 	u8         release_all_pages[0x1];
1750 	u8         must_not_use[0x1];
1751 	u8         reserved_at_147[0x2];
1752 	u8         roce_accl[0x1];
1753 	u8         log_max_ra_req_qp[0x6];
1754 	u8         reserved_at_150[0xa];
1755 	u8         log_max_ra_res_qp[0x6];
1756 
1757 	u8         end_pad[0x1];
1758 	u8         cc_query_allowed[0x1];
1759 	u8         cc_modify_allowed[0x1];
1760 	u8         start_pad[0x1];
1761 	u8         cache_line_128byte[0x1];
1762 	u8         reserved_at_165[0x4];
1763 	u8         rts2rts_qp_counters_set_id[0x1];
1764 	u8         reserved_at_16a[0x2];
1765 	u8         vnic_env_int_rq_oob[0x1];
1766 	u8         sbcam_reg[0x1];
1767 	u8         reserved_at_16e[0x1];
1768 	u8         qcam_reg[0x1];
1769 	u8         gid_table_size[0x10];
1770 
1771 	u8         out_of_seq_cnt[0x1];
1772 	u8         vport_counters[0x1];
1773 	u8         retransmission_q_counters[0x1];
1774 	u8         debug[0x1];
1775 	u8         modify_rq_counter_set_id[0x1];
1776 	u8         rq_delay_drop[0x1];
1777 	u8         max_qp_cnt[0xa];
1778 	u8         pkey_table_size[0x10];
1779 
1780 	u8         vport_group_manager[0x1];
1781 	u8         vhca_group_manager[0x1];
1782 	u8         ib_virt[0x1];
1783 	u8         eth_virt[0x1];
1784 	u8         vnic_env_queue_counters[0x1];
1785 	u8         ets[0x1];
1786 	u8         nic_flow_table[0x1];
1787 	u8         eswitch_manager[0x1];
1788 	u8         device_memory[0x1];
1789 	u8         mcam_reg[0x1];
1790 	u8         pcam_reg[0x1];
1791 	u8         local_ca_ack_delay[0x5];
1792 	u8         port_module_event[0x1];
1793 	u8         enhanced_error_q_counters[0x1];
1794 	u8         ports_check[0x1];
1795 	u8         reserved_at_1b3[0x1];
1796 	u8         disable_link_up[0x1];
1797 	u8         beacon_led[0x1];
1798 	u8         port_type[0x2];
1799 	u8         num_ports[0x8];
1800 
1801 	u8         reserved_at_1c0[0x1];
1802 	u8         pps[0x1];
1803 	u8         pps_modify[0x1];
1804 	u8         log_max_msg[0x5];
1805 	u8         reserved_at_1c8[0x4];
1806 	u8         max_tc[0x4];
1807 	u8         temp_warn_event[0x1];
1808 	u8         dcbx[0x1];
1809 	u8         general_notification_event[0x1];
1810 	u8         reserved_at_1d3[0x2];
1811 	u8         fpga[0x1];
1812 	u8         rol_s[0x1];
1813 	u8         rol_g[0x1];
1814 	u8         reserved_at_1d8[0x1];
1815 	u8         wol_s[0x1];
1816 	u8         wol_g[0x1];
1817 	u8         wol_a[0x1];
1818 	u8         wol_b[0x1];
1819 	u8         wol_m[0x1];
1820 	u8         wol_u[0x1];
1821 	u8         wol_p[0x1];
1822 
1823 	u8         stat_rate_support[0x10];
1824 	u8         reserved_at_1f0[0x1];
1825 	u8         pci_sync_for_fw_update_event[0x1];
1826 	u8         reserved_at_1f2[0x6];
1827 	u8         init2_lag_tx_port_affinity[0x1];
1828 	u8         reserved_at_1fa[0x2];
1829 	u8         wqe_based_flow_table_update_cap[0x1];
1830 	u8         cqe_version[0x4];
1831 
1832 	u8         compact_address_vector[0x1];
1833 	u8         striding_rq[0x1];
1834 	u8         reserved_at_202[0x1];
1835 	u8         ipoib_enhanced_offloads[0x1];
1836 	u8         ipoib_basic_offloads[0x1];
1837 	u8         reserved_at_205[0x1];
1838 	u8         repeated_block_disabled[0x1];
1839 	u8         umr_modify_entity_size_disabled[0x1];
1840 	u8         umr_modify_atomic_disabled[0x1];
1841 	u8         umr_indirect_mkey_disabled[0x1];
1842 	u8         umr_fence[0x2];
1843 	u8         dc_req_scat_data_cqe[0x1];
1844 	u8         reserved_at_20d[0x2];
1845 	u8         drain_sigerr[0x1];
1846 	u8         cmdif_checksum[0x2];
1847 	u8         sigerr_cqe[0x1];
1848 	u8         reserved_at_213[0x1];
1849 	u8         wq_signature[0x1];
1850 	u8         sctr_data_cqe[0x1];
1851 	u8         reserved_at_216[0x1];
1852 	u8         sho[0x1];
1853 	u8         tph[0x1];
1854 	u8         rf[0x1];
1855 	u8         dct[0x1];
1856 	u8         qos[0x1];
1857 	u8         eth_net_offloads[0x1];
1858 	u8         roce[0x1];
1859 	u8         atomic[0x1];
1860 	u8         reserved_at_21f[0x1];
1861 
1862 	u8         cq_oi[0x1];
1863 	u8         cq_resize[0x1];
1864 	u8         cq_moderation[0x1];
1865 	u8         cq_period_mode_modify[0x1];
1866 	u8         reserved_at_224[0x2];
1867 	u8         cq_eq_remap[0x1];
1868 	u8         pg[0x1];
1869 	u8         block_lb_mc[0x1];
1870 	u8         reserved_at_229[0x1];
1871 	u8         scqe_break_moderation[0x1];
1872 	u8         cq_period_start_from_cqe[0x1];
1873 	u8         cd[0x1];
1874 	u8         reserved_at_22d[0x1];
1875 	u8         apm[0x1];
1876 	u8         vector_calc[0x1];
1877 	u8         umr_ptr_rlky[0x1];
1878 	u8	   imaicl[0x1];
1879 	u8	   qp_packet_based[0x1];
1880 	u8         reserved_at_233[0x3];
1881 	u8         qkv[0x1];
1882 	u8         pkv[0x1];
1883 	u8         set_deth_sqpn[0x1];
1884 	u8         reserved_at_239[0x3];
1885 	u8         xrc[0x1];
1886 	u8         ud[0x1];
1887 	u8         uc[0x1];
1888 	u8         rc[0x1];
1889 
1890 	u8         uar_4k[0x1];
1891 	u8         reserved_at_241[0x7];
1892 	u8         fl_rc_qp_when_roce_disabled[0x1];
1893 	u8         regexp_params[0x1];
1894 	u8         uar_sz[0x6];
1895 	u8         port_selection_cap[0x1];
1896 	u8         nic_cap_reg[0x1];
1897 	u8         umem_uid_0[0x1];
1898 	u8         reserved_at_253[0x5];
1899 	u8         log_pg_sz[0x8];
1900 
1901 	u8         bf[0x1];
1902 	u8         driver_version[0x1];
1903 	u8         pad_tx_eth_packet[0x1];
1904 	u8         reserved_at_263[0x3];
1905 	u8         mkey_by_name[0x1];
1906 	u8         reserved_at_267[0x4];
1907 
1908 	u8         log_bf_reg_size[0x5];
1909 
1910 	u8         disciplined_fr_counter[0x1];
1911 	u8         reserved_at_271[0x2];
1912 	u8	   qp_error_syndrome[0x1];
1913 	u8	   reserved_at_274[0x2];
1914 	u8         lag_dct[0x2];
1915 	u8         lag_tx_port_affinity[0x1];
1916 	u8         lag_native_fdb_selection[0x1];
1917 	u8         reserved_at_27a[0x1];
1918 	u8         lag_master[0x1];
1919 	u8         num_lag_ports[0x4];
1920 
1921 	u8         reserved_at_280[0x10];
1922 	u8         max_wqe_sz_sq[0x10];
1923 
1924 	u8         icm_mng_function_id_mode[0x1];
1925 	u8         reserved_at_2a1[0x6];
1926 	u8         mkey_pcie_tph[0x1];
1927 	u8         reserved_at_2a8[0x1];
1928 	u8         tis_tir_td_order[0x1];
1929 
1930 	u8         psp[0x1];
1931 	u8         shampo[0x1];
1932 	u8         reserved_at_2ac[0x4];
1933 	u8         max_wqe_sz_rq[0x10];
1934 
1935 	u8         max_flow_counter_31_16[0x10];
1936 	u8         max_wqe_sz_sq_dc[0x10];
1937 
1938 	u8         reserved_at_2e0[0x7];
1939 	u8         max_qp_mcg[0x19];
1940 
1941 	u8         reserved_at_300[0x10];
1942 	u8         flow_counter_bulk_alloc[0x8];
1943 	u8         log_max_mcg[0x8];
1944 
1945 	u8         reserved_at_320[0x3];
1946 	u8         log_max_transport_domain[0x5];
1947 	u8         reserved_at_328[0x2];
1948 	u8	   relaxed_ordering_read[0x1];
1949 	u8         log_max_pd[0x5];
1950 	u8         dp_ordering_ooo_all_ud[0x1];
1951 	u8         dp_ordering_ooo_all_uc[0x1];
1952 	u8         dp_ordering_ooo_all_xrc[0x1];
1953 	u8         dp_ordering_ooo_all_dc[0x1];
1954 	u8         dp_ordering_ooo_all_rc[0x1];
1955 	u8         pcie_reset_using_hotreset_method[0x1];
1956 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1957 	u8         vnic_env_cnt_steering_fail[0x1];
1958 	u8         vport_counter_local_loopback[0x1];
1959 	u8         q_counter_aggregation[0x1];
1960 	u8         q_counter_other_vport[0x1];
1961 	u8         log_max_xrcd[0x5];
1962 
1963 	u8         nic_receive_steering_discard[0x1];
1964 	u8         receive_discard_vport_down[0x1];
1965 	u8         transmit_discard_vport_down[0x1];
1966 	u8         eq_overrun_count[0x1];
1967 	u8         reserved_at_344[0x1];
1968 	u8         invalid_command_count[0x1];
1969 	u8         quota_exceeded_count[0x1];
1970 	u8         reserved_at_347[0x1];
1971 	u8         log_max_flow_counter_bulk[0x8];
1972 	u8         max_flow_counter_15_0[0x10];
1973 
1974 
1975 	u8         reserved_at_360[0x3];
1976 	u8         log_max_rq[0x5];
1977 	u8         ft_alias_sw_vhca_id[0x1];
1978 	u8         reserved_at_369[0x2];
1979 	u8         log_max_sq[0x5];
1980 	u8         reserved_at_370[0x3];
1981 	u8         log_max_tir[0x5];
1982 	u8         reserved_at_378[0x3];
1983 	u8         log_max_tis[0x5];
1984 
1985 	u8         basic_cyclic_rcv_wqe[0x1];
1986 	u8         reserved_at_381[0x2];
1987 	u8         log_max_rmp[0x5];
1988 	u8         reserved_at_388[0x3];
1989 	u8         log_max_rqt[0x5];
1990 	u8         reserved_at_390[0x3];
1991 	u8         log_max_rqt_size[0x5];
1992 	u8         tlp_device_emulation_manager[0x1];
1993 	u8	   vnic_env_cnt_bar_uar_access[0x1];
1994 	u8	   vnic_env_cnt_odp_page_fault[0x1];
1995 	u8         log_max_tis_per_sq[0x5];
1996 
1997 	u8         ext_stride_num_range[0x1];
1998 	u8         roce_rw_supported[0x1];
1999 	u8         log_max_current_uc_list_wr_supported[0x1];
2000 	u8         log_max_stride_sz_rq[0x5];
2001 	u8         reserved_at_3a8[0x3];
2002 	u8         log_min_stride_sz_rq[0x5];
2003 	u8         reserved_at_3b0[0x3];
2004 	u8         log_max_stride_sz_sq[0x5];
2005 	u8         reserved_at_3b8[0x3];
2006 	u8         log_min_stride_sz_sq[0x5];
2007 
2008 	u8         hairpin[0x1];
2009 	u8         reserved_at_3c1[0x2];
2010 	u8         log_max_hairpin_queues[0x5];
2011 	u8         reserved_at_3c8[0x3];
2012 	u8         log_max_hairpin_wq_data_sz[0x5];
2013 	u8         reserved_at_3d0[0x3];
2014 	u8         log_max_hairpin_num_packets[0x5];
2015 	u8         reserved_at_3d8[0x3];
2016 	u8         log_max_wq_sz[0x5];
2017 
2018 	u8         nic_vport_change_event[0x1];
2019 	u8         disable_local_lb_uc[0x1];
2020 	u8         disable_local_lb_mc[0x1];
2021 	u8         log_min_hairpin_wq_data_sz[0x5];
2022 	u8         reserved_at_3e8[0x1];
2023 	u8         silent_mode_set[0x1];
2024 	u8         vhca_state[0x1];
2025 	u8         log_max_vlan_list[0x5];
2026 	u8         reserved_at_3f0[0x3];
2027 	u8         log_max_current_mc_list[0x5];
2028 	u8         reserved_at_3f8[0x1];
2029 	u8         silent_mode_query[0x1];
2030 	u8         reserved_at_3fa[0x1];
2031 	u8         log_max_current_uc_list[0x5];
2032 
2033 	u8         general_obj_types[0x40];
2034 
2035 	u8         sq_ts_format[0x2];
2036 	u8         rq_ts_format[0x2];
2037 	u8         steering_format_version[0x4];
2038 	u8         create_qp_start_hint[0x18];
2039 
2040 	u8         reserved_at_460[0x1];
2041 	u8         ats[0x1];
2042 	u8         cross_vhca_rqt[0x1];
2043 	u8         log_max_uctx[0x5];
2044 	u8         reserved_at_468[0x1];
2045 	u8         crypto[0x1];
2046 	u8         ipsec_offload[0x1];
2047 	u8         log_max_umem[0x5];
2048 	u8         max_num_eqs[0x10];
2049 
2050 	u8         reserved_at_480[0x1];
2051 	u8         tls_tx[0x1];
2052 	u8         tls_rx[0x1];
2053 	u8         log_max_l2_table[0x5];
2054 	u8         reserved_at_488[0x8];
2055 	u8         log_uar_page_sz[0x10];
2056 
2057 	u8         reserved_at_4a0[0x20];
2058 	u8         device_frequency_mhz[0x20];
2059 	u8         device_frequency_khz[0x20];
2060 
2061 	u8         reserved_at_500[0x20];
2062 	u8	   num_of_uars_per_page[0x20];
2063 
2064 	u8         flex_parser_protocols[0x20];
2065 
2066 	u8         max_geneve_tlv_options[0x8];
2067 	u8         reserved_at_568[0x3];
2068 	u8         max_geneve_tlv_option_data_len[0x5];
2069 	u8         reserved_at_570[0x1];
2070 	u8         adv_rdma[0x1];
2071 	u8         reserved_at_572[0x7];
2072 	u8         adv_virtualization[0x1];
2073 	u8         reserved_at_57a[0x6];
2074 
2075 	u8	   reserved_at_580[0xb];
2076 	u8	   log_max_dci_stream_channels[0x5];
2077 	u8	   reserved_at_590[0x3];
2078 	u8	   log_max_dci_errored_streams[0x5];
2079 	u8	   reserved_at_598[0x8];
2080 
2081 	u8         reserved_at_5a0[0x10];
2082 	u8         enhanced_cqe_compression[0x1];
2083 	u8         reserved_at_5b1[0x1];
2084 	u8         crossing_vhca_mkey[0x1];
2085 	u8         log_max_dek[0x5];
2086 	u8         reserved_at_5b8[0x4];
2087 	u8         mini_cqe_resp_stride_index[0x1];
2088 	u8         cqe_128_always[0x1];
2089 	u8         cqe_compression_128[0x1];
2090 	u8         cqe_compression[0x1];
2091 
2092 	u8         cqe_compression_timeout[0x10];
2093 	u8         cqe_compression_max_num[0x10];
2094 
2095 	u8         reserved_at_5e0[0x8];
2096 	u8         flex_parser_id_gtpu_dw_0[0x4];
2097 	u8         reserved_at_5ec[0x4];
2098 	u8         tag_matching[0x1];
2099 	u8         rndv_offload_rc[0x1];
2100 	u8         rndv_offload_dc[0x1];
2101 	u8         log_tag_matching_list_sz[0x5];
2102 	u8         reserved_at_5f8[0x3];
2103 	u8         log_max_xrq[0x5];
2104 
2105 	u8	   affiliate_nic_vport_criteria[0x8];
2106 	u8	   native_port_num[0x8];
2107 	u8	   num_vhca_ports[0x8];
2108 	u8         flex_parser_id_gtpu_teid[0x4];
2109 	u8         reserved_at_61c[0x2];
2110 	u8	   sw_owner_id[0x1];
2111 	u8         reserved_at_61f[0x1];
2112 
2113 	u8         max_num_of_monitor_counters[0x10];
2114 	u8         num_ppcnt_monitor_counters[0x10];
2115 
2116 	u8         max_num_sf[0x10];
2117 	u8         num_q_monitor_counters[0x10];
2118 
2119 	u8         reserved_at_660[0x20];
2120 
2121 	u8         sf[0x1];
2122 	u8         sf_set_partition[0x1];
2123 	u8         reserved_at_682[0x1];
2124 	u8         log_max_sf[0x5];
2125 	u8         apu[0x1];
2126 	u8         reserved_at_689[0x4];
2127 	u8         migration[0x1];
2128 	u8         reserved_at_68e[0x2];
2129 	u8         log_min_sf_size[0x8];
2130 	u8         max_num_sf_partitions[0x8];
2131 
2132 	u8         uctx_cap[0x20];
2133 
2134 	u8         reserved_at_6c0[0x4];
2135 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2136 	u8         flex_parser_id_icmp_dw1[0x4];
2137 	u8         flex_parser_id_icmp_dw0[0x4];
2138 	u8         flex_parser_id_icmpv6_dw1[0x4];
2139 	u8         flex_parser_id_icmpv6_dw0[0x4];
2140 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2141 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2142 
2143 	u8         max_num_match_definer[0x10];
2144 	u8	   sf_base_id[0x10];
2145 
2146 	u8         flex_parser_id_gtpu_dw_2[0x4];
2147 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2148 	u8	   num_total_dynamic_vf_msix[0x18];
2149 	u8	   reserved_at_720[0x14];
2150 	u8	   dynamic_msix_table_size[0xc];
2151 	u8	   reserved_at_740[0xc];
2152 	u8	   min_dynamic_vf_msix_table_size[0x4];
2153 	u8	   reserved_at_750[0x2];
2154 	u8	   data_direct[0x1];
2155 	u8	   reserved_at_753[0x1];
2156 	u8	   max_dynamic_vf_msix_table_size[0xc];
2157 
2158 	u8         reserved_at_760[0x3];
2159 	u8         log_max_num_header_modify_argument[0x5];
2160 	u8         log_header_modify_argument_granularity_offset[0x4];
2161 	u8         log_header_modify_argument_granularity[0x4];
2162 	u8         reserved_at_770[0x3];
2163 	u8         log_header_modify_argument_max_alloc[0x5];
2164 	u8         reserved_at_778[0x8];
2165 
2166 	u8	   vhca_tunnel_commands[0x40];
2167 	u8         match_definer_format_supported[0x40];
2168 };
2169 
2170 enum {
2171 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2172 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2173 };
2174 
2175 enum {
2176 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2177 };
2178 
2179 struct mlx5_ifc_cmd_hca_cap_2_bits {
2180 	u8	   reserved_at_0[0x80];
2181 
2182 	u8         migratable[0x1];
2183 	u8         reserved_at_81[0x7];
2184 	u8         dp_ordering_force[0x1];
2185 	u8         reserved_at_89[0x9];
2186 	u8         query_vuid[0x1];
2187 	u8         reserved_at_93[0x5];
2188 	u8         umr_log_entity_size_5[0x1];
2189 	u8         reserved_at_99[0x7];
2190 
2191 	u8	   max_reformat_insert_size[0x8];
2192 	u8	   max_reformat_insert_offset[0x8];
2193 	u8	   max_reformat_remove_size[0x8];
2194 	u8	   max_reformat_remove_offset[0x8];
2195 
2196 	u8	   reserved_at_c0[0x8];
2197 	u8	   migration_multi_load[0x1];
2198 	u8	   migration_tracking_state[0x1];
2199 	u8	   multiplane_qp_ud[0x1];
2200 	u8	   reserved_at_cb[0x5];
2201 	u8	   migration_in_chunks[0x1];
2202 	u8	   reserved_at_d1[0x1];
2203 	u8	   sf_eq_usage[0x1];
2204 	u8	   reserved_at_d3[0x5];
2205 	u8	   multiplane[0x1];
2206 	u8	   migration_state[0x1];
2207 	u8	   reserved_at_da[0x6];
2208 
2209 	u8	   cross_vhca_object_to_object_supported[0x20];
2210 
2211 	u8	   allowed_object_for_other_vhca_access[0x40];
2212 
2213 	u8	   reserved_at_140[0x60];
2214 
2215 	u8	   flow_table_type_2_type[0x8];
2216 	u8	   reserved_at_1a8[0x2];
2217 	u8         format_select_dw_8_6_ext[0x1];
2218 	u8	   log_min_mkey_entity_size[0x5];
2219 	u8	   reserved_at_1b0[0x10];
2220 
2221 	u8	   general_obj_types_127_64[0x40];
2222 	u8	   reserved_at_200[0x20];
2223 
2224 	u8	   reserved_at_220[0x1];
2225 	u8	   sw_vhca_id_valid[0x1];
2226 	u8	   sw_vhca_id[0xe];
2227 	u8	   reserved_at_230[0x10];
2228 
2229 	u8	   reserved_at_240[0xb];
2230 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2231 	u8	   reserved_at_250[0x10];
2232 
2233 	u8	   reserved_at_260[0x20];
2234 
2235 	u8	   format_select_dw_gtpu_dw_0[0x8];
2236 	u8	   format_select_dw_gtpu_dw_1[0x8];
2237 	u8	   format_select_dw_gtpu_dw_2[0x8];
2238 	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2239 
2240 	u8	   generate_wqe_type[0x20];
2241 
2242 	u8	   reserved_at_2c0[0xc0];
2243 
2244 	u8	   reserved_at_380[0xb];
2245 	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2246 	u8	   ec_vf_vport_base[0x10];
2247 
2248 	u8	   reserved_at_3a0[0x2];
2249 	u8	   max_mkey_log_entity_size_fixed_buffer[0x6];
2250 	u8	   reserved_at_3a8[0x2];
2251 	u8	   max_mkey_log_entity_size_mtt[0x6];
2252 	u8	   max_rqt_vhca_id[0x10];
2253 
2254 	u8	   reserved_at_3c0[0x20];
2255 
2256 	u8	   reserved_at_3e0[0x10];
2257 	u8	   pcc_ifa2[0x1];
2258 	u8	   reserved_at_3f1[0xf];
2259 
2260 	u8	   reserved_at_400[0x1];
2261 	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2262 	u8	   reserved_at_402[0xe];
2263 	u8	   return_reg_id[0x10];
2264 
2265 	u8	   reserved_at_420[0x1c];
2266 	u8	   flow_table_hash_type[0x4];
2267 
2268 	u8	   reserved_at_440[0x8];
2269 	u8	   max_num_eqs_24b[0x18];
2270 
2271 	u8         reserved_at_460[0x144];
2272 	u8         load_balance_id[0x4];
2273 	u8         reserved_at_5a8[0x18];
2274 
2275 	u8         query_adjacent_functions_id[0x1];
2276 	u8         ingress_egress_esw_vport_connect[0x1];
2277 	u8         function_id_type_vhca_id[0x1];
2278 	u8         reserved_at_5c3[0x1];
2279 	u8         lag_per_mp_group[0x1];
2280 	u8         reserved_at_5c5[0xb];
2281 	u8         delegate_vhca_management_profiles[0x10];
2282 
2283 	u8         delegated_vhca_max[0x10];
2284 	u8         delegate_vhca_max[0x10];
2285 
2286 	u8         reserved_at_600[0x200];
2287 };
2288 
2289 enum mlx5_ifc_flow_destination_type {
2290 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2291 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2292 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2293 	MLX5_IFC_FLOW_DESTINATION_TYPE_VHCA_RX	    = 0x4,
2294 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2295 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2296 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2297 };
2298 
2299 enum mlx5_flow_table_miss_action {
2300 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2301 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2302 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2303 };
2304 
2305 struct mlx5_ifc_dest_format_struct_bits {
2306 	u8         destination_type[0x8];
2307 	u8         destination_id[0x18];
2308 
2309 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2310 	u8         packet_reformat[0x1];
2311 	u8         reserved_at_22[0x6];
2312 	u8         destination_table_type[0x8];
2313 	u8         destination_eswitch_owner_vhca_id[0x10];
2314 };
2315 
2316 struct mlx5_ifc_flow_counter_list_bits {
2317 	u8         flow_counter_id[0x20];
2318 
2319 	u8         reserved_at_20[0x20];
2320 };
2321 
2322 struct mlx5_ifc_extended_dest_format_bits {
2323 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2324 
2325 	u8         packet_reformat_id[0x20];
2326 
2327 	u8         reserved_at_60[0x20];
2328 };
2329 
2330 union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2331 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2332 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2333 };
2334 
2335 struct mlx5_ifc_fte_match_param_bits {
2336 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2337 
2338 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2339 
2340 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2341 
2342 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2343 
2344 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2345 
2346 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2347 
2348 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2349 
2350 	u8         reserved_at_e00[0x200];
2351 };
2352 
2353 enum {
2354 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2355 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2356 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2357 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2358 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2359 };
2360 
2361 struct mlx5_ifc_rx_hash_field_select_bits {
2362 	u8         l3_prot_type[0x1];
2363 	u8         l4_prot_type[0x1];
2364 	u8         selected_fields[0x1e];
2365 };
2366 
2367 enum {
2368 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2369 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2370 };
2371 
2372 enum {
2373 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2374 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2375 };
2376 
2377 struct mlx5_ifc_wq_bits {
2378 	u8         wq_type[0x4];
2379 	u8         wq_signature[0x1];
2380 	u8         end_padding_mode[0x2];
2381 	u8         cd_slave[0x1];
2382 	u8         reserved_at_8[0x18];
2383 
2384 	u8         hds_skip_first_sge[0x1];
2385 	u8         log2_hds_buf_size[0x3];
2386 	u8         reserved_at_24[0x7];
2387 	u8         page_offset[0x5];
2388 	u8         lwm[0x10];
2389 
2390 	u8         reserved_at_40[0x8];
2391 	u8         pd[0x18];
2392 
2393 	u8         reserved_at_60[0x8];
2394 	u8         uar_page[0x18];
2395 
2396 	u8         dbr_addr[0x40];
2397 
2398 	u8         hw_counter[0x20];
2399 
2400 	u8         sw_counter[0x20];
2401 
2402 	u8         reserved_at_100[0xc];
2403 	u8         log_wq_stride[0x4];
2404 	u8         reserved_at_110[0x3];
2405 	u8         log_wq_pg_sz[0x5];
2406 	u8         reserved_at_118[0x3];
2407 	u8         log_wq_sz[0x5];
2408 
2409 	u8         dbr_umem_valid[0x1];
2410 	u8         wq_umem_valid[0x1];
2411 	u8         reserved_at_122[0x1];
2412 	u8         log_hairpin_num_packets[0x5];
2413 	u8         reserved_at_128[0x3];
2414 	u8         log_hairpin_data_sz[0x5];
2415 
2416 	u8         reserved_at_130[0x4];
2417 	u8         log_wqe_num_of_strides[0x4];
2418 	u8         two_byte_shift_en[0x1];
2419 	u8         reserved_at_139[0x4];
2420 	u8         log_wqe_stride_size[0x3];
2421 
2422 	u8         dbr_umem_id[0x20];
2423 	u8         wq_umem_id[0x20];
2424 
2425 	u8         wq_umem_offset[0x40];
2426 
2427 	u8         headers_mkey[0x20];
2428 
2429 	u8         shampo_enable[0x1];
2430 	u8         reserved_at_1e1[0x1];
2431 	u8         shampo_mode[0x2];
2432 	u8         reserved_at_1e4[0x1];
2433 	u8         log_reservation_size[0x3];
2434 	u8         reserved_at_1e8[0x5];
2435 	u8         log_max_num_of_packets_per_reservation[0x3];
2436 	u8         reserved_at_1f0[0x6];
2437 	u8         log_headers_entry_size[0x2];
2438 	u8         reserved_at_1f8[0x4];
2439 	u8         log_headers_buffer_entry_num[0x4];
2440 
2441 	u8         reserved_at_200[0x400];
2442 
2443 	struct mlx5_ifc_cmd_pas_bits pas[];
2444 };
2445 
2446 struct mlx5_ifc_rq_num_bits {
2447 	u8         reserved_at_0[0x8];
2448 	u8         rq_num[0x18];
2449 };
2450 
2451 struct mlx5_ifc_rq_vhca_bits {
2452 	u8         reserved_at_0[0x8];
2453 	u8         rq_num[0x18];
2454 	u8         reserved_at_20[0x10];
2455 	u8         rq_vhca_id[0x10];
2456 };
2457 
2458 struct mlx5_ifc_mac_address_layout_bits {
2459 	u8         reserved_at_0[0x10];
2460 	u8         mac_addr_47_32[0x10];
2461 
2462 	u8         mac_addr_31_0[0x20];
2463 };
2464 
2465 struct mlx5_ifc_vlan_layout_bits {
2466 	u8         reserved_at_0[0x14];
2467 	u8         vlan[0x0c];
2468 
2469 	u8         reserved_at_20[0x20];
2470 };
2471 
2472 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2473 	u8         reserved_at_0[0xa0];
2474 
2475 	u8         min_time_between_cnps[0x20];
2476 
2477 	u8         reserved_at_c0[0x12];
2478 	u8         cnp_dscp[0x6];
2479 	u8         reserved_at_d8[0x4];
2480 	u8         cnp_prio_mode[0x1];
2481 	u8         cnp_802p_prio[0x3];
2482 
2483 	u8         reserved_at_e0[0x720];
2484 };
2485 
2486 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2487 	u8         reserved_at_0[0x60];
2488 
2489 	u8         reserved_at_60[0x4];
2490 	u8         clamp_tgt_rate[0x1];
2491 	u8         reserved_at_65[0x3];
2492 	u8         clamp_tgt_rate_after_time_inc[0x1];
2493 	u8         reserved_at_69[0x17];
2494 
2495 	u8         reserved_at_80[0x20];
2496 
2497 	u8         rpg_time_reset[0x20];
2498 
2499 	u8         rpg_byte_reset[0x20];
2500 
2501 	u8         rpg_threshold[0x20];
2502 
2503 	u8         rpg_max_rate[0x20];
2504 
2505 	u8         rpg_ai_rate[0x20];
2506 
2507 	u8         rpg_hai_rate[0x20];
2508 
2509 	u8         rpg_gd[0x20];
2510 
2511 	u8         rpg_min_dec_fac[0x20];
2512 
2513 	u8         rpg_min_rate[0x20];
2514 
2515 	u8         reserved_at_1c0[0xe0];
2516 
2517 	u8         rate_to_set_on_first_cnp[0x20];
2518 
2519 	u8         dce_tcp_g[0x20];
2520 
2521 	u8         dce_tcp_rtt[0x20];
2522 
2523 	u8         rate_reduce_monitor_period[0x20];
2524 
2525 	u8         reserved_at_320[0x20];
2526 
2527 	u8         initial_alpha_value[0x20];
2528 
2529 	u8         reserved_at_360[0x4a0];
2530 };
2531 
2532 struct mlx5_ifc_cong_control_r_roce_general_bits {
2533 	u8         reserved_at_0[0x80];
2534 
2535 	u8         reserved_at_80[0x10];
2536 	u8         rtt_resp_dscp_valid[0x1];
2537 	u8         reserved_at_91[0x9];
2538 	u8         rtt_resp_dscp[0x6];
2539 
2540 	u8         reserved_at_a0[0x760];
2541 };
2542 
2543 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2544 	u8         reserved_at_0[0x80];
2545 
2546 	u8         rppp_max_rps[0x20];
2547 
2548 	u8         rpg_time_reset[0x20];
2549 
2550 	u8         rpg_byte_reset[0x20];
2551 
2552 	u8         rpg_threshold[0x20];
2553 
2554 	u8         rpg_max_rate[0x20];
2555 
2556 	u8         rpg_ai_rate[0x20];
2557 
2558 	u8         rpg_hai_rate[0x20];
2559 
2560 	u8         rpg_gd[0x20];
2561 
2562 	u8         rpg_min_dec_fac[0x20];
2563 
2564 	u8         rpg_min_rate[0x20];
2565 
2566 	u8         reserved_at_1c0[0x640];
2567 };
2568 
2569 enum {
2570 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2571 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2572 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2573 };
2574 
2575 struct mlx5_ifc_resize_field_select_bits {
2576 	u8         resize_field_select[0x20];
2577 };
2578 
2579 struct mlx5_ifc_resource_dump_bits {
2580 	u8         more_dump[0x1];
2581 	u8         inline_dump[0x1];
2582 	u8         reserved_at_2[0xa];
2583 	u8         seq_num[0x4];
2584 	u8         segment_type[0x10];
2585 
2586 	u8         reserved_at_20[0x10];
2587 	u8         vhca_id[0x10];
2588 
2589 	u8         index1[0x20];
2590 
2591 	u8         index2[0x20];
2592 
2593 	u8         num_of_obj1[0x10];
2594 	u8         num_of_obj2[0x10];
2595 
2596 	u8         reserved_at_a0[0x20];
2597 
2598 	u8         device_opaque[0x40];
2599 
2600 	u8         mkey[0x20];
2601 
2602 	u8         size[0x20];
2603 
2604 	u8         address[0x40];
2605 
2606 	u8         inline_data[52][0x20];
2607 };
2608 
2609 struct mlx5_ifc_resource_dump_menu_record_bits {
2610 	u8         reserved_at_0[0x4];
2611 	u8         num_of_obj2_supports_active[0x1];
2612 	u8         num_of_obj2_supports_all[0x1];
2613 	u8         must_have_num_of_obj2[0x1];
2614 	u8         support_num_of_obj2[0x1];
2615 	u8         num_of_obj1_supports_active[0x1];
2616 	u8         num_of_obj1_supports_all[0x1];
2617 	u8         must_have_num_of_obj1[0x1];
2618 	u8         support_num_of_obj1[0x1];
2619 	u8         must_have_index2[0x1];
2620 	u8         support_index2[0x1];
2621 	u8         must_have_index1[0x1];
2622 	u8         support_index1[0x1];
2623 	u8         segment_type[0x10];
2624 
2625 	u8         segment_name[4][0x20];
2626 
2627 	u8         index1_name[4][0x20];
2628 
2629 	u8         index2_name[4][0x20];
2630 };
2631 
2632 struct mlx5_ifc_resource_dump_segment_header_bits {
2633 	u8         length_dw[0x10];
2634 	u8         segment_type[0x10];
2635 };
2636 
2637 struct mlx5_ifc_resource_dump_command_segment_bits {
2638 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2639 
2640 	u8         segment_called[0x10];
2641 	u8         vhca_id[0x10];
2642 
2643 	u8         index1[0x20];
2644 
2645 	u8         index2[0x20];
2646 
2647 	u8         num_of_obj1[0x10];
2648 	u8         num_of_obj2[0x10];
2649 };
2650 
2651 struct mlx5_ifc_resource_dump_error_segment_bits {
2652 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2653 
2654 	u8         reserved_at_20[0x10];
2655 	u8         syndrome_id[0x10];
2656 
2657 	u8         reserved_at_40[0x40];
2658 
2659 	u8         error[8][0x20];
2660 };
2661 
2662 struct mlx5_ifc_resource_dump_info_segment_bits {
2663 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2664 
2665 	u8         reserved_at_20[0x18];
2666 	u8         dump_version[0x8];
2667 
2668 	u8         hw_version[0x20];
2669 
2670 	u8         fw_version[0x20];
2671 };
2672 
2673 struct mlx5_ifc_resource_dump_menu_segment_bits {
2674 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2675 
2676 	u8         reserved_at_20[0x10];
2677 	u8         num_of_records[0x10];
2678 
2679 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2680 };
2681 
2682 struct mlx5_ifc_resource_dump_resource_segment_bits {
2683 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2684 
2685 	u8         reserved_at_20[0x20];
2686 
2687 	u8         index1[0x20];
2688 
2689 	u8         index2[0x20];
2690 
2691 	u8         payload[][0x20];
2692 };
2693 
2694 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2695 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2696 };
2697 
2698 struct mlx5_ifc_menu_resource_dump_response_bits {
2699 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2700 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2701 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2702 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2703 };
2704 
2705 enum {
2706 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2707 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2708 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2709 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2710 };
2711 
2712 struct mlx5_ifc_modify_field_select_bits {
2713 	u8         modify_field_select[0x20];
2714 };
2715 
2716 struct mlx5_ifc_field_select_r_roce_np_bits {
2717 	u8         field_select_r_roce_np[0x20];
2718 };
2719 
2720 struct mlx5_ifc_field_select_r_roce_rp_bits {
2721 	u8         field_select_r_roce_rp[0x20];
2722 };
2723 
2724 enum {
2725 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2726 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2727 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2728 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2729 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2730 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2731 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2732 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2733 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2734 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2735 };
2736 
2737 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2738 	u8         field_select_8021qaurp[0x20];
2739 };
2740 
2741 struct mlx5_ifc_phys_layer_recovery_cntrs_bits {
2742 	u8         total_successful_recovery_events[0x20];
2743 
2744 	u8         reserved_at_20[0x7a0];
2745 };
2746 
2747 struct mlx5_ifc_phys_layer_cntrs_bits {
2748 	u8         time_since_last_clear_high[0x20];
2749 
2750 	u8         time_since_last_clear_low[0x20];
2751 
2752 	u8         symbol_errors_high[0x20];
2753 
2754 	u8         symbol_errors_low[0x20];
2755 
2756 	u8         sync_headers_errors_high[0x20];
2757 
2758 	u8         sync_headers_errors_low[0x20];
2759 
2760 	u8         edpl_bip_errors_lane0_high[0x20];
2761 
2762 	u8         edpl_bip_errors_lane0_low[0x20];
2763 
2764 	u8         edpl_bip_errors_lane1_high[0x20];
2765 
2766 	u8         edpl_bip_errors_lane1_low[0x20];
2767 
2768 	u8         edpl_bip_errors_lane2_high[0x20];
2769 
2770 	u8         edpl_bip_errors_lane2_low[0x20];
2771 
2772 	u8         edpl_bip_errors_lane3_high[0x20];
2773 
2774 	u8         edpl_bip_errors_lane3_low[0x20];
2775 
2776 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2777 
2778 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2779 
2780 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2781 
2782 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2783 
2784 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2785 
2786 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2787 
2788 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2789 
2790 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2791 
2792 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2793 
2794 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2795 
2796 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2797 
2798 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2799 
2800 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2801 
2802 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2803 
2804 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2805 
2806 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2807 
2808 	u8         rs_fec_corrected_blocks_high[0x20];
2809 
2810 	u8         rs_fec_corrected_blocks_low[0x20];
2811 
2812 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2813 
2814 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2815 
2816 	u8         rs_fec_no_errors_blocks_high[0x20];
2817 
2818 	u8         rs_fec_no_errors_blocks_low[0x20];
2819 
2820 	u8         rs_fec_single_error_blocks_high[0x20];
2821 
2822 	u8         rs_fec_single_error_blocks_low[0x20];
2823 
2824 	u8         rs_fec_corrected_symbols_total_high[0x20];
2825 
2826 	u8         rs_fec_corrected_symbols_total_low[0x20];
2827 
2828 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2829 
2830 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2831 
2832 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2833 
2834 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2835 
2836 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2837 
2838 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2839 
2840 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2841 
2842 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2843 
2844 	u8         link_down_events[0x20];
2845 
2846 	u8         successful_recovery_events[0x20];
2847 
2848 	u8         reserved_at_640[0x180];
2849 };
2850 
2851 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2852 	u8         time_since_last_clear_high[0x20];
2853 
2854 	u8         time_since_last_clear_low[0x20];
2855 
2856 	u8         phy_received_bits_high[0x20];
2857 
2858 	u8         phy_received_bits_low[0x20];
2859 
2860 	u8         phy_symbol_errors_high[0x20];
2861 
2862 	u8         phy_symbol_errors_low[0x20];
2863 
2864 	u8         phy_corrected_bits_high[0x20];
2865 
2866 	u8         phy_corrected_bits_low[0x20];
2867 
2868 	u8         phy_corrected_bits_lane0_high[0x20];
2869 
2870 	u8         phy_corrected_bits_lane0_low[0x20];
2871 
2872 	u8         phy_corrected_bits_lane1_high[0x20];
2873 
2874 	u8         phy_corrected_bits_lane1_low[0x20];
2875 
2876 	u8         phy_corrected_bits_lane2_high[0x20];
2877 
2878 	u8         phy_corrected_bits_lane2_low[0x20];
2879 
2880 	u8         phy_corrected_bits_lane3_high[0x20];
2881 
2882 	u8         phy_corrected_bits_lane3_low[0x20];
2883 
2884 	u8         reserved_at_200[0x5c0];
2885 };
2886 
2887 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2888 	u8	   symbol_error_counter[0x10];
2889 
2890 	u8         link_error_recovery_counter[0x8];
2891 
2892 	u8         link_downed_counter[0x8];
2893 
2894 	u8         port_rcv_errors[0x10];
2895 
2896 	u8         port_rcv_remote_physical_errors[0x10];
2897 
2898 	u8         port_rcv_switch_relay_errors[0x10];
2899 
2900 	u8         port_xmit_discards[0x10];
2901 
2902 	u8         port_xmit_constraint_errors[0x8];
2903 
2904 	u8         port_rcv_constraint_errors[0x8];
2905 
2906 	u8         reserved_at_70[0x8];
2907 
2908 	u8         link_overrun_errors[0x8];
2909 
2910 	u8	   reserved_at_80[0x10];
2911 
2912 	u8         vl_15_dropped[0x10];
2913 
2914 	u8	   reserved_at_a0[0x80];
2915 
2916 	u8         port_xmit_wait[0x20];
2917 };
2918 
2919 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2920 	u8         reserved_at_0[0x300];
2921 
2922 	u8         port_xmit_data_high[0x20];
2923 
2924 	u8         port_xmit_data_low[0x20];
2925 
2926 	u8         port_rcv_data_high[0x20];
2927 
2928 	u8         port_rcv_data_low[0x20];
2929 
2930 	u8         port_xmit_pkts_high[0x20];
2931 
2932 	u8         port_xmit_pkts_low[0x20];
2933 
2934 	u8         port_rcv_pkts_high[0x20];
2935 
2936 	u8         port_rcv_pkts_low[0x20];
2937 
2938 	u8         reserved_at_400[0x80];
2939 
2940 	u8         port_unicast_xmit_pkts_high[0x20];
2941 
2942 	u8         port_unicast_xmit_pkts_low[0x20];
2943 
2944 	u8         port_multicast_xmit_pkts_high[0x20];
2945 
2946 	u8         port_multicast_xmit_pkts_low[0x20];
2947 
2948 	u8         port_unicast_rcv_pkts_high[0x20];
2949 
2950 	u8         port_unicast_rcv_pkts_low[0x20];
2951 
2952 	u8         port_multicast_rcv_pkts_high[0x20];
2953 
2954 	u8         port_multicast_rcv_pkts_low[0x20];
2955 
2956 	u8         reserved_at_580[0x240];
2957 };
2958 
2959 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2960 	u8         transmit_queue_high[0x20];
2961 
2962 	u8         transmit_queue_low[0x20];
2963 
2964 	u8         no_buffer_discard_uc_high[0x20];
2965 
2966 	u8         no_buffer_discard_uc_low[0x20];
2967 
2968 	u8         reserved_at_80[0x740];
2969 };
2970 
2971 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2972 	u8         wred_discard_high[0x20];
2973 
2974 	u8         wred_discard_low[0x20];
2975 
2976 	u8         ecn_marked_tc_high[0x20];
2977 
2978 	u8         ecn_marked_tc_low[0x20];
2979 
2980 	u8         reserved_at_80[0x740];
2981 };
2982 
2983 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2984 	u8         rx_octets_high[0x20];
2985 
2986 	u8         rx_octets_low[0x20];
2987 
2988 	u8         reserved_at_40[0xc0];
2989 
2990 	u8         rx_frames_high[0x20];
2991 
2992 	u8         rx_frames_low[0x20];
2993 
2994 	u8         tx_octets_high[0x20];
2995 
2996 	u8         tx_octets_low[0x20];
2997 
2998 	u8         reserved_at_180[0xc0];
2999 
3000 	u8         tx_frames_high[0x20];
3001 
3002 	u8         tx_frames_low[0x20];
3003 
3004 	u8         rx_pause_high[0x20];
3005 
3006 	u8         rx_pause_low[0x20];
3007 
3008 	u8         rx_pause_duration_high[0x20];
3009 
3010 	u8         rx_pause_duration_low[0x20];
3011 
3012 	u8         tx_pause_high[0x20];
3013 
3014 	u8         tx_pause_low[0x20];
3015 
3016 	u8         tx_pause_duration_high[0x20];
3017 
3018 	u8         tx_pause_duration_low[0x20];
3019 
3020 	u8         rx_pause_transition_high[0x20];
3021 
3022 	u8         rx_pause_transition_low[0x20];
3023 
3024 	u8         rx_discards_high[0x20];
3025 
3026 	u8         rx_discards_low[0x20];
3027 
3028 	u8         device_stall_minor_watermark_cnt_high[0x20];
3029 
3030 	u8         device_stall_minor_watermark_cnt_low[0x20];
3031 
3032 	u8         device_stall_critical_watermark_cnt_high[0x20];
3033 
3034 	u8         device_stall_critical_watermark_cnt_low[0x20];
3035 
3036 	u8         reserved_at_480[0x340];
3037 };
3038 
3039 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
3040 	u8         port_transmit_wait_high[0x20];
3041 
3042 	u8         port_transmit_wait_low[0x20];
3043 
3044 	u8         reserved_at_40[0x100];
3045 
3046 	u8         rx_buffer_almost_full_high[0x20];
3047 
3048 	u8         rx_buffer_almost_full_low[0x20];
3049 
3050 	u8         rx_buffer_full_high[0x20];
3051 
3052 	u8         rx_buffer_full_low[0x20];
3053 
3054 	u8         rx_icrc_encapsulated_high[0x20];
3055 
3056 	u8         rx_icrc_encapsulated_low[0x20];
3057 
3058 	u8         reserved_at_200[0x5c0];
3059 };
3060 
3061 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
3062 	u8         dot3stats_alignment_errors_high[0x20];
3063 
3064 	u8         dot3stats_alignment_errors_low[0x20];
3065 
3066 	u8         dot3stats_fcs_errors_high[0x20];
3067 
3068 	u8         dot3stats_fcs_errors_low[0x20];
3069 
3070 	u8         dot3stats_single_collision_frames_high[0x20];
3071 
3072 	u8         dot3stats_single_collision_frames_low[0x20];
3073 
3074 	u8         dot3stats_multiple_collision_frames_high[0x20];
3075 
3076 	u8         dot3stats_multiple_collision_frames_low[0x20];
3077 
3078 	u8         dot3stats_sqe_test_errors_high[0x20];
3079 
3080 	u8         dot3stats_sqe_test_errors_low[0x20];
3081 
3082 	u8         dot3stats_deferred_transmissions_high[0x20];
3083 
3084 	u8         dot3stats_deferred_transmissions_low[0x20];
3085 
3086 	u8         dot3stats_late_collisions_high[0x20];
3087 
3088 	u8         dot3stats_late_collisions_low[0x20];
3089 
3090 	u8         dot3stats_excessive_collisions_high[0x20];
3091 
3092 	u8         dot3stats_excessive_collisions_low[0x20];
3093 
3094 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
3095 
3096 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
3097 
3098 	u8         dot3stats_carrier_sense_errors_high[0x20];
3099 
3100 	u8         dot3stats_carrier_sense_errors_low[0x20];
3101 
3102 	u8         dot3stats_frame_too_longs_high[0x20];
3103 
3104 	u8         dot3stats_frame_too_longs_low[0x20];
3105 
3106 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
3107 
3108 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
3109 
3110 	u8         dot3stats_symbol_errors_high[0x20];
3111 
3112 	u8         dot3stats_symbol_errors_low[0x20];
3113 
3114 	u8         dot3control_in_unknown_opcodes_high[0x20];
3115 
3116 	u8         dot3control_in_unknown_opcodes_low[0x20];
3117 
3118 	u8         dot3in_pause_frames_high[0x20];
3119 
3120 	u8         dot3in_pause_frames_low[0x20];
3121 
3122 	u8         dot3out_pause_frames_high[0x20];
3123 
3124 	u8         dot3out_pause_frames_low[0x20];
3125 
3126 	u8         reserved_at_400[0x3c0];
3127 };
3128 
3129 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3130 	u8         ether_stats_drop_events_high[0x20];
3131 
3132 	u8         ether_stats_drop_events_low[0x20];
3133 
3134 	u8         ether_stats_octets_high[0x20];
3135 
3136 	u8         ether_stats_octets_low[0x20];
3137 
3138 	u8         ether_stats_pkts_high[0x20];
3139 
3140 	u8         ether_stats_pkts_low[0x20];
3141 
3142 	u8         ether_stats_broadcast_pkts_high[0x20];
3143 
3144 	u8         ether_stats_broadcast_pkts_low[0x20];
3145 
3146 	u8         ether_stats_multicast_pkts_high[0x20];
3147 
3148 	u8         ether_stats_multicast_pkts_low[0x20];
3149 
3150 	u8         ether_stats_crc_align_errors_high[0x20];
3151 
3152 	u8         ether_stats_crc_align_errors_low[0x20];
3153 
3154 	u8         ether_stats_undersize_pkts_high[0x20];
3155 
3156 	u8         ether_stats_undersize_pkts_low[0x20];
3157 
3158 	u8         ether_stats_oversize_pkts_high[0x20];
3159 
3160 	u8         ether_stats_oversize_pkts_low[0x20];
3161 
3162 	u8         ether_stats_fragments_high[0x20];
3163 
3164 	u8         ether_stats_fragments_low[0x20];
3165 
3166 	u8         ether_stats_jabbers_high[0x20];
3167 
3168 	u8         ether_stats_jabbers_low[0x20];
3169 
3170 	u8         ether_stats_collisions_high[0x20];
3171 
3172 	u8         ether_stats_collisions_low[0x20];
3173 
3174 	u8         ether_stats_pkts64octets_high[0x20];
3175 
3176 	u8         ether_stats_pkts64octets_low[0x20];
3177 
3178 	u8         ether_stats_pkts65to127octets_high[0x20];
3179 
3180 	u8         ether_stats_pkts65to127octets_low[0x20];
3181 
3182 	u8         ether_stats_pkts128to255octets_high[0x20];
3183 
3184 	u8         ether_stats_pkts128to255octets_low[0x20];
3185 
3186 	u8         ether_stats_pkts256to511octets_high[0x20];
3187 
3188 	u8         ether_stats_pkts256to511octets_low[0x20];
3189 
3190 	u8         ether_stats_pkts512to1023octets_high[0x20];
3191 
3192 	u8         ether_stats_pkts512to1023octets_low[0x20];
3193 
3194 	u8         ether_stats_pkts1024to1518octets_high[0x20];
3195 
3196 	u8         ether_stats_pkts1024to1518octets_low[0x20];
3197 
3198 	u8         ether_stats_pkts1519to2047octets_high[0x20];
3199 
3200 	u8         ether_stats_pkts1519to2047octets_low[0x20];
3201 
3202 	u8         ether_stats_pkts2048to4095octets_high[0x20];
3203 
3204 	u8         ether_stats_pkts2048to4095octets_low[0x20];
3205 
3206 	u8         ether_stats_pkts4096to8191octets_high[0x20];
3207 
3208 	u8         ether_stats_pkts4096to8191octets_low[0x20];
3209 
3210 	u8         ether_stats_pkts8192to10239octets_high[0x20];
3211 
3212 	u8         ether_stats_pkts8192to10239octets_low[0x20];
3213 
3214 	u8         reserved_at_540[0x280];
3215 };
3216 
3217 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3218 	u8         if_in_octets_high[0x20];
3219 
3220 	u8         if_in_octets_low[0x20];
3221 
3222 	u8         if_in_ucast_pkts_high[0x20];
3223 
3224 	u8         if_in_ucast_pkts_low[0x20];
3225 
3226 	u8         if_in_discards_high[0x20];
3227 
3228 	u8         if_in_discards_low[0x20];
3229 
3230 	u8         if_in_errors_high[0x20];
3231 
3232 	u8         if_in_errors_low[0x20];
3233 
3234 	u8         if_in_unknown_protos_high[0x20];
3235 
3236 	u8         if_in_unknown_protos_low[0x20];
3237 
3238 	u8         if_out_octets_high[0x20];
3239 
3240 	u8         if_out_octets_low[0x20];
3241 
3242 	u8         if_out_ucast_pkts_high[0x20];
3243 
3244 	u8         if_out_ucast_pkts_low[0x20];
3245 
3246 	u8         if_out_discards_high[0x20];
3247 
3248 	u8         if_out_discards_low[0x20];
3249 
3250 	u8         if_out_errors_high[0x20];
3251 
3252 	u8         if_out_errors_low[0x20];
3253 
3254 	u8         if_in_multicast_pkts_high[0x20];
3255 
3256 	u8         if_in_multicast_pkts_low[0x20];
3257 
3258 	u8         if_in_broadcast_pkts_high[0x20];
3259 
3260 	u8         if_in_broadcast_pkts_low[0x20];
3261 
3262 	u8         if_out_multicast_pkts_high[0x20];
3263 
3264 	u8         if_out_multicast_pkts_low[0x20];
3265 
3266 	u8         if_out_broadcast_pkts_high[0x20];
3267 
3268 	u8         if_out_broadcast_pkts_low[0x20];
3269 
3270 	u8         reserved_at_340[0x480];
3271 };
3272 
3273 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3274 	u8         a_frames_transmitted_ok_high[0x20];
3275 
3276 	u8         a_frames_transmitted_ok_low[0x20];
3277 
3278 	u8         a_frames_received_ok_high[0x20];
3279 
3280 	u8         a_frames_received_ok_low[0x20];
3281 
3282 	u8         a_frame_check_sequence_errors_high[0x20];
3283 
3284 	u8         a_frame_check_sequence_errors_low[0x20];
3285 
3286 	u8         a_alignment_errors_high[0x20];
3287 
3288 	u8         a_alignment_errors_low[0x20];
3289 
3290 	u8         a_octets_transmitted_ok_high[0x20];
3291 
3292 	u8         a_octets_transmitted_ok_low[0x20];
3293 
3294 	u8         a_octets_received_ok_high[0x20];
3295 
3296 	u8         a_octets_received_ok_low[0x20];
3297 
3298 	u8         a_multicast_frames_xmitted_ok_high[0x20];
3299 
3300 	u8         a_multicast_frames_xmitted_ok_low[0x20];
3301 
3302 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3303 
3304 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3305 
3306 	u8         a_multicast_frames_received_ok_high[0x20];
3307 
3308 	u8         a_multicast_frames_received_ok_low[0x20];
3309 
3310 	u8         a_broadcast_frames_received_ok_high[0x20];
3311 
3312 	u8         a_broadcast_frames_received_ok_low[0x20];
3313 
3314 	u8         a_in_range_length_errors_high[0x20];
3315 
3316 	u8         a_in_range_length_errors_low[0x20];
3317 
3318 	u8         a_out_of_range_length_field_high[0x20];
3319 
3320 	u8         a_out_of_range_length_field_low[0x20];
3321 
3322 	u8         a_frame_too_long_errors_high[0x20];
3323 
3324 	u8         a_frame_too_long_errors_low[0x20];
3325 
3326 	u8         a_symbol_error_during_carrier_high[0x20];
3327 
3328 	u8         a_symbol_error_during_carrier_low[0x20];
3329 
3330 	u8         a_mac_control_frames_transmitted_high[0x20];
3331 
3332 	u8         a_mac_control_frames_transmitted_low[0x20];
3333 
3334 	u8         a_mac_control_frames_received_high[0x20];
3335 
3336 	u8         a_mac_control_frames_received_low[0x20];
3337 
3338 	u8         a_unsupported_opcodes_received_high[0x20];
3339 
3340 	u8         a_unsupported_opcodes_received_low[0x20];
3341 
3342 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3343 
3344 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3345 
3346 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3347 
3348 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3349 
3350 	u8         reserved_at_4c0[0x300];
3351 };
3352 
3353 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3354 	u8         life_time_counter_high[0x20];
3355 
3356 	u8         life_time_counter_low[0x20];
3357 
3358 	u8         rx_errors[0x20];
3359 
3360 	u8         tx_errors[0x20];
3361 
3362 	u8         l0_to_recovery_eieos[0x20];
3363 
3364 	u8         l0_to_recovery_ts[0x20];
3365 
3366 	u8         l0_to_recovery_framing[0x20];
3367 
3368 	u8         l0_to_recovery_retrain[0x20];
3369 
3370 	u8         crc_error_dllp[0x20];
3371 
3372 	u8         crc_error_tlp[0x20];
3373 
3374 	u8         tx_overflow_buffer_pkt_high[0x20];
3375 
3376 	u8         tx_overflow_buffer_pkt_low[0x20];
3377 
3378 	u8         outbound_stalled_reads[0x20];
3379 
3380 	u8         outbound_stalled_writes[0x20];
3381 
3382 	u8         outbound_stalled_reads_events[0x20];
3383 
3384 	u8         outbound_stalled_writes_events[0x20];
3385 
3386 	u8         reserved_at_200[0x5c0];
3387 };
3388 
3389 struct mlx5_ifc_cmd_inter_comp_event_bits {
3390 	u8         command_completion_vector[0x20];
3391 
3392 	u8         reserved_at_20[0xc0];
3393 };
3394 
3395 struct mlx5_ifc_stall_vl_event_bits {
3396 	u8         reserved_at_0[0x18];
3397 	u8         port_num[0x1];
3398 	u8         reserved_at_19[0x3];
3399 	u8         vl[0x4];
3400 
3401 	u8         reserved_at_20[0xa0];
3402 };
3403 
3404 struct mlx5_ifc_db_bf_congestion_event_bits {
3405 	u8         event_subtype[0x8];
3406 	u8         reserved_at_8[0x8];
3407 	u8         congestion_level[0x8];
3408 	u8         reserved_at_18[0x8];
3409 
3410 	u8         reserved_at_20[0xa0];
3411 };
3412 
3413 struct mlx5_ifc_gpio_event_bits {
3414 	u8         reserved_at_0[0x60];
3415 
3416 	u8         gpio_event_hi[0x20];
3417 
3418 	u8         gpio_event_lo[0x20];
3419 
3420 	u8         reserved_at_a0[0x40];
3421 };
3422 
3423 struct mlx5_ifc_port_state_change_event_bits {
3424 	u8         reserved_at_0[0x40];
3425 
3426 	u8         port_num[0x4];
3427 	u8         reserved_at_44[0x1c];
3428 
3429 	u8         reserved_at_60[0x80];
3430 };
3431 
3432 struct mlx5_ifc_dropped_packet_logged_bits {
3433 	u8         reserved_at_0[0xe0];
3434 };
3435 
3436 struct mlx5_ifc_nic_cap_reg_bits {
3437 	u8	   reserved_at_0[0x1a];
3438 	u8	   vhca_icm_ctrl[0x1];
3439 	u8	   reserved_at_1b[0x5];
3440 
3441 	u8	   reserved_at_20[0x60];
3442 };
3443 
3444 struct mlx5_ifc_default_timeout_bits {
3445 	u8         to_multiplier[0x3];
3446 	u8         reserved_at_3[0x9];
3447 	u8         to_value[0x14];
3448 };
3449 
3450 struct mlx5_ifc_dtor_reg_bits {
3451 	u8         reserved_at_0[0x20];
3452 
3453 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3454 
3455 	u8         reserved_at_40[0x60];
3456 
3457 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3458 
3459 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3460 
3461 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3462 
3463 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3464 
3465 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3466 
3467 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3468 
3469 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3470 
3471 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3472 
3473 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3474 
3475 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3476 
3477 	u8         reserved_at_1c0[0x20];
3478 };
3479 
3480 struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3481 	u8	   vhca_id_valid[0x1];
3482 	u8	   reserved_at_1[0xf];
3483 	u8	   vhca_id[0x10];
3484 
3485 	u8	   reserved_at_20[0xa0];
3486 
3487 	u8	   cur_alloc_icm[0x20];
3488 
3489 	u8	   reserved_at_e0[0x120];
3490 };
3491 
3492 enum {
3493 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3494 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3495 };
3496 
3497 struct mlx5_ifc_cq_error_bits {
3498 	u8         reserved_at_0[0x8];
3499 	u8         cqn[0x18];
3500 
3501 	u8         reserved_at_20[0x20];
3502 
3503 	u8         reserved_at_40[0x18];
3504 	u8         syndrome[0x8];
3505 
3506 	u8         reserved_at_60[0x80];
3507 };
3508 
3509 struct mlx5_ifc_rdma_page_fault_event_bits {
3510 	u8         bytes_committed[0x20];
3511 
3512 	u8         r_key[0x20];
3513 
3514 	u8         reserved_at_40[0x10];
3515 	u8         packet_len[0x10];
3516 
3517 	u8         rdma_op_len[0x20];
3518 
3519 	u8         rdma_va[0x40];
3520 
3521 	u8         reserved_at_c0[0x5];
3522 	u8         rdma[0x1];
3523 	u8         write[0x1];
3524 	u8         requestor[0x1];
3525 	u8         qp_number[0x18];
3526 };
3527 
3528 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3529 	u8         bytes_committed[0x20];
3530 
3531 	u8         reserved_at_20[0x10];
3532 	u8         wqe_index[0x10];
3533 
3534 	u8         reserved_at_40[0x10];
3535 	u8         len[0x10];
3536 
3537 	u8         reserved_at_60[0x60];
3538 
3539 	u8         reserved_at_c0[0x5];
3540 	u8         rdma[0x1];
3541 	u8         write_read[0x1];
3542 	u8         requestor[0x1];
3543 	u8         qpn[0x18];
3544 };
3545 
3546 struct mlx5_ifc_qp_events_bits {
3547 	u8         reserved_at_0[0xa0];
3548 
3549 	u8         type[0x8];
3550 	u8         reserved_at_a8[0x18];
3551 
3552 	u8         reserved_at_c0[0x8];
3553 	u8         qpn_rqn_sqn[0x18];
3554 };
3555 
3556 struct mlx5_ifc_dct_events_bits {
3557 	u8         reserved_at_0[0xc0];
3558 
3559 	u8         reserved_at_c0[0x8];
3560 	u8         dct_number[0x18];
3561 };
3562 
3563 struct mlx5_ifc_comp_event_bits {
3564 	u8         reserved_at_0[0xc0];
3565 
3566 	u8         reserved_at_c0[0x8];
3567 	u8         cq_number[0x18];
3568 };
3569 
3570 enum {
3571 	MLX5_QPC_STATE_RST        = 0x0,
3572 	MLX5_QPC_STATE_INIT       = 0x1,
3573 	MLX5_QPC_STATE_RTR        = 0x2,
3574 	MLX5_QPC_STATE_RTS        = 0x3,
3575 	MLX5_QPC_STATE_SQER       = 0x4,
3576 	MLX5_QPC_STATE_ERR        = 0x6,
3577 	MLX5_QPC_STATE_SQD        = 0x7,
3578 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3579 };
3580 
3581 enum {
3582 	MLX5_QPC_ST_RC            = 0x0,
3583 	MLX5_QPC_ST_UC            = 0x1,
3584 	MLX5_QPC_ST_UD            = 0x2,
3585 	MLX5_QPC_ST_XRC           = 0x3,
3586 	MLX5_QPC_ST_DCI           = 0x5,
3587 	MLX5_QPC_ST_QP0           = 0x7,
3588 	MLX5_QPC_ST_QP1           = 0x8,
3589 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3590 	MLX5_QPC_ST_REG_UMR       = 0xc,
3591 };
3592 
3593 enum {
3594 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3595 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3596 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3597 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3598 };
3599 
3600 enum {
3601 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3602 };
3603 
3604 enum {
3605 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3606 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3607 };
3608 
3609 enum {
3610 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3611 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3612 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3613 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3614 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3615 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3616 };
3617 
3618 enum {
3619 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3620 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3621 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3622 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3623 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3624 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3625 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3626 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3627 };
3628 
3629 enum {
3630 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3631 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3632 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3633 };
3634 
3635 enum {
3636 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3637 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3638 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3639 };
3640 
3641 enum {
3642 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3643 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3644 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3645 };
3646 
3647 struct mlx5_ifc_qpc_bits {
3648 	u8         state[0x4];
3649 	u8         lag_tx_port_affinity[0x4];
3650 	u8         st[0x8];
3651 	u8         reserved_at_10[0x2];
3652 	u8	   isolate_vl_tc[0x1];
3653 	u8         pm_state[0x2];
3654 	u8         reserved_at_15[0x1];
3655 	u8         req_e2e_credit_mode[0x2];
3656 	u8         offload_type[0x4];
3657 	u8         end_padding_mode[0x2];
3658 	u8         reserved_at_1e[0x2];
3659 
3660 	u8         wq_signature[0x1];
3661 	u8         block_lb_mc[0x1];
3662 	u8         atomic_like_write_en[0x1];
3663 	u8         latency_sensitive[0x1];
3664 	u8         reserved_at_24[0x1];
3665 	u8         drain_sigerr[0x1];
3666 	u8         reserved_at_26[0x1];
3667 	u8         dp_ordering_force[0x1];
3668 	u8         pd[0x18];
3669 
3670 	u8         mtu[0x3];
3671 	u8         log_msg_max[0x5];
3672 	u8         reserved_at_48[0x1];
3673 	u8         log_rq_size[0x4];
3674 	u8         log_rq_stride[0x3];
3675 	u8         no_sq[0x1];
3676 	u8         log_sq_size[0x4];
3677 	u8         reserved_at_55[0x1];
3678 	u8	   retry_mode[0x2];
3679 	u8	   ts_format[0x2];
3680 	u8         reserved_at_5a[0x1];
3681 	u8         rlky[0x1];
3682 	u8         ulp_stateless_offload_mode[0x4];
3683 
3684 	u8         counter_set_id[0x8];
3685 	u8         uar_page[0x18];
3686 
3687 	u8         reserved_at_80[0x8];
3688 	u8         user_index[0x18];
3689 
3690 	u8         reserved_at_a0[0x3];
3691 	u8         log_page_size[0x5];
3692 	u8         remote_qpn[0x18];
3693 
3694 	struct mlx5_ifc_ads_bits primary_address_path;
3695 
3696 	struct mlx5_ifc_ads_bits secondary_address_path;
3697 
3698 	u8         log_ack_req_freq[0x4];
3699 	u8         reserved_at_384[0x4];
3700 	u8         log_sra_max[0x3];
3701 	u8         reserved_at_38b[0x2];
3702 	u8         retry_count[0x3];
3703 	u8         rnr_retry[0x3];
3704 	u8         reserved_at_393[0x1];
3705 	u8         fre[0x1];
3706 	u8         cur_rnr_retry[0x3];
3707 	u8         cur_retry_count[0x3];
3708 	u8         reserved_at_39b[0x5];
3709 
3710 	u8         reserved_at_3a0[0x20];
3711 
3712 	u8         reserved_at_3c0[0x8];
3713 	u8         next_send_psn[0x18];
3714 
3715 	u8         reserved_at_3e0[0x3];
3716 	u8	   log_num_dci_stream_channels[0x5];
3717 	u8         cqn_snd[0x18];
3718 
3719 	u8         reserved_at_400[0x3];
3720 	u8	   log_num_dci_errored_streams[0x5];
3721 	u8         deth_sqpn[0x18];
3722 
3723 	u8         reserved_at_420[0x20];
3724 
3725 	u8         reserved_at_440[0x8];
3726 	u8         last_acked_psn[0x18];
3727 
3728 	u8         reserved_at_460[0x8];
3729 	u8         ssn[0x18];
3730 
3731 	u8         reserved_at_480[0x8];
3732 	u8         log_rra_max[0x3];
3733 	u8         reserved_at_48b[0x1];
3734 	u8         atomic_mode[0x4];
3735 	u8         rre[0x1];
3736 	u8         rwe[0x1];
3737 	u8         rae[0x1];
3738 	u8         reserved_at_493[0x1];
3739 	u8         page_offset[0x6];
3740 	u8         reserved_at_49a[0x2];
3741 	u8         dp_ordering_1[0x1];
3742 	u8         cd_slave_receive[0x1];
3743 	u8         cd_slave_send[0x1];
3744 	u8         cd_master[0x1];
3745 
3746 	u8         reserved_at_4a0[0x3];
3747 	u8         min_rnr_nak[0x5];
3748 	u8         next_rcv_psn[0x18];
3749 
3750 	u8         reserved_at_4c0[0x8];
3751 	u8         xrcd[0x18];
3752 
3753 	u8         reserved_at_4e0[0x8];
3754 	u8         cqn_rcv[0x18];
3755 
3756 	u8         dbr_addr[0x40];
3757 
3758 	u8         q_key[0x20];
3759 
3760 	u8         reserved_at_560[0x5];
3761 	u8         rq_type[0x3];
3762 	u8         srqn_rmpn_xrqn[0x18];
3763 
3764 	u8         reserved_at_580[0x8];
3765 	u8         rmsn[0x18];
3766 
3767 	u8         hw_sq_wqebb_counter[0x10];
3768 	u8         sw_sq_wqebb_counter[0x10];
3769 
3770 	u8         hw_rq_counter[0x20];
3771 
3772 	u8         sw_rq_counter[0x20];
3773 
3774 	u8         reserved_at_600[0x20];
3775 
3776 	u8         reserved_at_620[0xf];
3777 	u8         cgs[0x1];
3778 	u8         cs_req[0x8];
3779 	u8         cs_res[0x8];
3780 
3781 	u8         dc_access_key[0x40];
3782 
3783 	u8         reserved_at_680[0x3];
3784 	u8         dbr_umem_valid[0x1];
3785 
3786 	u8         reserved_at_684[0xbc];
3787 };
3788 
3789 struct mlx5_ifc_roce_addr_layout_bits {
3790 	u8         source_l3_address[16][0x8];
3791 
3792 	u8         reserved_at_80[0x3];
3793 	u8         vlan_valid[0x1];
3794 	u8         vlan_id[0xc];
3795 	u8         source_mac_47_32[0x10];
3796 
3797 	u8         source_mac_31_0[0x20];
3798 
3799 	u8         reserved_at_c0[0x14];
3800 	u8         roce_l3_type[0x4];
3801 	u8         roce_version[0x8];
3802 
3803 	u8         reserved_at_e0[0x20];
3804 };
3805 
3806 struct mlx5_ifc_crypto_cap_bits {
3807 	u8    reserved_at_0[0x3];
3808 	u8    synchronize_dek[0x1];
3809 	u8    int_kek_manual[0x1];
3810 	u8    int_kek_auto[0x1];
3811 	u8    reserved_at_6[0x1a];
3812 
3813 	u8    reserved_at_20[0x3];
3814 	u8    log_dek_max_alloc[0x5];
3815 	u8    reserved_at_28[0x3];
3816 	u8    log_max_num_deks[0x5];
3817 	u8    reserved_at_30[0x10];
3818 
3819 	u8    reserved_at_40[0x20];
3820 
3821 	u8    reserved_at_60[0x3];
3822 	u8    log_dek_granularity[0x5];
3823 	u8    reserved_at_68[0x3];
3824 	u8    log_max_num_int_kek[0x5];
3825 	u8    sw_wrapped_dek[0x10];
3826 
3827 	u8    reserved_at_80[0x780];
3828 };
3829 
3830 struct mlx5_ifc_shampo_cap_bits {
3831 	u8    reserved_at_0[0x3];
3832 	u8    shampo_log_max_reservation_size[0x5];
3833 	u8    reserved_at_8[0x3];
3834 	u8    shampo_log_min_reservation_size[0x5];
3835 	u8    shampo_min_mss_size[0x10];
3836 
3837 	u8    shampo_header_split[0x1];
3838 	u8    shampo_header_split_data_merge[0x1];
3839 	u8    reserved_at_22[0x1];
3840 	u8    shampo_log_max_headers_entry_size[0x5];
3841 	u8    reserved_at_28[0x18];
3842 
3843 	u8    reserved_at_40[0x7c0];
3844 };
3845 
3846 union mlx5_ifc_hca_cap_union_bits {
3847 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3848 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3849 	struct mlx5_ifc_odp_cap_bits odp_cap;
3850 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3851 	struct mlx5_ifc_roce_cap_bits roce_cap;
3852 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3853 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3854 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3855 	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3856 	struct mlx5_ifc_esw_cap_bits esw_cap;
3857 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3858 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3859 	struct mlx5_ifc_qos_cap_bits qos_cap;
3860 	struct mlx5_ifc_debug_cap_bits debug_cap;
3861 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3862 	struct mlx5_ifc_tls_cap_bits tls_cap;
3863 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3864 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3865 	struct mlx5_ifc_tlp_dev_emu_capabilities_bits tlp_dev_emu_capabilities;
3866 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3867 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3868 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3869 	struct mlx5_ifc_psp_cap_bits psp_cap;
3870 	u8         reserved_at_0[0x8000];
3871 };
3872 
3873 enum {
3874 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3875 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3876 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3877 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3878 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3879 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3880 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3881 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3882 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3883 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3884 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3885 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3886 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3887 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3888 };
3889 
3890 enum {
3891 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3892 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3893 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3894 };
3895 
3896 enum {
3897 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3898 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3899 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP     = 0x2,
3900 };
3901 
3902 struct mlx5_ifc_vlan_bits {
3903 	u8         ethtype[0x10];
3904 	u8         prio[0x3];
3905 	u8         cfi[0x1];
3906 	u8         vid[0xc];
3907 };
3908 
3909 enum {
3910 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3911 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3912 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3913 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3914 };
3915 
3916 enum {
3917 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3918 };
3919 
3920 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3921 	u8        return_reg_id[0x4];
3922 	u8        aso_type[0x4];
3923 	u8        reserved_at_8[0x14];
3924 	u8        action[0x1];
3925 	u8        init_color[0x2];
3926 	u8        meter_id[0x1];
3927 };
3928 
3929 union mlx5_ifc_exe_aso_ctrl {
3930 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3931 };
3932 
3933 struct mlx5_ifc_execute_aso_bits {
3934 	u8        valid[0x1];
3935 	u8        reserved_at_1[0x7];
3936 	u8        aso_object_id[0x18];
3937 
3938 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3939 };
3940 
3941 struct mlx5_ifc_flow_context_bits {
3942 	struct mlx5_ifc_vlan_bits push_vlan;
3943 
3944 	u8         group_id[0x20];
3945 
3946 	u8         reserved_at_40[0x8];
3947 	u8         flow_tag[0x18];
3948 
3949 	u8         reserved_at_60[0x10];
3950 	u8         action[0x10];
3951 
3952 	u8         extended_destination[0x1];
3953 	u8         uplink_hairpin_en[0x1];
3954 	u8         flow_source[0x2];
3955 	u8         encrypt_decrypt_type[0x4];
3956 	u8         destination_list_size[0x18];
3957 
3958 	u8         reserved_at_a0[0x8];
3959 	u8         flow_counter_list_size[0x18];
3960 
3961 	u8         packet_reformat_id[0x20];
3962 
3963 	u8         modify_header_id[0x20];
3964 
3965 	struct mlx5_ifc_vlan_bits push_vlan_2;
3966 
3967 	u8         encrypt_decrypt_obj_id[0x20];
3968 	u8         reserved_at_140[0xc0];
3969 
3970 	struct mlx5_ifc_fte_match_param_bits match_value;
3971 
3972 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3973 
3974 	u8         reserved_at_1300[0x500];
3975 
3976 	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3977 };
3978 
3979 enum {
3980 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3981 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3982 };
3983 
3984 struct mlx5_ifc_xrc_srqc_bits {
3985 	u8         state[0x4];
3986 	u8         log_xrc_srq_size[0x4];
3987 	u8         reserved_at_8[0x18];
3988 
3989 	u8         wq_signature[0x1];
3990 	u8         cont_srq[0x1];
3991 	u8         reserved_at_22[0x1];
3992 	u8         rlky[0x1];
3993 	u8         basic_cyclic_rcv_wqe[0x1];
3994 	u8         log_rq_stride[0x3];
3995 	u8         xrcd[0x18];
3996 
3997 	u8         page_offset[0x6];
3998 	u8         reserved_at_46[0x1];
3999 	u8         dbr_umem_valid[0x1];
4000 	u8         cqn[0x18];
4001 
4002 	u8         reserved_at_60[0x20];
4003 
4004 	u8         user_index_equal_xrc_srqn[0x1];
4005 	u8         reserved_at_81[0x1];
4006 	u8         log_page_size[0x6];
4007 	u8         user_index[0x18];
4008 
4009 	u8         reserved_at_a0[0x20];
4010 
4011 	u8         reserved_at_c0[0x8];
4012 	u8         pd[0x18];
4013 
4014 	u8         lwm[0x10];
4015 	u8         wqe_cnt[0x10];
4016 
4017 	u8         reserved_at_100[0x40];
4018 
4019 	u8         db_record_addr_h[0x20];
4020 
4021 	u8         db_record_addr_l[0x1e];
4022 	u8         reserved_at_17e[0x2];
4023 
4024 	u8         reserved_at_180[0x80];
4025 };
4026 
4027 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
4028 	u8         counter_error_queues[0x20];
4029 
4030 	u8         total_error_queues[0x20];
4031 
4032 	u8         send_queue_priority_update_flow[0x20];
4033 
4034 	u8         reserved_at_60[0x20];
4035 
4036 	u8         nic_receive_steering_discard[0x40];
4037 
4038 	u8         receive_discard_vport_down[0x40];
4039 
4040 	u8         transmit_discard_vport_down[0x40];
4041 
4042 	u8         async_eq_overrun[0x20];
4043 
4044 	u8         comp_eq_overrun[0x20];
4045 
4046 	u8         reserved_at_180[0x20];
4047 
4048 	u8         invalid_command[0x20];
4049 
4050 	u8         quota_exceeded_command[0x20];
4051 
4052 	u8         internal_rq_out_of_buffer[0x20];
4053 
4054 	u8         cq_overrun[0x20];
4055 
4056 	u8         eth_wqe_too_small[0x20];
4057 
4058 	u8         reserved_at_220[0xc0];
4059 
4060 	u8         generated_pkt_steering_fail[0x40];
4061 
4062 	u8         handled_pkt_steering_fail[0x40];
4063 
4064 	u8         bar_uar_access[0x20];
4065 
4066 	u8         odp_local_triggered_page_fault[0x20];
4067 
4068 	u8         odp_remote_triggered_page_fault[0x20];
4069 
4070 	u8         reserved_at_3c0[0xc20];
4071 };
4072 
4073 struct mlx5_ifc_traffic_counter_bits {
4074 	u8         packets[0x40];
4075 
4076 	u8         octets[0x40];
4077 };
4078 
4079 struct mlx5_ifc_tisc_bits {
4080 	u8         strict_lag_tx_port_affinity[0x1];
4081 	u8         tls_en[0x1];
4082 	u8         reserved_at_2[0x2];
4083 	u8         lag_tx_port_affinity[0x04];
4084 
4085 	u8         reserved_at_8[0x4];
4086 	u8         prio[0x4];
4087 	u8         reserved_at_10[0x10];
4088 
4089 	u8         reserved_at_20[0x100];
4090 
4091 	u8         reserved_at_120[0x8];
4092 	u8         transport_domain[0x18];
4093 
4094 	u8         reserved_at_140[0x8];
4095 	u8         underlay_qpn[0x18];
4096 
4097 	u8         reserved_at_160[0x8];
4098 	u8         pd[0x18];
4099 
4100 	u8         reserved_at_180[0x380];
4101 };
4102 
4103 enum {
4104 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
4105 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
4106 };
4107 
4108 enum {
4109 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
4110 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
4111 };
4112 
4113 enum {
4114 	MLX5_RX_HASH_FN_NONE           = 0x0,
4115 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
4116 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
4117 };
4118 
4119 enum {
4120 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
4121 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
4122 };
4123 
4124 struct mlx5_ifc_tirc_bits {
4125 	u8         reserved_at_0[0x20];
4126 
4127 	u8         disp_type[0x4];
4128 	u8         tls_en[0x1];
4129 	u8         reserved_at_25[0x1b];
4130 
4131 	u8         reserved_at_40[0x40];
4132 
4133 	u8         reserved_at_80[0x4];
4134 	u8         lro_timeout_period_usecs[0x10];
4135 	u8         packet_merge_mask[0x4];
4136 	u8         lro_max_ip_payload_size[0x8];
4137 
4138 	u8         reserved_at_a0[0x40];
4139 
4140 	u8         reserved_at_e0[0x8];
4141 	u8         inline_rqn[0x18];
4142 
4143 	u8         rx_hash_symmetric[0x1];
4144 	u8         reserved_at_101[0x1];
4145 	u8         tunneled_offload_en[0x1];
4146 	u8         reserved_at_103[0x5];
4147 	u8         indirect_table[0x18];
4148 
4149 	u8         rx_hash_fn[0x4];
4150 	u8         reserved_at_124[0x2];
4151 	u8         self_lb_block[0x2];
4152 	u8         transport_domain[0x18];
4153 
4154 	u8         rx_hash_toeplitz_key[10][0x20];
4155 
4156 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4157 
4158 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4159 
4160 	u8         reserved_at_2c0[0x4c0];
4161 };
4162 
4163 enum {
4164 	MLX5_SRQC_STATE_GOOD   = 0x0,
4165 	MLX5_SRQC_STATE_ERROR  = 0x1,
4166 };
4167 
4168 struct mlx5_ifc_srqc_bits {
4169 	u8         state[0x4];
4170 	u8         log_srq_size[0x4];
4171 	u8         reserved_at_8[0x18];
4172 
4173 	u8         wq_signature[0x1];
4174 	u8         cont_srq[0x1];
4175 	u8         reserved_at_22[0x1];
4176 	u8         rlky[0x1];
4177 	u8         reserved_at_24[0x1];
4178 	u8         log_rq_stride[0x3];
4179 	u8         xrcd[0x18];
4180 
4181 	u8         page_offset[0x6];
4182 	u8         reserved_at_46[0x2];
4183 	u8         cqn[0x18];
4184 
4185 	u8         reserved_at_60[0x20];
4186 
4187 	u8         reserved_at_80[0x2];
4188 	u8         log_page_size[0x6];
4189 	u8         reserved_at_88[0x18];
4190 
4191 	u8         reserved_at_a0[0x20];
4192 
4193 	u8         reserved_at_c0[0x8];
4194 	u8         pd[0x18];
4195 
4196 	u8         lwm[0x10];
4197 	u8         wqe_cnt[0x10];
4198 
4199 	u8         reserved_at_100[0x40];
4200 
4201 	u8         dbr_addr[0x40];
4202 
4203 	u8         reserved_at_180[0x80];
4204 };
4205 
4206 enum {
4207 	MLX5_SQC_STATE_RST  = 0x0,
4208 	MLX5_SQC_STATE_RDY  = 0x1,
4209 	MLX5_SQC_STATE_ERR  = 0x3,
4210 };
4211 
4212 struct mlx5_ifc_sqc_bits {
4213 	u8         rlky[0x1];
4214 	u8         cd_master[0x1];
4215 	u8         fre[0x1];
4216 	u8         flush_in_error_en[0x1];
4217 	u8         allow_multi_pkt_send_wqe[0x1];
4218 	u8	   min_wqe_inline_mode[0x3];
4219 	u8         state[0x4];
4220 	u8         reg_umr[0x1];
4221 	u8         allow_swp[0x1];
4222 	u8         hairpin[0x1];
4223 	u8         non_wire[0x1];
4224 	u8         reserved_at_10[0xa];
4225 	u8	   ts_format[0x2];
4226 	u8	   reserved_at_1c[0x4];
4227 
4228 	u8         reserved_at_20[0x8];
4229 	u8         user_index[0x18];
4230 
4231 	u8         reserved_at_40[0x8];
4232 	u8         cqn[0x18];
4233 
4234 	u8         reserved_at_60[0x8];
4235 	u8         hairpin_peer_rq[0x18];
4236 
4237 	u8         reserved_at_80[0x10];
4238 	u8         hairpin_peer_vhca[0x10];
4239 
4240 	u8         reserved_at_a0[0x20];
4241 
4242 	u8         reserved_at_c0[0x8];
4243 	u8         ts_cqe_to_dest_cqn[0x18];
4244 
4245 	u8         reserved_at_e0[0x10];
4246 	u8         packet_pacing_rate_limit_index[0x10];
4247 	u8         tis_lst_sz[0x10];
4248 	u8         qos_queue_group_id[0x10];
4249 
4250 	u8         reserved_at_120[0x40];
4251 
4252 	u8         reserved_at_160[0x8];
4253 	u8         tis_num_0[0x18];
4254 
4255 	struct mlx5_ifc_wq_bits wq;
4256 };
4257 
4258 enum {
4259 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4260 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4261 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4262 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4263 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4264 	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,
4265 };
4266 
4267 enum {
4268 	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4269 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4270 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4271 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4272 	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4273 	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,
4274 };
4275 
4276 enum {
4277 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4278 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4279 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4280 	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,
4281 };
4282 
4283 enum {
4284 	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4285 	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4286 	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4287 	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,
4288 };
4289 
4290 struct mlx5_ifc_tsar_element_bits {
4291 	u8         traffic_class[0x4];
4292 	u8         reserved_at_4[0x4];
4293 	u8         tsar_type[0x8];
4294 	u8         reserved_at_10[0x10];
4295 };
4296 
4297 struct mlx5_ifc_vport_element_bits {
4298 	u8         reserved_at_0[0x4];
4299 	u8         eswitch_owner_vhca_id_valid[0x1];
4300 	u8         eswitch_owner_vhca_id[0xb];
4301 	u8         vport_number[0x10];
4302 };
4303 
4304 struct mlx5_ifc_vport_tc_element_bits {
4305 	u8         traffic_class[0x4];
4306 	u8         eswitch_owner_vhca_id_valid[0x1];
4307 	u8         eswitch_owner_vhca_id[0xb];
4308 	u8         vport_number[0x10];
4309 };
4310 
4311 union mlx5_ifc_element_attributes_bits {
4312 	struct mlx5_ifc_tsar_element_bits tsar;
4313 	struct mlx5_ifc_vport_element_bits vport;
4314 	struct mlx5_ifc_vport_tc_element_bits vport_tc;
4315 	u8 reserved_at_0[0x20];
4316 };
4317 
4318 struct mlx5_ifc_scheduling_context_bits {
4319 	u8         element_type[0x8];
4320 	u8         reserved_at_8[0x18];
4321 
4322 	union mlx5_ifc_element_attributes_bits element_attributes;
4323 
4324 	u8         parent_element_id[0x20];
4325 
4326 	u8         reserved_at_60[0x40];
4327 
4328 	u8         bw_share[0x20];
4329 
4330 	u8         max_average_bw[0x20];
4331 
4332 	u8         max_bw_obj_id[0x20];
4333 
4334 	u8         reserved_at_100[0x100];
4335 };
4336 
4337 struct mlx5_ifc_rqtc_bits {
4338 	u8    reserved_at_0[0xa0];
4339 
4340 	u8    reserved_at_a0[0x5];
4341 	u8    list_q_type[0x3];
4342 	u8    reserved_at_a8[0x8];
4343 	u8    rqt_max_size[0x10];
4344 
4345 	u8    rq_vhca_id_format[0x1];
4346 	u8    reserved_at_c1[0xf];
4347 	u8    rqt_actual_size[0x10];
4348 
4349 	u8    reserved_at_e0[0x6a0];
4350 
4351 	union {
4352 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4353 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4354 	};
4355 };
4356 
4357 enum {
4358 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4359 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4360 };
4361 
4362 enum {
4363 	MLX5_RQC_STATE_RST  = 0x0,
4364 	MLX5_RQC_STATE_RDY  = 0x1,
4365 	MLX5_RQC_STATE_ERR  = 0x3,
4366 };
4367 
4368 enum {
4369 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4370 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4371 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4372 };
4373 
4374 enum {
4375 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4376 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4377 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4378 };
4379 
4380 struct mlx5_ifc_rqc_bits {
4381 	u8         rlky[0x1];
4382 	u8	   delay_drop_en[0x1];
4383 	u8         scatter_fcs[0x1];
4384 	u8         vsd[0x1];
4385 	u8         mem_rq_type[0x4];
4386 	u8         state[0x4];
4387 	u8         reserved_at_c[0x1];
4388 	u8         flush_in_error_en[0x1];
4389 	u8         hairpin[0x1];
4390 	u8         reserved_at_f[0xb];
4391 	u8	   ts_format[0x2];
4392 	u8	   reserved_at_1c[0x4];
4393 
4394 	u8         reserved_at_20[0x8];
4395 	u8         user_index[0x18];
4396 
4397 	u8         reserved_at_40[0x8];
4398 	u8         cqn[0x18];
4399 
4400 	u8         counter_set_id[0x8];
4401 	u8         reserved_at_68[0x18];
4402 
4403 	u8         reserved_at_80[0x8];
4404 	u8         rmpn[0x18];
4405 
4406 	u8         reserved_at_a0[0x8];
4407 	u8         hairpin_peer_sq[0x18];
4408 
4409 	u8         reserved_at_c0[0x10];
4410 	u8         hairpin_peer_vhca[0x10];
4411 
4412 	u8         reserved_at_e0[0x46];
4413 	u8         shampo_no_match_alignment_granularity[0x2];
4414 	u8         reserved_at_128[0x6];
4415 	u8         shampo_match_criteria_type[0x2];
4416 	u8         reservation_timeout[0x10];
4417 
4418 	u8         reserved_at_140[0x40];
4419 
4420 	struct mlx5_ifc_wq_bits wq;
4421 };
4422 
4423 enum {
4424 	MLX5_RMPC_STATE_RDY  = 0x1,
4425 	MLX5_RMPC_STATE_ERR  = 0x3,
4426 };
4427 
4428 struct mlx5_ifc_rmpc_bits {
4429 	u8         reserved_at_0[0x8];
4430 	u8         state[0x4];
4431 	u8         reserved_at_c[0x14];
4432 
4433 	u8         basic_cyclic_rcv_wqe[0x1];
4434 	u8         reserved_at_21[0x1f];
4435 
4436 	u8         reserved_at_40[0x140];
4437 
4438 	struct mlx5_ifc_wq_bits wq;
4439 };
4440 
4441 enum {
4442 	VHCA_ID_TYPE_HW = 0,
4443 	VHCA_ID_TYPE_SW = 1,
4444 };
4445 
4446 struct mlx5_ifc_nic_vport_context_bits {
4447 	u8         reserved_at_0[0x5];
4448 	u8         min_wqe_inline_mode[0x3];
4449 	u8         reserved_at_8[0x15];
4450 	u8         disable_mc_local_lb[0x1];
4451 	u8         disable_uc_local_lb[0x1];
4452 	u8         roce_en[0x1];
4453 
4454 	u8         arm_change_event[0x1];
4455 	u8         reserved_at_21[0x1a];
4456 	u8         event_on_mtu[0x1];
4457 	u8         event_on_promisc_change[0x1];
4458 	u8         event_on_vlan_change[0x1];
4459 	u8         event_on_mc_address_change[0x1];
4460 	u8         event_on_uc_address_change[0x1];
4461 
4462 	u8         vhca_id_type[0x1];
4463 	u8         reserved_at_41[0xb];
4464 	u8	   affiliation_criteria[0x4];
4465 	u8	   affiliated_vhca_id[0x10];
4466 
4467 	u8	   reserved_at_60[0xa0];
4468 
4469 	u8	   reserved_at_100[0x1];
4470 	u8         sd_group[0x3];
4471 	u8	   reserved_at_104[0x1c];
4472 
4473 	u8	   reserved_at_120[0x10];
4474 	u8         mtu[0x10];
4475 
4476 	u8         system_image_guid[0x40];
4477 	u8         port_guid[0x40];
4478 	u8         node_guid[0x40];
4479 
4480 	u8         reserved_at_200[0x140];
4481 	u8         qkey_violation_counter[0x10];
4482 	u8         reserved_at_350[0x430];
4483 
4484 	u8         promisc_uc[0x1];
4485 	u8         promisc_mc[0x1];
4486 	u8         promisc_all[0x1];
4487 	u8         reserved_at_783[0x2];
4488 	u8         allowed_list_type[0x3];
4489 	u8         reserved_at_788[0xc];
4490 	u8         allowed_list_size[0xc];
4491 
4492 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4493 
4494 	u8         reserved_at_7e0[0x20];
4495 
4496 	u8         current_uc_mac_address[][0x40];
4497 };
4498 
4499 enum {
4500 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4501 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4502 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4503 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4504 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4505 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4506 	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4507 };
4508 
4509 enum {
4510 	MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0,
4511 };
4512 
4513 struct mlx5_ifc_mkc_bits {
4514 	u8         reserved_at_0[0x1];
4515 	u8         free[0x1];
4516 	u8         reserved_at_2[0x1];
4517 	u8         access_mode_4_2[0x3];
4518 	u8         reserved_at_6[0x7];
4519 	u8         relaxed_ordering_write[0x1];
4520 	u8         reserved_at_e[0x1];
4521 	u8         small_fence_on_rdma_read_response[0x1];
4522 	u8         umr_en[0x1];
4523 	u8         a[0x1];
4524 	u8         rw[0x1];
4525 	u8         rr[0x1];
4526 	u8         lw[0x1];
4527 	u8         lr[0x1];
4528 	u8         access_mode_1_0[0x2];
4529 	u8         reserved_at_18[0x2];
4530 	u8         ma_translation_mode[0x2];
4531 	u8         reserved_at_1c[0x4];
4532 
4533 	u8         qpn[0x18];
4534 	u8         mkey_7_0[0x8];
4535 
4536 	u8         reserved_at_40[0x20];
4537 
4538 	u8         length64[0x1];
4539 	u8         bsf_en[0x1];
4540 	u8         sync_umr[0x1];
4541 	u8         reserved_at_63[0x2];
4542 	u8         expected_sigerr_count[0x1];
4543 	u8         reserved_at_66[0x1];
4544 	u8         en_rinval[0x1];
4545 	u8         pd[0x18];
4546 
4547 	u8         start_addr[0x40];
4548 
4549 	u8         len[0x40];
4550 
4551 	u8         bsf_octword_size[0x20];
4552 
4553 	u8         reserved_at_120[0x60];
4554 
4555 	u8         crossing_target_vhca_id[0x10];
4556 	u8         reserved_at_190[0x10];
4557 
4558 	u8         translations_octword_size[0x20];
4559 
4560 	u8         reserved_at_1c0[0x19];
4561 	u8         relaxed_ordering_read[0x1];
4562 	u8         log_page_size[0x6];
4563 
4564 	u8         reserved_at_1e0[0x5];
4565 	u8         pcie_tph_en[0x1];
4566 	u8         pcie_tph_ph[0x2];
4567 	u8         pcie_tph_steering_tag_index[0x8];
4568 	u8         reserved_at_1f0[0x10];
4569 };
4570 
4571 struct mlx5_ifc_pkey_bits {
4572 	u8         reserved_at_0[0x10];
4573 	u8         pkey[0x10];
4574 };
4575 
4576 struct mlx5_ifc_array128_auto_bits {
4577 	u8         array128_auto[16][0x8];
4578 };
4579 
4580 struct mlx5_ifc_hca_vport_context_bits {
4581 	u8         field_select[0x20];
4582 
4583 	u8         reserved_at_20[0xe0];
4584 
4585 	u8         sm_virt_aware[0x1];
4586 	u8         has_smi[0x1];
4587 	u8         has_raw[0x1];
4588 	u8         grh_required[0x1];
4589 	u8         reserved_at_104[0x4];
4590 	u8         num_port_plane[0x8];
4591 	u8         port_physical_state[0x4];
4592 	u8         vport_state_policy[0x4];
4593 	u8         port_state[0x4];
4594 	u8         vport_state[0x4];
4595 
4596 	u8         reserved_at_120[0x20];
4597 
4598 	u8         system_image_guid[0x40];
4599 
4600 	u8         port_guid[0x40];
4601 
4602 	u8         node_guid[0x40];
4603 
4604 	u8         cap_mask1[0x20];
4605 
4606 	u8         cap_mask1_field_select[0x20];
4607 
4608 	u8         cap_mask2[0x20];
4609 
4610 	u8         cap_mask2_field_select[0x20];
4611 
4612 	u8         reserved_at_280[0x80];
4613 
4614 	u8         lid[0x10];
4615 	u8         reserved_at_310[0x4];
4616 	u8         init_type_reply[0x4];
4617 	u8         lmc[0x3];
4618 	u8         subnet_timeout[0x5];
4619 
4620 	u8         sm_lid[0x10];
4621 	u8         sm_sl[0x4];
4622 	u8         reserved_at_334[0xc];
4623 
4624 	u8         qkey_violation_counter[0x10];
4625 	u8         pkey_violation_counter[0x10];
4626 
4627 	u8         reserved_at_360[0xca0];
4628 };
4629 
4630 struct mlx5_ifc_esw_vport_context_bits {
4631 	u8         fdb_to_vport_reg_c[0x1];
4632 	u8         reserved_at_1[0x2];
4633 	u8         vport_svlan_strip[0x1];
4634 	u8         vport_cvlan_strip[0x1];
4635 	u8         vport_svlan_insert[0x1];
4636 	u8         vport_cvlan_insert[0x2];
4637 	u8         fdb_to_vport_reg_c_id[0x8];
4638 	u8         reserved_at_10[0x10];
4639 
4640 	u8         reserved_at_20[0x20];
4641 
4642 	u8         svlan_cfi[0x1];
4643 	u8         svlan_pcp[0x3];
4644 	u8         svlan_id[0xc];
4645 	u8         cvlan_cfi[0x1];
4646 	u8         cvlan_pcp[0x3];
4647 	u8         cvlan_id[0xc];
4648 
4649 	u8         reserved_at_60[0x720];
4650 
4651 	u8         sw_steering_vport_icm_address_rx[0x40];
4652 
4653 	u8         sw_steering_vport_icm_address_tx[0x40];
4654 };
4655 
4656 enum {
4657 	MLX5_EQC_STATUS_OK                = 0x0,
4658 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4659 };
4660 
4661 enum {
4662 	MLX5_EQC_ST_ARMED  = 0x9,
4663 	MLX5_EQC_ST_FIRED  = 0xa,
4664 };
4665 
4666 struct mlx5_ifc_eqc_bits {
4667 	u8         status[0x4];
4668 	u8         reserved_at_4[0x9];
4669 	u8         ec[0x1];
4670 	u8         oi[0x1];
4671 	u8         reserved_at_f[0x5];
4672 	u8         st[0x4];
4673 	u8         reserved_at_18[0x8];
4674 
4675 	u8         reserved_at_20[0x20];
4676 
4677 	u8         reserved_at_40[0x14];
4678 	u8         page_offset[0x6];
4679 	u8         reserved_at_5a[0x6];
4680 
4681 	u8         reserved_at_60[0x3];
4682 	u8         log_eq_size[0x5];
4683 	u8         uar_page[0x18];
4684 
4685 	u8         reserved_at_80[0x20];
4686 
4687 	u8         reserved_at_a0[0x14];
4688 	u8         intr[0xc];
4689 
4690 	u8         reserved_at_c0[0x3];
4691 	u8         log_page_size[0x5];
4692 	u8         reserved_at_c8[0x18];
4693 
4694 	u8         reserved_at_e0[0x60];
4695 
4696 	u8         reserved_at_140[0x8];
4697 	u8         consumer_counter[0x18];
4698 
4699 	u8         reserved_at_160[0x8];
4700 	u8         producer_counter[0x18];
4701 
4702 	u8         reserved_at_180[0x80];
4703 };
4704 
4705 enum {
4706 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4707 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4708 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4709 };
4710 
4711 enum {
4712 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4713 	MLX5_DCTC_CS_RES_NA         = 0x1,
4714 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4715 };
4716 
4717 enum {
4718 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4719 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4720 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4721 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4722 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4723 };
4724 
4725 struct mlx5_ifc_dctc_bits {
4726 	u8         reserved_at_0[0x4];
4727 	u8         state[0x4];
4728 	u8         reserved_at_8[0x18];
4729 
4730 	u8         reserved_at_20[0x7];
4731 	u8         dp_ordering_force[0x1];
4732 	u8         user_index[0x18];
4733 
4734 	u8         reserved_at_40[0x8];
4735 	u8         cqn[0x18];
4736 
4737 	u8         counter_set_id[0x8];
4738 	u8         atomic_mode[0x4];
4739 	u8         rre[0x1];
4740 	u8         rwe[0x1];
4741 	u8         rae[0x1];
4742 	u8         atomic_like_write_en[0x1];
4743 	u8         latency_sensitive[0x1];
4744 	u8         rlky[0x1];
4745 	u8         free_ar[0x1];
4746 	u8         reserved_at_73[0x1];
4747 	u8         dp_ordering_1[0x1];
4748 	u8         reserved_at_75[0xb];
4749 
4750 	u8         reserved_at_80[0x8];
4751 	u8         cs_res[0x8];
4752 	u8         reserved_at_90[0x3];
4753 	u8         min_rnr_nak[0x5];
4754 	u8         reserved_at_98[0x8];
4755 
4756 	u8         reserved_at_a0[0x8];
4757 	u8         srqn_xrqn[0x18];
4758 
4759 	u8         reserved_at_c0[0x8];
4760 	u8         pd[0x18];
4761 
4762 	u8         tclass[0x8];
4763 	u8         reserved_at_e8[0x4];
4764 	u8         flow_label[0x14];
4765 
4766 	u8         dc_access_key[0x40];
4767 
4768 	u8         reserved_at_140[0x5];
4769 	u8         mtu[0x3];
4770 	u8         port[0x8];
4771 	u8         pkey_index[0x10];
4772 
4773 	u8         reserved_at_160[0x8];
4774 	u8         my_addr_index[0x8];
4775 	u8         reserved_at_170[0x8];
4776 	u8         hop_limit[0x8];
4777 
4778 	u8         dc_access_key_violation_count[0x20];
4779 
4780 	u8         reserved_at_1a0[0x14];
4781 	u8         dei_cfi[0x1];
4782 	u8         eth_prio[0x3];
4783 	u8         ecn[0x2];
4784 	u8         dscp[0x6];
4785 
4786 	u8         reserved_at_1c0[0x20];
4787 	u8         ece[0x20];
4788 };
4789 
4790 enum {
4791 	MLX5_CQC_STATUS_OK             = 0x0,
4792 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4793 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4794 };
4795 
4796 enum {
4797 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4798 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4799 };
4800 
4801 enum {
4802 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4803 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4804 	MLX5_CQC_ST_FIRED                                 = 0xa,
4805 };
4806 
4807 enum mlx5_cq_period_mode {
4808 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4809 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4810 	MLX5_CQ_PERIOD_NUM_MODES,
4811 };
4812 
4813 struct mlx5_ifc_cqc_bits {
4814 	u8         status[0x4];
4815 	u8         reserved_at_4[0x2];
4816 	u8         dbr_umem_valid[0x1];
4817 	u8         apu_cq[0x1];
4818 	u8         cqe_sz[0x3];
4819 	u8         cc[0x1];
4820 	u8         reserved_at_c[0x1];
4821 	u8         scqe_break_moderation_en[0x1];
4822 	u8         oi[0x1];
4823 	u8         cq_period_mode[0x2];
4824 	u8         cqe_comp_en[0x1];
4825 	u8         mini_cqe_res_format[0x2];
4826 	u8         st[0x4];
4827 	u8         reserved_at_18[0x6];
4828 	u8         cqe_compression_layout[0x2];
4829 
4830 	u8         reserved_at_20[0x20];
4831 
4832 	u8         reserved_at_40[0x14];
4833 	u8         page_offset[0x6];
4834 	u8         reserved_at_5a[0x6];
4835 
4836 	u8         reserved_at_60[0x3];
4837 	u8         log_cq_size[0x5];
4838 	u8         uar_page[0x18];
4839 
4840 	u8         reserved_at_80[0x4];
4841 	u8         cq_period[0xc];
4842 	u8         cq_max_count[0x10];
4843 
4844 	u8         c_eqn_or_apu_element[0x20];
4845 
4846 	u8         reserved_at_c0[0x3];
4847 	u8         log_page_size[0x5];
4848 	u8         reserved_at_c8[0x18];
4849 
4850 	u8         reserved_at_e0[0x20];
4851 
4852 	u8         reserved_at_100[0x8];
4853 	u8         last_notified_index[0x18];
4854 
4855 	u8         reserved_at_120[0x8];
4856 	u8         last_solicit_index[0x18];
4857 
4858 	u8         reserved_at_140[0x8];
4859 	u8         consumer_counter[0x18];
4860 
4861 	u8         reserved_at_160[0x8];
4862 	u8         producer_counter[0x18];
4863 
4864 	u8         reserved_at_180[0x40];
4865 
4866 	u8         dbr_addr[0x40];
4867 };
4868 
4869 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4870 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4871 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4872 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4873 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4874 	u8         reserved_at_0[0x800];
4875 };
4876 
4877 struct mlx5_ifc_query_adapter_param_block_bits {
4878 	u8         reserved_at_0[0xc0];
4879 
4880 	u8         reserved_at_c0[0x8];
4881 	u8         ieee_vendor_id[0x18];
4882 
4883 	u8         reserved_at_e0[0x10];
4884 	u8         vsd_vendor_id[0x10];
4885 
4886 	u8         vsd[208][0x8];
4887 
4888 	u8         vsd_contd_psid[16][0x8];
4889 };
4890 
4891 enum {
4892 	MLX5_XRQC_STATE_GOOD   = 0x0,
4893 	MLX5_XRQC_STATE_ERROR  = 0x1,
4894 };
4895 
4896 enum {
4897 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4898 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4899 };
4900 
4901 enum {
4902 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4903 };
4904 
4905 struct mlx5_ifc_tag_matching_topology_context_bits {
4906 	u8         log_matching_list_sz[0x4];
4907 	u8         reserved_at_4[0xc];
4908 	u8         append_next_index[0x10];
4909 
4910 	u8         sw_phase_cnt[0x10];
4911 	u8         hw_phase_cnt[0x10];
4912 
4913 	u8         reserved_at_40[0x40];
4914 };
4915 
4916 struct mlx5_ifc_xrqc_bits {
4917 	u8         state[0x4];
4918 	u8         rlkey[0x1];
4919 	u8         reserved_at_5[0xf];
4920 	u8         topology[0x4];
4921 	u8         reserved_at_18[0x4];
4922 	u8         offload[0x4];
4923 
4924 	u8         reserved_at_20[0x8];
4925 	u8         user_index[0x18];
4926 
4927 	u8         reserved_at_40[0x8];
4928 	u8         cqn[0x18];
4929 
4930 	u8         reserved_at_60[0xa0];
4931 
4932 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4933 
4934 	u8         reserved_at_180[0x280];
4935 
4936 	struct mlx5_ifc_wq_bits wq;
4937 };
4938 
4939 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4940 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4941 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4942 	u8         reserved_at_0[0x20];
4943 };
4944 
4945 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4946 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4947 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4948 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4949 	u8         reserved_at_0[0x20];
4950 };
4951 
4952 struct mlx5_ifc_rs_histogram_cntrs_bits {
4953 	u8         hist[16][0x40];
4954 	u8         reserved_at_400[0x2c0];
4955 };
4956 
4957 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4958 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4959 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4960 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4961 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4962 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4963 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4964 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4965 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4966 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4967 	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4968 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4969 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4970 	struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;
4971 	struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs;
4972 	u8         reserved_at_0[0x7c0];
4973 };
4974 
4975 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4976 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4977 	u8         reserved_at_0[0x7c0];
4978 };
4979 
4980 union mlx5_ifc_event_auto_bits {
4981 	struct mlx5_ifc_comp_event_bits comp_event;
4982 	struct mlx5_ifc_dct_events_bits dct_events;
4983 	struct mlx5_ifc_qp_events_bits qp_events;
4984 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4985 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4986 	struct mlx5_ifc_cq_error_bits cq_error;
4987 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4988 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4989 	struct mlx5_ifc_gpio_event_bits gpio_event;
4990 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4991 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4992 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4993 	u8         reserved_at_0[0xe0];
4994 };
4995 
4996 struct mlx5_ifc_health_buffer_bits {
4997 	u8         reserved_at_0[0x100];
4998 
4999 	u8         assert_existptr[0x20];
5000 
5001 	u8         assert_callra[0x20];
5002 
5003 	u8         reserved_at_140[0x20];
5004 
5005 	u8         time[0x20];
5006 
5007 	u8         fw_version[0x20];
5008 
5009 	u8         hw_id[0x20];
5010 
5011 	u8         rfr[0x1];
5012 	u8         reserved_at_1c1[0x3];
5013 	u8         valid[0x1];
5014 	u8         severity[0x3];
5015 	u8         reserved_at_1c8[0x18];
5016 
5017 	u8         irisc_index[0x8];
5018 	u8         synd[0x8];
5019 	u8         ext_synd[0x10];
5020 };
5021 
5022 struct mlx5_ifc_register_loopback_control_bits {
5023 	u8         no_lb[0x1];
5024 	u8         reserved_at_1[0x7];
5025 	u8         port[0x8];
5026 	u8         reserved_at_10[0x10];
5027 
5028 	u8         reserved_at_20[0x60];
5029 };
5030 
5031 enum {
5032 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
5033 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
5034 };
5035 
5036 struct mlx5_ifc_teardown_hca_out_bits {
5037 	u8         status[0x8];
5038 	u8         reserved_at_8[0x18];
5039 
5040 	u8         syndrome[0x20];
5041 
5042 	u8         reserved_at_40[0x3f];
5043 
5044 	u8         state[0x1];
5045 };
5046 
5047 enum {
5048 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
5049 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
5050 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
5051 };
5052 
5053 struct mlx5_ifc_teardown_hca_in_bits {
5054 	u8         opcode[0x10];
5055 	u8         reserved_at_10[0x10];
5056 
5057 	u8         reserved_at_20[0x10];
5058 	u8         op_mod[0x10];
5059 
5060 	u8         reserved_at_40[0x10];
5061 	u8         profile[0x10];
5062 
5063 	u8         reserved_at_60[0x20];
5064 };
5065 
5066 struct mlx5_ifc_sqerr2rts_qp_out_bits {
5067 	u8         status[0x8];
5068 	u8         reserved_at_8[0x18];
5069 
5070 	u8         syndrome[0x20];
5071 
5072 	u8         reserved_at_40[0x40];
5073 };
5074 
5075 struct mlx5_ifc_sqerr2rts_qp_in_bits {
5076 	u8         opcode[0x10];
5077 	u8         uid[0x10];
5078 
5079 	u8         reserved_at_20[0x10];
5080 	u8         op_mod[0x10];
5081 
5082 	u8         reserved_at_40[0x8];
5083 	u8         qpn[0x18];
5084 
5085 	u8         reserved_at_60[0x20];
5086 
5087 	u8         opt_param_mask[0x20];
5088 
5089 	u8         reserved_at_a0[0x20];
5090 
5091 	struct mlx5_ifc_qpc_bits qpc;
5092 
5093 	u8         reserved_at_800[0x80];
5094 };
5095 
5096 struct mlx5_ifc_sqd2rts_qp_out_bits {
5097 	u8         status[0x8];
5098 	u8         reserved_at_8[0x18];
5099 
5100 	u8         syndrome[0x20];
5101 
5102 	u8         reserved_at_40[0x40];
5103 };
5104 
5105 struct mlx5_ifc_sqd2rts_qp_in_bits {
5106 	u8         opcode[0x10];
5107 	u8         uid[0x10];
5108 
5109 	u8         reserved_at_20[0x10];
5110 	u8         op_mod[0x10];
5111 
5112 	u8         reserved_at_40[0x8];
5113 	u8         qpn[0x18];
5114 
5115 	u8         reserved_at_60[0x20];
5116 
5117 	u8         opt_param_mask[0x20];
5118 
5119 	u8         reserved_at_a0[0x20];
5120 
5121 	struct mlx5_ifc_qpc_bits qpc;
5122 
5123 	u8         reserved_at_800[0x80];
5124 };
5125 
5126 struct mlx5_ifc_set_roce_address_out_bits {
5127 	u8         status[0x8];
5128 	u8         reserved_at_8[0x18];
5129 
5130 	u8         syndrome[0x20];
5131 
5132 	u8         reserved_at_40[0x40];
5133 };
5134 
5135 struct mlx5_ifc_set_roce_address_in_bits {
5136 	u8         opcode[0x10];
5137 	u8         reserved_at_10[0x10];
5138 
5139 	u8         reserved_at_20[0x10];
5140 	u8         op_mod[0x10];
5141 
5142 	u8         roce_address_index[0x10];
5143 	u8         reserved_at_50[0xc];
5144 	u8	   vhca_port_num[0x4];
5145 
5146 	u8         reserved_at_60[0x20];
5147 
5148 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5149 };
5150 
5151 struct mlx5_ifc_set_mad_demux_out_bits {
5152 	u8         status[0x8];
5153 	u8         reserved_at_8[0x18];
5154 
5155 	u8         syndrome[0x20];
5156 
5157 	u8         reserved_at_40[0x40];
5158 };
5159 
5160 enum {
5161 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
5162 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
5163 };
5164 
5165 struct mlx5_ifc_set_mad_demux_in_bits {
5166 	u8         opcode[0x10];
5167 	u8         reserved_at_10[0x10];
5168 
5169 	u8         reserved_at_20[0x10];
5170 	u8         op_mod[0x10];
5171 
5172 	u8         reserved_at_40[0x20];
5173 
5174 	u8         reserved_at_60[0x6];
5175 	u8         demux_mode[0x2];
5176 	u8         reserved_at_68[0x18];
5177 };
5178 
5179 struct mlx5_ifc_set_l2_table_entry_out_bits {
5180 	u8         status[0x8];
5181 	u8         reserved_at_8[0x18];
5182 
5183 	u8         syndrome[0x20];
5184 
5185 	u8         reserved_at_40[0x40];
5186 };
5187 
5188 struct mlx5_ifc_set_l2_table_entry_in_bits {
5189 	u8         opcode[0x10];
5190 	u8         reserved_at_10[0x10];
5191 
5192 	u8         reserved_at_20[0x10];
5193 	u8         op_mod[0x10];
5194 
5195 	u8         reserved_at_40[0x60];
5196 
5197 	u8         reserved_at_a0[0x8];
5198 	u8         table_index[0x18];
5199 
5200 	u8         reserved_at_c0[0x20];
5201 
5202 	u8         reserved_at_e0[0x10];
5203 	u8         silent_mode_valid[0x1];
5204 	u8         silent_mode[0x1];
5205 	u8         reserved_at_f2[0x1];
5206 	u8         vlan_valid[0x1];
5207 	u8         vlan[0xc];
5208 
5209 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5210 
5211 	u8         reserved_at_140[0xc0];
5212 };
5213 
5214 struct mlx5_ifc_set_issi_out_bits {
5215 	u8         status[0x8];
5216 	u8         reserved_at_8[0x18];
5217 
5218 	u8         syndrome[0x20];
5219 
5220 	u8         reserved_at_40[0x40];
5221 };
5222 
5223 struct mlx5_ifc_set_issi_in_bits {
5224 	u8         opcode[0x10];
5225 	u8         reserved_at_10[0x10];
5226 
5227 	u8         reserved_at_20[0x10];
5228 	u8         op_mod[0x10];
5229 
5230 	u8         reserved_at_40[0x10];
5231 	u8         current_issi[0x10];
5232 
5233 	u8         reserved_at_60[0x20];
5234 };
5235 
5236 struct mlx5_ifc_set_hca_cap_out_bits {
5237 	u8         status[0x8];
5238 	u8         reserved_at_8[0x18];
5239 
5240 	u8         syndrome[0x20];
5241 
5242 	u8         reserved_at_40[0x40];
5243 };
5244 
5245 struct mlx5_ifc_set_hca_cap_in_bits {
5246 	u8         opcode[0x10];
5247 	u8         reserved_at_10[0x10];
5248 
5249 	u8         reserved_at_20[0x10];
5250 	u8         op_mod[0x10];
5251 
5252 	u8         other_function[0x1];
5253 	u8         ec_vf_function[0x1];
5254 	u8         reserved_at_42[0x1];
5255 	u8         function_id_type[0x1];
5256 	u8         reserved_at_44[0xc];
5257 	u8         function_id[0x10];
5258 
5259 	u8         reserved_at_60[0x20];
5260 
5261 	union mlx5_ifc_hca_cap_union_bits capability;
5262 };
5263 
5264 enum {
5265 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5266 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5267 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5268 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5269 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5270 };
5271 
5272 struct mlx5_ifc_set_fte_out_bits {
5273 	u8         status[0x8];
5274 	u8         reserved_at_8[0x18];
5275 
5276 	u8         syndrome[0x20];
5277 
5278 	u8         reserved_at_40[0x40];
5279 };
5280 
5281 struct mlx5_ifc_set_fte_in_bits {
5282 	u8         opcode[0x10];
5283 	u8         reserved_at_10[0x10];
5284 
5285 	u8         reserved_at_20[0x10];
5286 	u8         op_mod[0x10];
5287 
5288 	u8         other_vport[0x1];
5289 	u8         other_eswitch[0x1];
5290 	u8         reserved_at_42[0xe];
5291 	u8         vport_number[0x10];
5292 
5293 	u8         reserved_at_60[0x20];
5294 
5295 	u8         table_type[0x8];
5296 	u8         reserved_at_88[0x8];
5297 	u8         eswitch_owner_vhca_id[0x10];
5298 
5299 	u8         reserved_at_a0[0x8];
5300 	u8         table_id[0x18];
5301 
5302 	u8         ignore_flow_level[0x1];
5303 	u8         reserved_at_c1[0x17];
5304 	u8         modify_enable_mask[0x8];
5305 
5306 	u8         reserved_at_e0[0x20];
5307 
5308 	u8         flow_index[0x20];
5309 
5310 	u8         reserved_at_120[0xe0];
5311 
5312 	struct mlx5_ifc_flow_context_bits flow_context;
5313 };
5314 
5315 struct mlx5_ifc_dest_format_bits {
5316 	u8         destination_type[0x8];
5317 	u8         destination_id[0x18];
5318 
5319 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5320 	u8         packet_reformat[0x1];
5321 	u8         reserved_at_22[0xe];
5322 	u8         destination_eswitch_owner_vhca_id[0x10];
5323 };
5324 
5325 struct mlx5_ifc_rts2rts_qp_out_bits {
5326 	u8         status[0x8];
5327 	u8         reserved_at_8[0x18];
5328 
5329 	u8         syndrome[0x20];
5330 
5331 	u8         reserved_at_40[0x20];
5332 	u8         ece[0x20];
5333 };
5334 
5335 struct mlx5_ifc_rts2rts_qp_in_bits {
5336 	u8         opcode[0x10];
5337 	u8         uid[0x10];
5338 
5339 	u8         reserved_at_20[0x10];
5340 	u8         op_mod[0x10];
5341 
5342 	u8         reserved_at_40[0x8];
5343 	u8         qpn[0x18];
5344 
5345 	u8         reserved_at_60[0x20];
5346 
5347 	u8         opt_param_mask[0x20];
5348 
5349 	u8         ece[0x20];
5350 
5351 	struct mlx5_ifc_qpc_bits qpc;
5352 
5353 	u8         reserved_at_800[0x80];
5354 };
5355 
5356 struct mlx5_ifc_rtr2rts_qp_out_bits {
5357 	u8         status[0x8];
5358 	u8         reserved_at_8[0x18];
5359 
5360 	u8         syndrome[0x20];
5361 
5362 	u8         reserved_at_40[0x20];
5363 	u8         ece[0x20];
5364 };
5365 
5366 struct mlx5_ifc_rtr2rts_qp_in_bits {
5367 	u8         opcode[0x10];
5368 	u8         uid[0x10];
5369 
5370 	u8         reserved_at_20[0x10];
5371 	u8         op_mod[0x10];
5372 
5373 	u8         reserved_at_40[0x8];
5374 	u8         qpn[0x18];
5375 
5376 	u8         reserved_at_60[0x20];
5377 
5378 	u8         opt_param_mask[0x20];
5379 
5380 	u8         ece[0x20];
5381 
5382 	struct mlx5_ifc_qpc_bits qpc;
5383 
5384 	u8         reserved_at_800[0x80];
5385 };
5386 
5387 struct mlx5_ifc_rst2init_qp_out_bits {
5388 	u8         status[0x8];
5389 	u8         reserved_at_8[0x18];
5390 
5391 	u8         syndrome[0x20];
5392 
5393 	u8         reserved_at_40[0x20];
5394 	u8         ece[0x20];
5395 };
5396 
5397 struct mlx5_ifc_rst2init_qp_in_bits {
5398 	u8         opcode[0x10];
5399 	u8         uid[0x10];
5400 
5401 	u8         reserved_at_20[0x10];
5402 	u8         op_mod[0x10];
5403 
5404 	u8         reserved_at_40[0x8];
5405 	u8         qpn[0x18];
5406 
5407 	u8         reserved_at_60[0x20];
5408 
5409 	u8         opt_param_mask[0x20];
5410 
5411 	u8         ece[0x20];
5412 
5413 	struct mlx5_ifc_qpc_bits qpc;
5414 
5415 	u8         reserved_at_800[0x80];
5416 };
5417 
5418 struct mlx5_ifc_query_xrq_out_bits {
5419 	u8         status[0x8];
5420 	u8         reserved_at_8[0x18];
5421 
5422 	u8         syndrome[0x20];
5423 
5424 	u8         reserved_at_40[0x40];
5425 
5426 	struct mlx5_ifc_xrqc_bits xrq_context;
5427 };
5428 
5429 struct mlx5_ifc_query_xrq_in_bits {
5430 	u8         opcode[0x10];
5431 	u8         reserved_at_10[0x10];
5432 
5433 	u8         reserved_at_20[0x10];
5434 	u8         op_mod[0x10];
5435 
5436 	u8         reserved_at_40[0x8];
5437 	u8         xrqn[0x18];
5438 
5439 	u8         reserved_at_60[0x20];
5440 };
5441 
5442 struct mlx5_ifc_query_xrc_srq_out_bits {
5443 	u8         status[0x8];
5444 	u8         reserved_at_8[0x18];
5445 
5446 	u8         syndrome[0x20];
5447 
5448 	u8         reserved_at_40[0x40];
5449 
5450 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5451 
5452 	u8         reserved_at_280[0x600];
5453 
5454 	u8         pas[][0x40];
5455 };
5456 
5457 struct mlx5_ifc_query_xrc_srq_in_bits {
5458 	u8         opcode[0x10];
5459 	u8         reserved_at_10[0x10];
5460 
5461 	u8         reserved_at_20[0x10];
5462 	u8         op_mod[0x10];
5463 
5464 	u8         reserved_at_40[0x8];
5465 	u8         xrc_srqn[0x18];
5466 
5467 	u8         reserved_at_60[0x20];
5468 };
5469 
5470 enum {
5471 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5472 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5473 };
5474 
5475 struct mlx5_ifc_query_vport_state_out_bits {
5476 	u8         status[0x8];
5477 	u8         reserved_at_8[0x18];
5478 
5479 	u8         syndrome[0x20];
5480 
5481 	u8         reserved_at_40[0x20];
5482 
5483 	u8         max_tx_speed[0x10];
5484 	u8         reserved_at_70[0x8];
5485 	u8         admin_state[0x4];
5486 	u8         state[0x4];
5487 };
5488 
5489 struct mlx5_ifc_array1024_auto_bits {
5490 	u8         array1024_auto[32][0x20];
5491 };
5492 
5493 struct mlx5_ifc_query_vuid_in_bits {
5494 	u8         opcode[0x10];
5495 	u8         uid[0x10];
5496 
5497 	u8         reserved_at_20[0x40];
5498 
5499 	u8         query_vfs_vuid[0x1];
5500 	u8         data_direct[0x1];
5501 	u8         reserved_at_62[0xe];
5502 	u8         vhca_id[0x10];
5503 };
5504 
5505 struct mlx5_ifc_query_vuid_out_bits {
5506 	u8        status[0x8];
5507 	u8        reserved_at_8[0x18];
5508 
5509 	u8        syndrome[0x20];
5510 
5511 	u8        reserved_at_40[0x1a0];
5512 
5513 	u8        reserved_at_1e0[0x10];
5514 	u8        num_of_entries[0x10];
5515 
5516 	struct mlx5_ifc_array1024_auto_bits vuid[];
5517 };
5518 
5519 enum {
5520 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5521 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5522 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5523 };
5524 
5525 struct mlx5_ifc_arm_monitor_counter_in_bits {
5526 	u8         opcode[0x10];
5527 	u8         uid[0x10];
5528 
5529 	u8         reserved_at_20[0x10];
5530 	u8         op_mod[0x10];
5531 
5532 	u8         reserved_at_40[0x20];
5533 
5534 	u8         reserved_at_60[0x20];
5535 };
5536 
5537 struct mlx5_ifc_arm_monitor_counter_out_bits {
5538 	u8         status[0x8];
5539 	u8         reserved_at_8[0x18];
5540 
5541 	u8         syndrome[0x20];
5542 
5543 	u8         reserved_at_40[0x40];
5544 };
5545 
5546 enum {
5547 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5548 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5549 };
5550 
5551 enum mlx5_monitor_counter_ppcnt {
5552 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5553 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5554 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5555 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5556 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5557 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5558 };
5559 
5560 enum {
5561 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5562 };
5563 
5564 struct mlx5_ifc_monitor_counter_output_bits {
5565 	u8         reserved_at_0[0x4];
5566 	u8         type[0x4];
5567 	u8         reserved_at_8[0x8];
5568 	u8         counter[0x10];
5569 
5570 	u8         counter_group_id[0x20];
5571 };
5572 
5573 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5574 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5575 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5576 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5577 
5578 struct mlx5_ifc_set_monitor_counter_in_bits {
5579 	u8         opcode[0x10];
5580 	u8         uid[0x10];
5581 
5582 	u8         reserved_at_20[0x10];
5583 	u8         op_mod[0x10];
5584 
5585 	u8         reserved_at_40[0x10];
5586 	u8         num_of_counters[0x10];
5587 
5588 	u8         reserved_at_60[0x20];
5589 
5590 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5591 };
5592 
5593 struct mlx5_ifc_set_monitor_counter_out_bits {
5594 	u8         status[0x8];
5595 	u8         reserved_at_8[0x18];
5596 
5597 	u8         syndrome[0x20];
5598 
5599 	u8         reserved_at_40[0x40];
5600 };
5601 
5602 struct mlx5_ifc_query_vport_state_in_bits {
5603 	u8         opcode[0x10];
5604 	u8         reserved_at_10[0x10];
5605 
5606 	u8         reserved_at_20[0x10];
5607 	u8         op_mod[0x10];
5608 
5609 	u8         other_vport[0x1];
5610 	u8         reserved_at_41[0xf];
5611 	u8         vport_number[0x10];
5612 
5613 	u8         reserved_at_60[0x20];
5614 };
5615 
5616 struct mlx5_ifc_query_vnic_env_out_bits {
5617 	u8         status[0x8];
5618 	u8         reserved_at_8[0x18];
5619 
5620 	u8         syndrome[0x20];
5621 
5622 	u8         reserved_at_40[0x40];
5623 
5624 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5625 };
5626 
5627 enum {
5628 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5629 };
5630 
5631 struct mlx5_ifc_query_vnic_env_in_bits {
5632 	u8         opcode[0x10];
5633 	u8         reserved_at_10[0x10];
5634 
5635 	u8         reserved_at_20[0x10];
5636 	u8         op_mod[0x10];
5637 
5638 	u8         other_vport[0x1];
5639 	u8         reserved_at_41[0xf];
5640 	u8         vport_number[0x10];
5641 
5642 	u8         reserved_at_60[0x20];
5643 };
5644 
5645 struct mlx5_ifc_query_vport_counter_out_bits {
5646 	u8         status[0x8];
5647 	u8         reserved_at_8[0x18];
5648 
5649 	u8         syndrome[0x20];
5650 
5651 	u8         reserved_at_40[0x40];
5652 
5653 	struct mlx5_ifc_traffic_counter_bits received_errors;
5654 
5655 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5656 
5657 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5658 
5659 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5660 
5661 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5662 
5663 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5664 
5665 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5666 
5667 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5668 
5669 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5670 
5671 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5672 
5673 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5674 
5675 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5676 
5677 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5678 
5679 	u8         reserved_at_700[0x980];
5680 };
5681 
5682 enum {
5683 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5684 };
5685 
5686 struct mlx5_ifc_query_vport_counter_in_bits {
5687 	u8         opcode[0x10];
5688 	u8         reserved_at_10[0x10];
5689 
5690 	u8         reserved_at_20[0x10];
5691 	u8         op_mod[0x10];
5692 
5693 	u8         other_vport[0x1];
5694 	u8         reserved_at_41[0xb];
5695 	u8	   port_num[0x4];
5696 	u8         vport_number[0x10];
5697 
5698 	u8         reserved_at_60[0x60];
5699 
5700 	u8         clear[0x1];
5701 	u8         reserved_at_c1[0x1f];
5702 
5703 	u8         reserved_at_e0[0x20];
5704 };
5705 
5706 struct mlx5_ifc_query_tis_out_bits {
5707 	u8         status[0x8];
5708 	u8         reserved_at_8[0x18];
5709 
5710 	u8         syndrome[0x20];
5711 
5712 	u8         reserved_at_40[0x40];
5713 
5714 	struct mlx5_ifc_tisc_bits tis_context;
5715 };
5716 
5717 struct mlx5_ifc_query_tis_in_bits {
5718 	u8         opcode[0x10];
5719 	u8         reserved_at_10[0x10];
5720 
5721 	u8         reserved_at_20[0x10];
5722 	u8         op_mod[0x10];
5723 
5724 	u8         reserved_at_40[0x8];
5725 	u8         tisn[0x18];
5726 
5727 	u8         reserved_at_60[0x20];
5728 };
5729 
5730 struct mlx5_ifc_query_tir_out_bits {
5731 	u8         status[0x8];
5732 	u8         reserved_at_8[0x18];
5733 
5734 	u8         syndrome[0x20];
5735 
5736 	u8         reserved_at_40[0xc0];
5737 
5738 	struct mlx5_ifc_tirc_bits tir_context;
5739 };
5740 
5741 struct mlx5_ifc_query_tir_in_bits {
5742 	u8         opcode[0x10];
5743 	u8         reserved_at_10[0x10];
5744 
5745 	u8         reserved_at_20[0x10];
5746 	u8         op_mod[0x10];
5747 
5748 	u8         reserved_at_40[0x8];
5749 	u8         tirn[0x18];
5750 
5751 	u8         reserved_at_60[0x20];
5752 };
5753 
5754 struct mlx5_ifc_query_srq_out_bits {
5755 	u8         status[0x8];
5756 	u8         reserved_at_8[0x18];
5757 
5758 	u8         syndrome[0x20];
5759 
5760 	u8         reserved_at_40[0x40];
5761 
5762 	struct mlx5_ifc_srqc_bits srq_context_entry;
5763 
5764 	u8         reserved_at_280[0x600];
5765 
5766 	u8         pas[][0x40];
5767 };
5768 
5769 struct mlx5_ifc_query_srq_in_bits {
5770 	u8         opcode[0x10];
5771 	u8         reserved_at_10[0x10];
5772 
5773 	u8         reserved_at_20[0x10];
5774 	u8         op_mod[0x10];
5775 
5776 	u8         reserved_at_40[0x8];
5777 	u8         srqn[0x18];
5778 
5779 	u8         reserved_at_60[0x20];
5780 };
5781 
5782 struct mlx5_ifc_query_sq_out_bits {
5783 	u8         status[0x8];
5784 	u8         reserved_at_8[0x18];
5785 
5786 	u8         syndrome[0x20];
5787 
5788 	u8         reserved_at_40[0xc0];
5789 
5790 	struct mlx5_ifc_sqc_bits sq_context;
5791 };
5792 
5793 struct mlx5_ifc_query_sq_in_bits {
5794 	u8         opcode[0x10];
5795 	u8         reserved_at_10[0x10];
5796 
5797 	u8         reserved_at_20[0x10];
5798 	u8         op_mod[0x10];
5799 
5800 	u8         reserved_at_40[0x8];
5801 	u8         sqn[0x18];
5802 
5803 	u8         reserved_at_60[0x20];
5804 };
5805 
5806 struct mlx5_ifc_query_special_contexts_out_bits {
5807 	u8         status[0x8];
5808 	u8         reserved_at_8[0x18];
5809 
5810 	u8         syndrome[0x20];
5811 
5812 	u8         dump_fill_mkey[0x20];
5813 
5814 	u8         resd_lkey[0x20];
5815 
5816 	u8         null_mkey[0x20];
5817 
5818 	u8	   terminate_scatter_list_mkey[0x20];
5819 
5820 	u8	   repeated_mkey[0x20];
5821 
5822 	u8         reserved_at_a0[0x20];
5823 };
5824 
5825 struct mlx5_ifc_query_special_contexts_in_bits {
5826 	u8         opcode[0x10];
5827 	u8         reserved_at_10[0x10];
5828 
5829 	u8         reserved_at_20[0x10];
5830 	u8         op_mod[0x10];
5831 
5832 	u8         reserved_at_40[0x40];
5833 };
5834 
5835 struct mlx5_ifc_query_scheduling_element_out_bits {
5836 	u8         opcode[0x10];
5837 	u8         reserved_at_10[0x10];
5838 
5839 	u8         reserved_at_20[0x10];
5840 	u8         op_mod[0x10];
5841 
5842 	u8         reserved_at_40[0xc0];
5843 
5844 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5845 
5846 	u8         reserved_at_300[0x100];
5847 };
5848 
5849 enum {
5850 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5851 	SCHEDULING_HIERARCHY_NIC = 0x3,
5852 };
5853 
5854 struct mlx5_ifc_query_scheduling_element_in_bits {
5855 	u8         opcode[0x10];
5856 	u8         reserved_at_10[0x10];
5857 
5858 	u8         reserved_at_20[0x10];
5859 	u8         op_mod[0x10];
5860 
5861 	u8         scheduling_hierarchy[0x8];
5862 	u8         reserved_at_48[0x18];
5863 
5864 	u8         scheduling_element_id[0x20];
5865 
5866 	u8         reserved_at_80[0x180];
5867 };
5868 
5869 struct mlx5_ifc_query_rqt_out_bits {
5870 	u8         status[0x8];
5871 	u8         reserved_at_8[0x18];
5872 
5873 	u8         syndrome[0x20];
5874 
5875 	u8         reserved_at_40[0xc0];
5876 
5877 	struct mlx5_ifc_rqtc_bits rqt_context;
5878 };
5879 
5880 struct mlx5_ifc_query_rqt_in_bits {
5881 	u8         opcode[0x10];
5882 	u8         reserved_at_10[0x10];
5883 
5884 	u8         reserved_at_20[0x10];
5885 	u8         op_mod[0x10];
5886 
5887 	u8         reserved_at_40[0x8];
5888 	u8         rqtn[0x18];
5889 
5890 	u8         reserved_at_60[0x20];
5891 };
5892 
5893 struct mlx5_ifc_query_rq_out_bits {
5894 	u8         status[0x8];
5895 	u8         reserved_at_8[0x18];
5896 
5897 	u8         syndrome[0x20];
5898 
5899 	u8         reserved_at_40[0xc0];
5900 
5901 	struct mlx5_ifc_rqc_bits rq_context;
5902 };
5903 
5904 struct mlx5_ifc_query_rq_in_bits {
5905 	u8         opcode[0x10];
5906 	u8         reserved_at_10[0x10];
5907 
5908 	u8         reserved_at_20[0x10];
5909 	u8         op_mod[0x10];
5910 
5911 	u8         reserved_at_40[0x8];
5912 	u8         rqn[0x18];
5913 
5914 	u8         reserved_at_60[0x20];
5915 };
5916 
5917 struct mlx5_ifc_query_roce_address_out_bits {
5918 	u8         status[0x8];
5919 	u8         reserved_at_8[0x18];
5920 
5921 	u8         syndrome[0x20];
5922 
5923 	u8         reserved_at_40[0x40];
5924 
5925 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5926 };
5927 
5928 struct mlx5_ifc_query_roce_address_in_bits {
5929 	u8         opcode[0x10];
5930 	u8         reserved_at_10[0x10];
5931 
5932 	u8         reserved_at_20[0x10];
5933 	u8         op_mod[0x10];
5934 
5935 	u8         roce_address_index[0x10];
5936 	u8         reserved_at_50[0xc];
5937 	u8	   vhca_port_num[0x4];
5938 
5939 	u8         reserved_at_60[0x20];
5940 };
5941 
5942 struct mlx5_ifc_query_rmp_out_bits {
5943 	u8         status[0x8];
5944 	u8         reserved_at_8[0x18];
5945 
5946 	u8         syndrome[0x20];
5947 
5948 	u8         reserved_at_40[0xc0];
5949 
5950 	struct mlx5_ifc_rmpc_bits rmp_context;
5951 };
5952 
5953 struct mlx5_ifc_query_rmp_in_bits {
5954 	u8         opcode[0x10];
5955 	u8         reserved_at_10[0x10];
5956 
5957 	u8         reserved_at_20[0x10];
5958 	u8         op_mod[0x10];
5959 
5960 	u8         reserved_at_40[0x8];
5961 	u8         rmpn[0x18];
5962 
5963 	u8         reserved_at_60[0x20];
5964 };
5965 
5966 struct mlx5_ifc_cqe_error_syndrome_bits {
5967 	u8         hw_error_syndrome[0x8];
5968 	u8         hw_syndrome_type[0x4];
5969 	u8         reserved_at_c[0x4];
5970 	u8         vendor_error_syndrome[0x8];
5971 	u8         syndrome[0x8];
5972 };
5973 
5974 struct mlx5_ifc_qp_context_extension_bits {
5975 	u8         reserved_at_0[0x60];
5976 
5977 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5978 
5979 	u8         reserved_at_80[0x580];
5980 };
5981 
5982 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5983 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5984 
5985 	u8         pas[0][0x40];
5986 };
5987 
5988 struct mlx5_ifc_qp_pas_list_in_bits {
5989 	struct mlx5_ifc_cmd_pas_bits pas[0];
5990 };
5991 
5992 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5993 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5994 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5995 };
5996 
5997 struct mlx5_ifc_query_qp_out_bits {
5998 	u8         status[0x8];
5999 	u8         reserved_at_8[0x18];
6000 
6001 	u8         syndrome[0x20];
6002 
6003 	u8         reserved_at_40[0x40];
6004 
6005 	u8         opt_param_mask[0x20];
6006 
6007 	u8         ece[0x20];
6008 
6009 	struct mlx5_ifc_qpc_bits qpc;
6010 
6011 	u8         reserved_at_800[0x80];
6012 
6013 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
6014 };
6015 
6016 struct mlx5_ifc_query_qp_in_bits {
6017 	u8         opcode[0x10];
6018 	u8         reserved_at_10[0x10];
6019 
6020 	u8         reserved_at_20[0x10];
6021 	u8         op_mod[0x10];
6022 
6023 	u8         qpc_ext[0x1];
6024 	u8         reserved_at_41[0x7];
6025 	u8         qpn[0x18];
6026 
6027 	u8         reserved_at_60[0x20];
6028 };
6029 
6030 struct mlx5_ifc_query_q_counter_out_bits {
6031 	u8         status[0x8];
6032 	u8         reserved_at_8[0x18];
6033 
6034 	u8         syndrome[0x20];
6035 
6036 	u8         reserved_at_40[0x40];
6037 
6038 	u8         rx_write_requests[0x20];
6039 
6040 	u8         reserved_at_a0[0x20];
6041 
6042 	u8         rx_read_requests[0x20];
6043 
6044 	u8         reserved_at_e0[0x20];
6045 
6046 	u8         rx_atomic_requests[0x20];
6047 
6048 	u8         reserved_at_120[0x20];
6049 
6050 	u8         rx_dct_connect[0x20];
6051 
6052 	u8         reserved_at_160[0x20];
6053 
6054 	u8         out_of_buffer[0x20];
6055 
6056 	u8         reserved_at_1a0[0x20];
6057 
6058 	u8         out_of_sequence[0x20];
6059 
6060 	u8         reserved_at_1e0[0x20];
6061 
6062 	u8         duplicate_request[0x20];
6063 
6064 	u8         reserved_at_220[0x20];
6065 
6066 	u8         rnr_nak_retry_err[0x20];
6067 
6068 	u8         reserved_at_260[0x20];
6069 
6070 	u8         packet_seq_err[0x20];
6071 
6072 	u8         reserved_at_2a0[0x20];
6073 
6074 	u8         implied_nak_seq_err[0x20];
6075 
6076 	u8         reserved_at_2e0[0x20];
6077 
6078 	u8         local_ack_timeout_err[0x20];
6079 
6080 	u8         reserved_at_320[0x60];
6081 
6082 	u8         req_rnr_retries_exceeded[0x20];
6083 
6084 	u8         reserved_at_3a0[0x20];
6085 
6086 	u8         resp_local_length_error[0x20];
6087 
6088 	u8         req_local_length_error[0x20];
6089 
6090 	u8         resp_local_qp_error[0x20];
6091 
6092 	u8         local_operation_error[0x20];
6093 
6094 	u8         resp_local_protection[0x20];
6095 
6096 	u8         req_local_protection[0x20];
6097 
6098 	u8         resp_cqe_error[0x20];
6099 
6100 	u8         req_cqe_error[0x20];
6101 
6102 	u8         req_mw_binding[0x20];
6103 
6104 	u8         req_bad_response[0x20];
6105 
6106 	u8         req_remote_invalid_request[0x20];
6107 
6108 	u8         resp_remote_invalid_request[0x20];
6109 
6110 	u8         req_remote_access_errors[0x20];
6111 
6112 	u8	   resp_remote_access_errors[0x20];
6113 
6114 	u8         req_remote_operation_errors[0x20];
6115 
6116 	u8         req_transport_retries_exceeded[0x20];
6117 
6118 	u8         cq_overflow[0x20];
6119 
6120 	u8         resp_cqe_flush_error[0x20];
6121 
6122 	u8         req_cqe_flush_error[0x20];
6123 
6124 	u8         reserved_at_620[0x20];
6125 
6126 	u8         roce_adp_retrans[0x20];
6127 
6128 	u8         roce_adp_retrans_to[0x20];
6129 
6130 	u8         roce_slow_restart[0x20];
6131 
6132 	u8         roce_slow_restart_cnps[0x20];
6133 
6134 	u8         roce_slow_restart_trans[0x20];
6135 
6136 	u8         reserved_at_6e0[0x120];
6137 };
6138 
6139 struct mlx5_ifc_query_q_counter_in_bits {
6140 	u8         opcode[0x10];
6141 	u8         reserved_at_10[0x10];
6142 
6143 	u8         reserved_at_20[0x10];
6144 	u8         op_mod[0x10];
6145 
6146 	u8         other_vport[0x1];
6147 	u8         reserved_at_41[0xf];
6148 	u8         vport_number[0x10];
6149 
6150 	u8         reserved_at_60[0x60];
6151 
6152 	u8         clear[0x1];
6153 	u8         aggregate[0x1];
6154 	u8         reserved_at_c2[0x1e];
6155 
6156 	u8         reserved_at_e0[0x18];
6157 	u8         counter_set_id[0x8];
6158 };
6159 
6160 struct mlx5_ifc_query_pages_out_bits {
6161 	u8         status[0x8];
6162 	u8         reserved_at_8[0x18];
6163 
6164 	u8         syndrome[0x20];
6165 
6166 	u8         embedded_cpu_function[0x1];
6167 	u8         reserved_at_41[0xf];
6168 	u8         function_id[0x10];
6169 
6170 	u8         num_pages[0x20];
6171 };
6172 
6173 enum {
6174 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
6175 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
6176 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
6177 };
6178 
6179 struct mlx5_ifc_query_pages_in_bits {
6180 	u8         opcode[0x10];
6181 	u8         reserved_at_10[0x10];
6182 
6183 	u8         reserved_at_20[0x10];
6184 	u8         op_mod[0x10];
6185 
6186 	u8         embedded_cpu_function[0x1];
6187 	u8         reserved_at_41[0xf];
6188 	u8         function_id[0x10];
6189 
6190 	u8         reserved_at_60[0x20];
6191 };
6192 
6193 struct mlx5_ifc_query_nic_vport_context_out_bits {
6194 	u8         status[0x8];
6195 	u8         reserved_at_8[0x18];
6196 
6197 	u8         syndrome[0x20];
6198 
6199 	u8         reserved_at_40[0x40];
6200 
6201 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6202 };
6203 
6204 struct mlx5_ifc_query_nic_vport_context_in_bits {
6205 	u8         opcode[0x10];
6206 	u8         reserved_at_10[0x10];
6207 
6208 	u8         reserved_at_20[0x10];
6209 	u8         op_mod[0x10];
6210 
6211 	u8         other_vport[0x1];
6212 	u8         reserved_at_41[0xf];
6213 	u8         vport_number[0x10];
6214 
6215 	u8         reserved_at_60[0x5];
6216 	u8         allowed_list_type[0x3];
6217 	u8         reserved_at_68[0x18];
6218 };
6219 
6220 struct mlx5_ifc_query_mkey_out_bits {
6221 	u8         status[0x8];
6222 	u8         reserved_at_8[0x18];
6223 
6224 	u8         syndrome[0x20];
6225 
6226 	u8         reserved_at_40[0x40];
6227 
6228 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6229 
6230 	u8         reserved_at_280[0x600];
6231 
6232 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6233 
6234 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6235 };
6236 
6237 struct mlx5_ifc_query_mkey_in_bits {
6238 	u8         opcode[0x10];
6239 	u8         reserved_at_10[0x10];
6240 
6241 	u8         reserved_at_20[0x10];
6242 	u8         op_mod[0x10];
6243 
6244 	u8         reserved_at_40[0x8];
6245 	u8         mkey_index[0x18];
6246 
6247 	u8         pg_access[0x1];
6248 	u8         reserved_at_61[0x1f];
6249 };
6250 
6251 struct mlx5_ifc_query_mad_demux_out_bits {
6252 	u8         status[0x8];
6253 	u8         reserved_at_8[0x18];
6254 
6255 	u8         syndrome[0x20];
6256 
6257 	u8         reserved_at_40[0x40];
6258 
6259 	u8         mad_dumux_parameters_block[0x20];
6260 };
6261 
6262 struct mlx5_ifc_query_mad_demux_in_bits {
6263 	u8         opcode[0x10];
6264 	u8         reserved_at_10[0x10];
6265 
6266 	u8         reserved_at_20[0x10];
6267 	u8         op_mod[0x10];
6268 
6269 	u8         reserved_at_40[0x40];
6270 };
6271 
6272 struct mlx5_ifc_query_l2_table_entry_out_bits {
6273 	u8         status[0x8];
6274 	u8         reserved_at_8[0x18];
6275 
6276 	u8         syndrome[0x20];
6277 
6278 	u8         reserved_at_40[0xa0];
6279 
6280 	u8         reserved_at_e0[0x11];
6281 	u8         silent_mode[0x1];
6282 	u8         reserved_at_f2[0x1];
6283 	u8         vlan_valid[0x1];
6284 	u8         vlan[0xc];
6285 
6286 	struct mlx5_ifc_mac_address_layout_bits mac_address;
6287 
6288 	u8         reserved_at_140[0xc0];
6289 };
6290 
6291 struct mlx5_ifc_query_l2_table_entry_in_bits {
6292 	u8         opcode[0x10];
6293 	u8         reserved_at_10[0x10];
6294 
6295 	u8         reserved_at_20[0x10];
6296 	u8         op_mod[0x10];
6297 
6298 	u8         reserved_at_40[0x40];
6299 
6300 	u8         silent_mode_query[0x1];
6301 	u8         reserved_at_81[0x1f];
6302 
6303 	u8         reserved_at_a0[0x8];
6304 	u8         table_index[0x18];
6305 
6306 	u8         reserved_at_c0[0x140];
6307 };
6308 
6309 struct mlx5_ifc_query_issi_out_bits {
6310 	u8         status[0x8];
6311 	u8         reserved_at_8[0x18];
6312 
6313 	u8         syndrome[0x20];
6314 
6315 	u8         reserved_at_40[0x10];
6316 	u8         current_issi[0x10];
6317 
6318 	u8         reserved_at_60[0xa0];
6319 
6320 	u8         reserved_at_100[76][0x8];
6321 	u8         supported_issi_dw0[0x20];
6322 };
6323 
6324 struct mlx5_ifc_query_issi_in_bits {
6325 	u8         opcode[0x10];
6326 	u8         reserved_at_10[0x10];
6327 
6328 	u8         reserved_at_20[0x10];
6329 	u8         op_mod[0x10];
6330 
6331 	u8         reserved_at_40[0x40];
6332 };
6333 
6334 struct mlx5_ifc_set_driver_version_out_bits {
6335 	u8         status[0x8];
6336 	u8         reserved_0[0x18];
6337 
6338 	u8         syndrome[0x20];
6339 	u8         reserved_1[0x40];
6340 };
6341 
6342 struct mlx5_ifc_set_driver_version_in_bits {
6343 	u8         opcode[0x10];
6344 	u8         reserved_0[0x10];
6345 
6346 	u8         reserved_1[0x10];
6347 	u8         op_mod[0x10];
6348 
6349 	u8         reserved_2[0x40];
6350 	u8         driver_version[64][0x8];
6351 };
6352 
6353 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6354 	u8         status[0x8];
6355 	u8         reserved_at_8[0x18];
6356 
6357 	u8         syndrome[0x20];
6358 
6359 	u8         reserved_at_40[0x40];
6360 
6361 	struct mlx5_ifc_pkey_bits pkey[];
6362 };
6363 
6364 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6365 	u8         opcode[0x10];
6366 	u8         reserved_at_10[0x10];
6367 
6368 	u8         reserved_at_20[0x10];
6369 	u8         op_mod[0x10];
6370 
6371 	u8         other_vport[0x1];
6372 	u8         reserved_at_41[0xb];
6373 	u8         port_num[0x4];
6374 	u8         vport_number[0x10];
6375 
6376 	u8         reserved_at_60[0x10];
6377 	u8         pkey_index[0x10];
6378 };
6379 
6380 enum {
6381 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6382 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6383 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6384 };
6385 
6386 struct mlx5_ifc_query_hca_vport_gid_out_bits {
6387 	u8         status[0x8];
6388 	u8         reserved_at_8[0x18];
6389 
6390 	u8         syndrome[0x20];
6391 
6392 	u8         reserved_at_40[0x20];
6393 
6394 	u8         gids_num[0x10];
6395 	u8         reserved_at_70[0x10];
6396 
6397 	struct mlx5_ifc_array128_auto_bits gid[];
6398 };
6399 
6400 struct mlx5_ifc_query_hca_vport_gid_in_bits {
6401 	u8         opcode[0x10];
6402 	u8         reserved_at_10[0x10];
6403 
6404 	u8         reserved_at_20[0x10];
6405 	u8         op_mod[0x10];
6406 
6407 	u8         other_vport[0x1];
6408 	u8         reserved_at_41[0xb];
6409 	u8         port_num[0x4];
6410 	u8         vport_number[0x10];
6411 
6412 	u8         reserved_at_60[0x10];
6413 	u8         gid_index[0x10];
6414 };
6415 
6416 struct mlx5_ifc_query_hca_vport_context_out_bits {
6417 	u8         status[0x8];
6418 	u8         reserved_at_8[0x18];
6419 
6420 	u8         syndrome[0x20];
6421 
6422 	u8         reserved_at_40[0x40];
6423 
6424 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6425 };
6426 
6427 struct mlx5_ifc_query_hca_vport_context_in_bits {
6428 	u8         opcode[0x10];
6429 	u8         reserved_at_10[0x10];
6430 
6431 	u8         reserved_at_20[0x10];
6432 	u8         op_mod[0x10];
6433 
6434 	u8         other_vport[0x1];
6435 	u8         reserved_at_41[0xb];
6436 	u8         port_num[0x4];
6437 	u8         vport_number[0x10];
6438 
6439 	u8         reserved_at_60[0x20];
6440 };
6441 
6442 struct mlx5_ifc_query_hca_cap_out_bits {
6443 	u8         status[0x8];
6444 	u8         reserved_at_8[0x18];
6445 
6446 	u8         syndrome[0x20];
6447 
6448 	u8         reserved_at_40[0x40];
6449 
6450 	union mlx5_ifc_hca_cap_union_bits capability;
6451 };
6452 
6453 struct mlx5_ifc_query_hca_cap_in_bits {
6454 	u8         opcode[0x10];
6455 	u8         reserved_at_10[0x10];
6456 
6457 	u8         reserved_at_20[0x10];
6458 	u8         op_mod[0x10];
6459 
6460 	u8         other_function[0x1];
6461 	u8         ec_vf_function[0x1];
6462 	u8         reserved_at_42[0x1];
6463 	u8         function_id_type[0x1];
6464 	u8         reserved_at_44[0xc];
6465 	u8         function_id[0x10];
6466 
6467 	u8         reserved_at_60[0x20];
6468 };
6469 
6470 struct mlx5_ifc_other_hca_cap_bits {
6471 	u8         roce[0x1];
6472 	u8         reserved_at_1[0x27f];
6473 };
6474 
6475 struct mlx5_ifc_query_other_hca_cap_out_bits {
6476 	u8         status[0x8];
6477 	u8         reserved_at_8[0x18];
6478 
6479 	u8         syndrome[0x20];
6480 
6481 	u8         reserved_at_40[0x40];
6482 
6483 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6484 };
6485 
6486 struct mlx5_ifc_query_other_hca_cap_in_bits {
6487 	u8         opcode[0x10];
6488 	u8         reserved_at_10[0x10];
6489 
6490 	u8         reserved_at_20[0x10];
6491 	u8         op_mod[0x10];
6492 
6493 	u8         reserved_at_40[0x10];
6494 	u8         function_id[0x10];
6495 
6496 	u8         reserved_at_60[0x20];
6497 };
6498 
6499 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6500 	u8         status[0x8];
6501 	u8         reserved_at_8[0x18];
6502 
6503 	u8         syndrome[0x20];
6504 
6505 	u8         reserved_at_40[0x40];
6506 };
6507 
6508 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6509 	u8         opcode[0x10];
6510 	u8         reserved_at_10[0x10];
6511 
6512 	u8         reserved_at_20[0x10];
6513 	u8         op_mod[0x10];
6514 
6515 	u8         reserved_at_40[0x10];
6516 	u8         function_id[0x10];
6517 	u8         field_select[0x20];
6518 
6519 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6520 };
6521 
6522 struct mlx5_ifc_sw_owner_icm_root_params_bits {
6523 	u8         sw_owner_icm_root_1[0x40];
6524 
6525 	u8         sw_owner_icm_root_0[0x40];
6526 };
6527 
6528 struct mlx5_ifc_rtc_params_bits {
6529 	u8         rtc_id_0[0x20];
6530 
6531 	u8         rtc_id_1[0x20];
6532 
6533 	u8         reserved_at_40[0x40];
6534 };
6535 
6536 struct mlx5_ifc_flow_table_context_bits {
6537 	u8         reformat_en[0x1];
6538 	u8         decap_en[0x1];
6539 	u8         sw_owner[0x1];
6540 	u8         termination_table[0x1];
6541 	u8         table_miss_action[0x4];
6542 	u8         level[0x8];
6543 	u8         rtc_valid[0x1];
6544 	u8         reserved_at_11[0x7];
6545 	u8         log_size[0x8];
6546 
6547 	u8         reserved_at_20[0x8];
6548 	u8         table_miss_id[0x18];
6549 
6550 	u8         reserved_at_40[0x8];
6551 	u8         lag_master_next_table_id[0x18];
6552 
6553 	u8         reserved_at_60[0x60];
6554 
6555 	union {
6556 		struct mlx5_ifc_sw_owner_icm_root_params_bits sws;
6557 		struct mlx5_ifc_rtc_params_bits hws;
6558 	};
6559 };
6560 
6561 struct mlx5_ifc_query_flow_table_out_bits {
6562 	u8         status[0x8];
6563 	u8         reserved_at_8[0x18];
6564 
6565 	u8         syndrome[0x20];
6566 
6567 	u8         reserved_at_40[0x80];
6568 
6569 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6570 };
6571 
6572 struct mlx5_ifc_query_flow_table_in_bits {
6573 	u8         opcode[0x10];
6574 	u8         reserved_at_10[0x10];
6575 
6576 	u8         reserved_at_20[0x10];
6577 	u8         op_mod[0x10];
6578 
6579 	u8         reserved_at_40[0x40];
6580 
6581 	u8         table_type[0x8];
6582 	u8         reserved_at_88[0x18];
6583 
6584 	u8         reserved_at_a0[0x8];
6585 	u8         table_id[0x18];
6586 
6587 	u8         reserved_at_c0[0x140];
6588 };
6589 
6590 struct mlx5_ifc_query_fte_out_bits {
6591 	u8         status[0x8];
6592 	u8         reserved_at_8[0x18];
6593 
6594 	u8         syndrome[0x20];
6595 
6596 	u8         reserved_at_40[0x1c0];
6597 
6598 	struct mlx5_ifc_flow_context_bits flow_context;
6599 };
6600 
6601 struct mlx5_ifc_query_fte_in_bits {
6602 	u8         opcode[0x10];
6603 	u8         reserved_at_10[0x10];
6604 
6605 	u8         reserved_at_20[0x10];
6606 	u8         op_mod[0x10];
6607 
6608 	u8         reserved_at_40[0x40];
6609 
6610 	u8         table_type[0x8];
6611 	u8         reserved_at_88[0x18];
6612 
6613 	u8         reserved_at_a0[0x8];
6614 	u8         table_id[0x18];
6615 
6616 	u8         reserved_at_c0[0x40];
6617 
6618 	u8         flow_index[0x20];
6619 
6620 	u8         reserved_at_120[0xe0];
6621 };
6622 
6623 struct mlx5_ifc_match_definer_format_0_bits {
6624 	u8         reserved_at_0[0x100];
6625 
6626 	u8         metadata_reg_c_0[0x20];
6627 
6628 	u8         metadata_reg_c_1[0x20];
6629 
6630 	u8         outer_dmac_47_16[0x20];
6631 
6632 	u8         outer_dmac_15_0[0x10];
6633 	u8         outer_ethertype[0x10];
6634 
6635 	u8         reserved_at_180[0x1];
6636 	u8         sx_sniffer[0x1];
6637 	u8         functional_lb[0x1];
6638 	u8         outer_ip_frag[0x1];
6639 	u8         outer_qp_type[0x2];
6640 	u8         outer_encap_type[0x2];
6641 	u8         port_number[0x2];
6642 	u8         outer_l3_type[0x2];
6643 	u8         outer_l4_type[0x2];
6644 	u8         outer_first_vlan_type[0x2];
6645 	u8         outer_first_vlan_prio[0x3];
6646 	u8         outer_first_vlan_cfi[0x1];
6647 	u8         outer_first_vlan_vid[0xc];
6648 
6649 	u8         outer_l4_type_ext[0x4];
6650 	u8         reserved_at_1a4[0x2];
6651 	u8         outer_ipsec_layer[0x2];
6652 	u8         outer_l2_type[0x2];
6653 	u8         force_lb[0x1];
6654 	u8         outer_l2_ok[0x1];
6655 	u8         outer_l3_ok[0x1];
6656 	u8         outer_l4_ok[0x1];
6657 	u8         outer_second_vlan_type[0x2];
6658 	u8         outer_second_vlan_prio[0x3];
6659 	u8         outer_second_vlan_cfi[0x1];
6660 	u8         outer_second_vlan_vid[0xc];
6661 
6662 	u8         outer_smac_47_16[0x20];
6663 
6664 	u8         outer_smac_15_0[0x10];
6665 	u8         inner_ipv4_checksum_ok[0x1];
6666 	u8         inner_l4_checksum_ok[0x1];
6667 	u8         outer_ipv4_checksum_ok[0x1];
6668 	u8         outer_l4_checksum_ok[0x1];
6669 	u8         inner_l3_ok[0x1];
6670 	u8         inner_l4_ok[0x1];
6671 	u8         outer_l3_ok_duplicate[0x1];
6672 	u8         outer_l4_ok_duplicate[0x1];
6673 	u8         outer_tcp_cwr[0x1];
6674 	u8         outer_tcp_ece[0x1];
6675 	u8         outer_tcp_urg[0x1];
6676 	u8         outer_tcp_ack[0x1];
6677 	u8         outer_tcp_psh[0x1];
6678 	u8         outer_tcp_rst[0x1];
6679 	u8         outer_tcp_syn[0x1];
6680 	u8         outer_tcp_fin[0x1];
6681 };
6682 
6683 struct mlx5_ifc_match_definer_format_22_bits {
6684 	u8         reserved_at_0[0x100];
6685 
6686 	u8         outer_ip_src_addr[0x20];
6687 
6688 	u8         outer_ip_dest_addr[0x20];
6689 
6690 	u8         outer_l4_sport[0x10];
6691 	u8         outer_l4_dport[0x10];
6692 
6693 	u8         reserved_at_160[0x1];
6694 	u8         sx_sniffer[0x1];
6695 	u8         functional_lb[0x1];
6696 	u8         outer_ip_frag[0x1];
6697 	u8         outer_qp_type[0x2];
6698 	u8         outer_encap_type[0x2];
6699 	u8         port_number[0x2];
6700 	u8         outer_l3_type[0x2];
6701 	u8         outer_l4_type[0x2];
6702 	u8         outer_first_vlan_type[0x2];
6703 	u8         outer_first_vlan_prio[0x3];
6704 	u8         outer_first_vlan_cfi[0x1];
6705 	u8         outer_first_vlan_vid[0xc];
6706 
6707 	u8         metadata_reg_c_0[0x20];
6708 
6709 	u8         outer_dmac_47_16[0x20];
6710 
6711 	u8         outer_smac_47_16[0x20];
6712 
6713 	u8         outer_smac_15_0[0x10];
6714 	u8         outer_dmac_15_0[0x10];
6715 };
6716 
6717 struct mlx5_ifc_match_definer_format_23_bits {
6718 	u8         reserved_at_0[0x100];
6719 
6720 	u8         inner_ip_src_addr[0x20];
6721 
6722 	u8         inner_ip_dest_addr[0x20];
6723 
6724 	u8         inner_l4_sport[0x10];
6725 	u8         inner_l4_dport[0x10];
6726 
6727 	u8         reserved_at_160[0x1];
6728 	u8         sx_sniffer[0x1];
6729 	u8         functional_lb[0x1];
6730 	u8         inner_ip_frag[0x1];
6731 	u8         inner_qp_type[0x2];
6732 	u8         inner_encap_type[0x2];
6733 	u8         port_number[0x2];
6734 	u8         inner_l3_type[0x2];
6735 	u8         inner_l4_type[0x2];
6736 	u8         inner_first_vlan_type[0x2];
6737 	u8         inner_first_vlan_prio[0x3];
6738 	u8         inner_first_vlan_cfi[0x1];
6739 	u8         inner_first_vlan_vid[0xc];
6740 
6741 	u8         tunnel_header_0[0x20];
6742 
6743 	u8         inner_dmac_47_16[0x20];
6744 
6745 	u8         inner_smac_47_16[0x20];
6746 
6747 	u8         inner_smac_15_0[0x10];
6748 	u8         inner_dmac_15_0[0x10];
6749 };
6750 
6751 struct mlx5_ifc_match_definer_format_29_bits {
6752 	u8         reserved_at_0[0xc0];
6753 
6754 	u8         outer_ip_dest_addr[0x80];
6755 
6756 	u8         outer_ip_src_addr[0x80];
6757 
6758 	u8         outer_l4_sport[0x10];
6759 	u8         outer_l4_dport[0x10];
6760 
6761 	u8         reserved_at_1e0[0x20];
6762 };
6763 
6764 struct mlx5_ifc_match_definer_format_30_bits {
6765 	u8         reserved_at_0[0xa0];
6766 
6767 	u8         outer_ip_dest_addr[0x80];
6768 
6769 	u8         outer_ip_src_addr[0x80];
6770 
6771 	u8         outer_dmac_47_16[0x20];
6772 
6773 	u8         outer_smac_47_16[0x20];
6774 
6775 	u8         outer_smac_15_0[0x10];
6776 	u8         outer_dmac_15_0[0x10];
6777 };
6778 
6779 struct mlx5_ifc_match_definer_format_31_bits {
6780 	u8         reserved_at_0[0xc0];
6781 
6782 	u8         inner_ip_dest_addr[0x80];
6783 
6784 	u8         inner_ip_src_addr[0x80];
6785 
6786 	u8         inner_l4_sport[0x10];
6787 	u8         inner_l4_dport[0x10];
6788 
6789 	u8         reserved_at_1e0[0x20];
6790 };
6791 
6792 struct mlx5_ifc_match_definer_format_32_bits {
6793 	u8         reserved_at_0[0xa0];
6794 
6795 	u8         inner_ip_dest_addr[0x80];
6796 
6797 	u8         inner_ip_src_addr[0x80];
6798 
6799 	u8         inner_dmac_47_16[0x20];
6800 
6801 	u8         inner_smac_47_16[0x20];
6802 
6803 	u8         inner_smac_15_0[0x10];
6804 	u8         inner_dmac_15_0[0x10];
6805 };
6806 
6807 enum {
6808 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6809 };
6810 
6811 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6812 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6813 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6814 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6815 
6816 struct mlx5_ifc_match_definer_match_mask_bits {
6817 	u8         reserved_at_1c0[5][0x20];
6818 	u8         match_dw_8[0x20];
6819 	u8         match_dw_7[0x20];
6820 	u8         match_dw_6[0x20];
6821 	u8         match_dw_5[0x20];
6822 	u8         match_dw_4[0x20];
6823 	u8         match_dw_3[0x20];
6824 	u8         match_dw_2[0x20];
6825 	u8         match_dw_1[0x20];
6826 	u8         match_dw_0[0x20];
6827 
6828 	u8         match_byte_7[0x8];
6829 	u8         match_byte_6[0x8];
6830 	u8         match_byte_5[0x8];
6831 	u8         match_byte_4[0x8];
6832 
6833 	u8         match_byte_3[0x8];
6834 	u8         match_byte_2[0x8];
6835 	u8         match_byte_1[0x8];
6836 	u8         match_byte_0[0x8];
6837 };
6838 
6839 struct mlx5_ifc_match_definer_bits {
6840 	u8         modify_field_select[0x40];
6841 
6842 	u8         reserved_at_40[0x40];
6843 
6844 	u8         reserved_at_80[0x10];
6845 	u8         format_id[0x10];
6846 
6847 	u8         reserved_at_a0[0x60];
6848 
6849 	u8         format_select_dw3[0x8];
6850 	u8         format_select_dw2[0x8];
6851 	u8         format_select_dw1[0x8];
6852 	u8         format_select_dw0[0x8];
6853 
6854 	u8         format_select_dw7[0x8];
6855 	u8         format_select_dw6[0x8];
6856 	u8         format_select_dw5[0x8];
6857 	u8         format_select_dw4[0x8];
6858 
6859 	u8         reserved_at_100[0x18];
6860 	u8         format_select_dw8[0x8];
6861 
6862 	u8         reserved_at_120[0x20];
6863 
6864 	u8         format_select_byte3[0x8];
6865 	u8         format_select_byte2[0x8];
6866 	u8         format_select_byte1[0x8];
6867 	u8         format_select_byte0[0x8];
6868 
6869 	u8         format_select_byte7[0x8];
6870 	u8         format_select_byte6[0x8];
6871 	u8         format_select_byte5[0x8];
6872 	u8         format_select_byte4[0x8];
6873 
6874 	u8         reserved_at_180[0x40];
6875 
6876 	union {
6877 		struct {
6878 			u8         match_mask[16][0x20];
6879 		};
6880 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6881 	};
6882 };
6883 
6884 struct mlx5_ifc_general_obj_create_param_bits {
6885 	u8         alias_object[0x1];
6886 	u8         reserved_at_1[0x2];
6887 	u8         log_obj_range[0x5];
6888 	u8         reserved_at_8[0x18];
6889 };
6890 
6891 struct mlx5_ifc_general_obj_query_param_bits {
6892 	u8         alias_object[0x1];
6893 	u8         obj_offset[0x1f];
6894 };
6895 
6896 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6897 	u8         opcode[0x10];
6898 	u8         uid[0x10];
6899 
6900 	u8         vhca_tunnel_id[0x10];
6901 	u8         obj_type[0x10];
6902 
6903 	u8         obj_id[0x20];
6904 
6905 	union {
6906 		struct mlx5_ifc_general_obj_create_param_bits create;
6907 		struct mlx5_ifc_general_obj_query_param_bits query;
6908 	} op_param;
6909 };
6910 
6911 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6912 	u8         status[0x8];
6913 	u8         reserved_at_8[0x18];
6914 
6915 	u8         syndrome[0x20];
6916 
6917 	u8         obj_id[0x20];
6918 
6919 	u8         reserved_at_60[0x20];
6920 };
6921 
6922 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6923 	u8 opcode[0x10];
6924 	u8 uid[0x10];
6925 	u8 reserved_at_20[0x10];
6926 	u8 op_mod[0x10];
6927 	u8 reserved_at_40[0x50];
6928 	u8 object_type_to_be_accessed[0x10];
6929 	u8 object_id_to_be_accessed[0x20];
6930 	u8 reserved_at_c0[0x40];
6931 	union {
6932 		u8 access_key_raw[0x100];
6933 		u8 access_key[8][0x20];
6934 	};
6935 };
6936 
6937 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6938 	u8 status[0x8];
6939 	u8 reserved_at_8[0x18];
6940 	u8 syndrome[0x20];
6941 	u8 reserved_at_40[0x40];
6942 };
6943 
6944 struct mlx5_ifc_modify_header_arg_bits {
6945 	u8         reserved_at_0[0x80];
6946 
6947 	u8         reserved_at_80[0x8];
6948 	u8         access_pd[0x18];
6949 };
6950 
6951 struct mlx5_ifc_create_modify_header_arg_in_bits {
6952 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6953 	struct mlx5_ifc_modify_header_arg_bits arg;
6954 };
6955 
6956 struct mlx5_ifc_create_match_definer_in_bits {
6957 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6958 
6959 	struct mlx5_ifc_match_definer_bits obj_context;
6960 };
6961 
6962 struct mlx5_ifc_create_match_definer_out_bits {
6963 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6964 };
6965 
6966 struct mlx5_ifc_alias_context_bits {
6967 	u8 vhca_id_to_be_accessed[0x10];
6968 	u8 reserved_at_10[0xb];
6969 	u8 vhca_id_type[0x1];
6970 	u8 reserved_at_1c[0x1];
6971 	u8 status[0x3];
6972 	u8 object_id_to_be_accessed[0x20];
6973 	u8 reserved_at_40[0x40];
6974 	union {
6975 		u8 access_key_raw[0x100];
6976 		u8 access_key[8][0x20];
6977 	};
6978 	u8 metadata[0x80];
6979 };
6980 
6981 struct mlx5_ifc_create_alias_obj_in_bits {
6982 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6983 	struct mlx5_ifc_alias_context_bits alias_ctx;
6984 };
6985 
6986 enum {
6987 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6988 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6989 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6990 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6991 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6992 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6993 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6994 };
6995 
6996 struct mlx5_ifc_query_flow_group_out_bits {
6997 	u8         status[0x8];
6998 	u8         reserved_at_8[0x18];
6999 
7000 	u8         syndrome[0x20];
7001 
7002 	u8         reserved_at_40[0xa0];
7003 
7004 	u8         start_flow_index[0x20];
7005 
7006 	u8         reserved_at_100[0x20];
7007 
7008 	u8         end_flow_index[0x20];
7009 
7010 	u8         reserved_at_140[0xa0];
7011 
7012 	u8         reserved_at_1e0[0x18];
7013 	u8         match_criteria_enable[0x8];
7014 
7015 	struct mlx5_ifc_fte_match_param_bits match_criteria;
7016 
7017 	u8         reserved_at_1200[0xe00];
7018 };
7019 
7020 struct mlx5_ifc_query_flow_group_in_bits {
7021 	u8         opcode[0x10];
7022 	u8         reserved_at_10[0x10];
7023 
7024 	u8         reserved_at_20[0x10];
7025 	u8         op_mod[0x10];
7026 
7027 	u8         reserved_at_40[0x40];
7028 
7029 	u8         table_type[0x8];
7030 	u8         reserved_at_88[0x18];
7031 
7032 	u8         reserved_at_a0[0x8];
7033 	u8         table_id[0x18];
7034 
7035 	u8         group_id[0x20];
7036 
7037 	u8         reserved_at_e0[0x120];
7038 };
7039 
7040 struct mlx5_ifc_query_flow_counter_out_bits {
7041 	u8         status[0x8];
7042 	u8         reserved_at_8[0x18];
7043 
7044 	u8         syndrome[0x20];
7045 
7046 	u8         reserved_at_40[0x40];
7047 
7048 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
7049 };
7050 
7051 struct mlx5_ifc_query_flow_counter_in_bits {
7052 	u8         opcode[0x10];
7053 	u8         reserved_at_10[0x10];
7054 
7055 	u8         reserved_at_20[0x10];
7056 	u8         op_mod[0x10];
7057 
7058 	u8         reserved_at_40[0x80];
7059 
7060 	u8         clear[0x1];
7061 	u8         reserved_at_c1[0xf];
7062 	u8         num_of_counters[0x10];
7063 
7064 	u8         flow_counter_id[0x20];
7065 };
7066 
7067 struct mlx5_ifc_query_esw_vport_context_out_bits {
7068 	u8         status[0x8];
7069 	u8         reserved_at_8[0x18];
7070 
7071 	u8         syndrome[0x20];
7072 
7073 	u8         reserved_at_40[0x40];
7074 
7075 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7076 };
7077 
7078 struct mlx5_ifc_query_esw_vport_context_in_bits {
7079 	u8         opcode[0x10];
7080 	u8         reserved_at_10[0x10];
7081 
7082 	u8         reserved_at_20[0x10];
7083 	u8         op_mod[0x10];
7084 
7085 	u8         other_vport[0x1];
7086 	u8         reserved_at_41[0xf];
7087 	u8         vport_number[0x10];
7088 
7089 	u8         reserved_at_60[0x20];
7090 };
7091 
7092 struct mlx5_ifc_destroy_esw_vport_out_bits {
7093 	u8         status[0x8];
7094 	u8         reserved_at_8[0x18];
7095 
7096 	u8         syndrome[0x20];
7097 
7098 	u8         reserved_at_40[0x20];
7099 };
7100 
7101 struct mlx5_ifc_destroy_esw_vport_in_bits {
7102 	u8         opcode[0x10];
7103 	u8         uid[0x10];
7104 
7105 	u8         reserved_at_20[0x10];
7106 	u8         op_mod[0x10];
7107 
7108 	u8         reserved_at_40[0x10];
7109 	u8         vport_num[0x10];
7110 
7111 	u8         reserved_at_60[0x20];
7112 };
7113 
7114 struct mlx5_ifc_modify_esw_vport_context_out_bits {
7115 	u8         status[0x8];
7116 	u8         reserved_at_8[0x18];
7117 
7118 	u8         syndrome[0x20];
7119 
7120 	u8         reserved_at_40[0x40];
7121 };
7122 
7123 struct mlx5_ifc_esw_vport_context_fields_select_bits {
7124 	u8         reserved_at_0[0x1b];
7125 	u8         fdb_to_vport_reg_c_id[0x1];
7126 	u8         vport_cvlan_insert[0x1];
7127 	u8         vport_svlan_insert[0x1];
7128 	u8         vport_cvlan_strip[0x1];
7129 	u8         vport_svlan_strip[0x1];
7130 };
7131 
7132 struct mlx5_ifc_modify_esw_vport_context_in_bits {
7133 	u8         opcode[0x10];
7134 	u8         reserved_at_10[0x10];
7135 
7136 	u8         reserved_at_20[0x10];
7137 	u8         op_mod[0x10];
7138 
7139 	u8         other_vport[0x1];
7140 	u8         reserved_at_41[0xf];
7141 	u8         vport_number[0x10];
7142 
7143 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
7144 
7145 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7146 };
7147 
7148 struct mlx5_ifc_query_eq_out_bits {
7149 	u8         status[0x8];
7150 	u8         reserved_at_8[0x18];
7151 
7152 	u8         syndrome[0x20];
7153 
7154 	u8         reserved_at_40[0x40];
7155 
7156 	struct mlx5_ifc_eqc_bits eq_context_entry;
7157 
7158 	u8         reserved_at_280[0x40];
7159 
7160 	u8         event_bitmask[0x40];
7161 
7162 	u8         reserved_at_300[0x580];
7163 
7164 	u8         pas[][0x40];
7165 };
7166 
7167 struct mlx5_ifc_query_eq_in_bits {
7168 	u8         opcode[0x10];
7169 	u8         reserved_at_10[0x10];
7170 
7171 	u8         reserved_at_20[0x10];
7172 	u8         op_mod[0x10];
7173 
7174 	u8         reserved_at_40[0x18];
7175 	u8         eq_number[0x8];
7176 
7177 	u8         reserved_at_60[0x20];
7178 };
7179 
7180 struct mlx5_ifc_packet_reformat_context_in_bits {
7181 	u8         reformat_type[0x8];
7182 	u8         reserved_at_8[0x4];
7183 	u8         reformat_param_0[0x4];
7184 	u8         reserved_at_10[0x6];
7185 	u8         reformat_data_size[0xa];
7186 
7187 	u8         reformat_param_1[0x8];
7188 	u8         reserved_at_28[0x8];
7189 	u8         reformat_data[2][0x8];
7190 
7191 	u8         more_reformat_data[][0x8];
7192 };
7193 
7194 struct mlx5_ifc_query_packet_reformat_context_out_bits {
7195 	u8         status[0x8];
7196 	u8         reserved_at_8[0x18];
7197 
7198 	u8         syndrome[0x20];
7199 
7200 	u8         reserved_at_40[0xa0];
7201 
7202 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7203 };
7204 
7205 struct mlx5_ifc_query_packet_reformat_context_in_bits {
7206 	u8         opcode[0x10];
7207 	u8         reserved_at_10[0x10];
7208 
7209 	u8         reserved_at_20[0x10];
7210 	u8         op_mod[0x10];
7211 
7212 	u8         packet_reformat_id[0x20];
7213 
7214 	u8         reserved_at_60[0xa0];
7215 };
7216 
7217 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7218 	u8         status[0x8];
7219 	u8         reserved_at_8[0x18];
7220 
7221 	u8         syndrome[0x20];
7222 
7223 	u8         packet_reformat_id[0x20];
7224 
7225 	u8         reserved_at_60[0x20];
7226 };
7227 
7228 enum {
7229 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7230 	MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2,
7231 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7232 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7233 };
7234 
7235 enum mlx5_reformat_ctx_type {
7236 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7237 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7238 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7239 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7240 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7241 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7242 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7243 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7244 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7245 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7246 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7247 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7248 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7249 	MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd,
7250 	MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe,
7251 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7252 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7253 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7254 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7255 };
7256 
7257 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7258 	u8         opcode[0x10];
7259 	u8         reserved_at_10[0x10];
7260 
7261 	u8         reserved_at_20[0x10];
7262 	u8         op_mod[0x10];
7263 
7264 	u8         reserved_at_40[0xa0];
7265 
7266 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7267 };
7268 
7269 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7270 	u8         status[0x8];
7271 	u8         reserved_at_8[0x18];
7272 
7273 	u8         syndrome[0x20];
7274 
7275 	u8         reserved_at_40[0x40];
7276 };
7277 
7278 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7279 	u8         opcode[0x10];
7280 	u8         reserved_at_10[0x10];
7281 
7282 	u8         reserved_20[0x10];
7283 	u8         op_mod[0x10];
7284 
7285 	u8         packet_reformat_id[0x20];
7286 
7287 	u8         reserved_60[0x20];
7288 };
7289 
7290 struct mlx5_ifc_set_action_in_bits {
7291 	u8         action_type[0x4];
7292 	u8         field[0xc];
7293 	u8         reserved_at_10[0x3];
7294 	u8         offset[0x5];
7295 	u8         reserved_at_18[0x3];
7296 	u8         length[0x5];
7297 
7298 	u8         data[0x20];
7299 };
7300 
7301 struct mlx5_ifc_add_action_in_bits {
7302 	u8         action_type[0x4];
7303 	u8         field[0xc];
7304 	u8         reserved_at_10[0x10];
7305 
7306 	u8         data[0x20];
7307 };
7308 
7309 struct mlx5_ifc_copy_action_in_bits {
7310 	u8         action_type[0x4];
7311 	u8         src_field[0xc];
7312 	u8         reserved_at_10[0x3];
7313 	u8         src_offset[0x5];
7314 	u8         reserved_at_18[0x3];
7315 	u8         length[0x5];
7316 
7317 	u8         reserved_at_20[0x4];
7318 	u8         dst_field[0xc];
7319 	u8         reserved_at_30[0x3];
7320 	u8         dst_offset[0x5];
7321 	u8         reserved_at_38[0x8];
7322 };
7323 
7324 union mlx5_ifc_set_add_copy_action_in_auto_bits {
7325 	struct mlx5_ifc_set_action_in_bits  set_action_in;
7326 	struct mlx5_ifc_add_action_in_bits  add_action_in;
7327 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7328 	u8         reserved_at_0[0x40];
7329 };
7330 
7331 enum {
7332 	MLX5_ACTION_TYPE_SET   = 0x1,
7333 	MLX5_ACTION_TYPE_ADD   = 0x2,
7334 	MLX5_ACTION_TYPE_COPY  = 0x3,
7335 };
7336 
7337 enum {
7338 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7339 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7340 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7341 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7342 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7343 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7344 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7345 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7346 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7347 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7348 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7349 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7350 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7351 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7352 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7353 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7354 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7355 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7356 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7357 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7358 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7359 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7360 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7361 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7362 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7363 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7364 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7365 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7366 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7367 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7368 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7369 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7370 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7371 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7372 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7373 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7374 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7375 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7376 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7377 	MLX5_ACTION_IN_FIELD_PSP_SYNDROME      = 0x71,
7378 };
7379 
7380 struct mlx5_ifc_alloc_modify_header_context_out_bits {
7381 	u8         status[0x8];
7382 	u8         reserved_at_8[0x18];
7383 
7384 	u8         syndrome[0x20];
7385 
7386 	u8         modify_header_id[0x20];
7387 
7388 	u8         reserved_at_60[0x20];
7389 };
7390 
7391 struct mlx5_ifc_alloc_modify_header_context_in_bits {
7392 	u8         opcode[0x10];
7393 	u8         reserved_at_10[0x10];
7394 
7395 	u8         reserved_at_20[0x10];
7396 	u8         op_mod[0x10];
7397 
7398 	u8         reserved_at_40[0x20];
7399 
7400 	u8         table_type[0x8];
7401 	u8         reserved_at_68[0x10];
7402 	u8         num_of_actions[0x8];
7403 
7404 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7405 };
7406 
7407 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7408 	u8         status[0x8];
7409 	u8         reserved_at_8[0x18];
7410 
7411 	u8         syndrome[0x20];
7412 
7413 	u8         reserved_at_40[0x40];
7414 };
7415 
7416 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7417 	u8         opcode[0x10];
7418 	u8         reserved_at_10[0x10];
7419 
7420 	u8         reserved_at_20[0x10];
7421 	u8         op_mod[0x10];
7422 
7423 	u8         modify_header_id[0x20];
7424 
7425 	u8         reserved_at_60[0x20];
7426 };
7427 
7428 struct mlx5_ifc_query_modify_header_context_in_bits {
7429 	u8         opcode[0x10];
7430 	u8         uid[0x10];
7431 
7432 	u8         reserved_at_20[0x10];
7433 	u8         op_mod[0x10];
7434 
7435 	u8         modify_header_id[0x20];
7436 
7437 	u8         reserved_at_60[0xa0];
7438 };
7439 
7440 struct mlx5_ifc_query_dct_out_bits {
7441 	u8         status[0x8];
7442 	u8         reserved_at_8[0x18];
7443 
7444 	u8         syndrome[0x20];
7445 
7446 	u8         reserved_at_40[0x40];
7447 
7448 	struct mlx5_ifc_dctc_bits dct_context_entry;
7449 
7450 	u8         reserved_at_280[0x180];
7451 };
7452 
7453 struct mlx5_ifc_query_dct_in_bits {
7454 	u8         opcode[0x10];
7455 	u8         reserved_at_10[0x10];
7456 
7457 	u8         reserved_at_20[0x10];
7458 	u8         op_mod[0x10];
7459 
7460 	u8         reserved_at_40[0x8];
7461 	u8         dctn[0x18];
7462 
7463 	u8         reserved_at_60[0x20];
7464 };
7465 
7466 struct mlx5_ifc_query_cq_out_bits {
7467 	u8         status[0x8];
7468 	u8         reserved_at_8[0x18];
7469 
7470 	u8         syndrome[0x20];
7471 
7472 	u8         reserved_at_40[0x40];
7473 
7474 	struct mlx5_ifc_cqc_bits cq_context;
7475 
7476 	u8         reserved_at_280[0x600];
7477 
7478 	u8         pas[][0x40];
7479 };
7480 
7481 struct mlx5_ifc_query_cq_in_bits {
7482 	u8         opcode[0x10];
7483 	u8         reserved_at_10[0x10];
7484 
7485 	u8         reserved_at_20[0x10];
7486 	u8         op_mod[0x10];
7487 
7488 	u8         reserved_at_40[0x8];
7489 	u8         cqn[0x18];
7490 
7491 	u8         reserved_at_60[0x20];
7492 };
7493 
7494 struct mlx5_ifc_query_cong_status_out_bits {
7495 	u8         status[0x8];
7496 	u8         reserved_at_8[0x18];
7497 
7498 	u8         syndrome[0x20];
7499 
7500 	u8         reserved_at_40[0x20];
7501 
7502 	u8         enable[0x1];
7503 	u8         tag_enable[0x1];
7504 	u8         reserved_at_62[0x1e];
7505 };
7506 
7507 struct mlx5_ifc_query_cong_status_in_bits {
7508 	u8         opcode[0x10];
7509 	u8         reserved_at_10[0x10];
7510 
7511 	u8         reserved_at_20[0x10];
7512 	u8         op_mod[0x10];
7513 
7514 	u8         reserved_at_40[0x18];
7515 	u8         priority[0x4];
7516 	u8         cong_protocol[0x4];
7517 
7518 	u8         reserved_at_60[0x20];
7519 };
7520 
7521 struct mlx5_ifc_query_cong_statistics_out_bits {
7522 	u8         status[0x8];
7523 	u8         reserved_at_8[0x18];
7524 
7525 	u8         syndrome[0x20];
7526 
7527 	u8         reserved_at_40[0x40];
7528 
7529 	u8         rp_cur_flows[0x20];
7530 
7531 	u8         sum_flows[0x20];
7532 
7533 	u8         rp_cnp_ignored_high[0x20];
7534 
7535 	u8         rp_cnp_ignored_low[0x20];
7536 
7537 	u8         rp_cnp_handled_high[0x20];
7538 
7539 	u8         rp_cnp_handled_low[0x20];
7540 
7541 	u8         reserved_at_140[0x100];
7542 
7543 	u8         time_stamp_high[0x20];
7544 
7545 	u8         time_stamp_low[0x20];
7546 
7547 	u8         accumulators_period[0x20];
7548 
7549 	u8         np_ecn_marked_roce_packets_high[0x20];
7550 
7551 	u8         np_ecn_marked_roce_packets_low[0x20];
7552 
7553 	u8         np_cnp_sent_high[0x20];
7554 
7555 	u8         np_cnp_sent_low[0x20];
7556 
7557 	u8         reserved_at_320[0x560];
7558 };
7559 
7560 struct mlx5_ifc_query_cong_statistics_in_bits {
7561 	u8         opcode[0x10];
7562 	u8         reserved_at_10[0x10];
7563 
7564 	u8         reserved_at_20[0x10];
7565 	u8         op_mod[0x10];
7566 
7567 	u8         clear[0x1];
7568 	u8         reserved_at_41[0x1f];
7569 
7570 	u8         reserved_at_60[0x20];
7571 };
7572 
7573 struct mlx5_ifc_query_cong_params_out_bits {
7574 	u8         status[0x8];
7575 	u8         reserved_at_8[0x18];
7576 
7577 	u8         syndrome[0x20];
7578 
7579 	u8         reserved_at_40[0x40];
7580 
7581 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7582 };
7583 
7584 struct mlx5_ifc_query_cong_params_in_bits {
7585 	u8         opcode[0x10];
7586 	u8         reserved_at_10[0x10];
7587 
7588 	u8         reserved_at_20[0x10];
7589 	u8         op_mod[0x10];
7590 
7591 	u8         reserved_at_40[0x1c];
7592 	u8         cong_protocol[0x4];
7593 
7594 	u8         reserved_at_60[0x20];
7595 };
7596 
7597 struct mlx5_ifc_query_adapter_out_bits {
7598 	u8         status[0x8];
7599 	u8         reserved_at_8[0x18];
7600 
7601 	u8         syndrome[0x20];
7602 
7603 	u8         reserved_at_40[0x40];
7604 
7605 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7606 };
7607 
7608 struct mlx5_ifc_query_adapter_in_bits {
7609 	u8         opcode[0x10];
7610 	u8         reserved_at_10[0x10];
7611 
7612 	u8         reserved_at_20[0x10];
7613 	u8         op_mod[0x10];
7614 
7615 	u8         reserved_at_40[0x40];
7616 };
7617 
7618 struct mlx5_ifc_function_vhca_rid_info_reg_bits {
7619 	u8         host_number[0x8];
7620 	u8         host_pci_device_function[0x8];
7621 	u8         host_pci_bus[0x8];
7622 	u8         reserved_at_18[0x3];
7623 	u8         pci_bus_assigned[0x1];
7624 	u8         function_type[0x4];
7625 
7626 	u8         parent_pci_device_function[0x8];
7627 	u8         parent_pci_bus[0x8];
7628 	u8         vhca_id[0x10];
7629 
7630 	u8         reserved_at_40[0x10];
7631 	u8         function_id[0x10];
7632 
7633 	u8         reserved_at_60[0x20];
7634 };
7635 
7636 struct mlx5_ifc_delegated_function_vhca_rid_info_bits {
7637 	struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info;
7638 
7639 	u8         reserved_at_80[0x18];
7640 	u8         manage_profile[0x8];
7641 
7642 	u8         reserved_at_a0[0x60];
7643 };
7644 
7645 struct mlx5_ifc_query_delegated_vhca_out_bits {
7646 	u8         status[0x8];
7647 	u8         reserved_at_8[0x18];
7648 
7649 	u8         syndrome[0x20];
7650 
7651 	u8         reserved_at_40[0x20];
7652 
7653 	u8         reserved_at_60[0x10];
7654 	u8         functions_count[0x10];
7655 
7656 	u8         reserved_at_80[0x80];
7657 
7658 	struct mlx5_ifc_delegated_function_vhca_rid_info_bits
7659 			delegated_function_vhca_rid_info[];
7660 };
7661 
7662 struct mlx5_ifc_query_delegated_vhca_in_bits {
7663 	u8         opcode[0x10];
7664 	u8         uid[0x10];
7665 
7666 	u8         reserved_at_20[0x10];
7667 	u8         op_mod[0x10];
7668 
7669 	u8         reserved_at_40[0x40];
7670 };
7671 
7672 struct mlx5_ifc_create_esw_vport_out_bits {
7673 	u8         status[0x8];
7674 	u8         reserved_at_8[0x18];
7675 
7676 	u8         syndrome[0x20];
7677 
7678 	u8         reserved_at_40[0x20];
7679 
7680 	u8         reserved_at_60[0x10];
7681 	u8         vport_num[0x10];
7682 };
7683 
7684 struct mlx5_ifc_create_esw_vport_in_bits {
7685 	u8         opcode[0x10];
7686 	u8         reserved_at_10[0x10];
7687 
7688 	u8         reserved_at_20[0x10];
7689 	u8         op_mod[0x10];
7690 
7691 	u8         reserved_at_40[0x10];
7692 	u8         managed_vhca_id[0x10];
7693 
7694 	u8         reserved_at_60[0x20];
7695 };
7696 
7697 struct mlx5_ifc_qp_2rst_out_bits {
7698 	u8         status[0x8];
7699 	u8         reserved_at_8[0x18];
7700 
7701 	u8         syndrome[0x20];
7702 
7703 	u8         reserved_at_40[0x40];
7704 };
7705 
7706 struct mlx5_ifc_qp_2rst_in_bits {
7707 	u8         opcode[0x10];
7708 	u8         uid[0x10];
7709 
7710 	u8         reserved_at_20[0x10];
7711 	u8         op_mod[0x10];
7712 
7713 	u8         reserved_at_40[0x8];
7714 	u8         qpn[0x18];
7715 
7716 	u8         reserved_at_60[0x20];
7717 };
7718 
7719 struct mlx5_ifc_qp_2err_out_bits {
7720 	u8         status[0x8];
7721 	u8         reserved_at_8[0x18];
7722 
7723 	u8         syndrome[0x20];
7724 
7725 	u8         reserved_at_40[0x40];
7726 };
7727 
7728 struct mlx5_ifc_qp_2err_in_bits {
7729 	u8         opcode[0x10];
7730 	u8         uid[0x10];
7731 
7732 	u8         reserved_at_20[0x10];
7733 	u8         op_mod[0x10];
7734 
7735 	u8         reserved_at_40[0x8];
7736 	u8         qpn[0x18];
7737 
7738 	u8         reserved_at_60[0x20];
7739 };
7740 
7741 struct mlx5_ifc_trans_page_fault_info_bits {
7742 	u8         error[0x1];
7743 	u8         reserved_at_1[0x4];
7744 	u8         page_fault_type[0x3];
7745 	u8         wq_number[0x18];
7746 
7747 	u8         reserved_at_20[0x8];
7748 	u8         fault_token[0x18];
7749 };
7750 
7751 struct mlx5_ifc_mem_page_fault_info_bits {
7752 	u8          error[0x1];
7753 	u8          reserved_at_1[0xf];
7754 	u8          fault_token_47_32[0x10];
7755 
7756 	u8          fault_token_31_0[0x20];
7757 };
7758 
7759 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7760 	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7761 	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7762 	u8          reserved_at_0[0x40];
7763 };
7764 
7765 struct mlx5_ifc_page_fault_resume_out_bits {
7766 	u8         status[0x8];
7767 	u8         reserved_at_8[0x18];
7768 
7769 	u8         syndrome[0x20];
7770 
7771 	u8         reserved_at_40[0x40];
7772 };
7773 
7774 struct mlx5_ifc_page_fault_resume_in_bits {
7775 	u8         opcode[0x10];
7776 	u8         reserved_at_10[0x10];
7777 
7778 	u8         reserved_at_20[0x10];
7779 	u8         op_mod[0x10];
7780 
7781 	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7782 		page_fault_info;
7783 };
7784 
7785 struct mlx5_ifc_nop_out_bits {
7786 	u8         status[0x8];
7787 	u8         reserved_at_8[0x18];
7788 
7789 	u8         syndrome[0x20];
7790 
7791 	u8         reserved_at_40[0x40];
7792 };
7793 
7794 struct mlx5_ifc_nop_in_bits {
7795 	u8         opcode[0x10];
7796 	u8         reserved_at_10[0x10];
7797 
7798 	u8         reserved_at_20[0x10];
7799 	u8         op_mod[0x10];
7800 
7801 	u8         reserved_at_40[0x40];
7802 };
7803 
7804 struct mlx5_ifc_modify_vport_state_out_bits {
7805 	u8         status[0x8];
7806 	u8         reserved_at_8[0x18];
7807 
7808 	u8         syndrome[0x20];
7809 
7810 	u8         reserved_at_40[0x40];
7811 };
7812 
7813 struct mlx5_ifc_modify_vport_state_in_bits {
7814 	u8         opcode[0x10];
7815 	u8         reserved_at_10[0x10];
7816 
7817 	u8         reserved_at_20[0x10];
7818 	u8         op_mod[0x10];
7819 
7820 	u8         other_vport[0x1];
7821 	u8         reserved_at_41[0xf];
7822 	u8         vport_number[0x10];
7823 
7824 	u8         max_tx_speed[0x10];
7825 	u8         ingress_connect[0x1];
7826 	u8         egress_connect[0x1];
7827 	u8         ingress_connect_valid[0x1];
7828 	u8         egress_connect_valid[0x1];
7829 	u8         reserved_at_74[0x4];
7830 	u8         admin_state[0x4];
7831 	u8         reserved_at_7c[0x4];
7832 };
7833 
7834 struct mlx5_ifc_modify_tis_out_bits {
7835 	u8         status[0x8];
7836 	u8         reserved_at_8[0x18];
7837 
7838 	u8         syndrome[0x20];
7839 
7840 	u8         reserved_at_40[0x40];
7841 };
7842 
7843 struct mlx5_ifc_modify_tis_bitmask_bits {
7844 	u8         reserved_at_0[0x20];
7845 
7846 	u8         reserved_at_20[0x1d];
7847 	u8         lag_tx_port_affinity[0x1];
7848 	u8         strict_lag_tx_port_affinity[0x1];
7849 	u8         prio[0x1];
7850 };
7851 
7852 struct mlx5_ifc_modify_tis_in_bits {
7853 	u8         opcode[0x10];
7854 	u8         uid[0x10];
7855 
7856 	u8         reserved_at_20[0x10];
7857 	u8         op_mod[0x10];
7858 
7859 	u8         reserved_at_40[0x8];
7860 	u8         tisn[0x18];
7861 
7862 	u8         reserved_at_60[0x20];
7863 
7864 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7865 
7866 	u8         reserved_at_c0[0x40];
7867 
7868 	struct mlx5_ifc_tisc_bits ctx;
7869 };
7870 
7871 struct mlx5_ifc_modify_tir_bitmask_bits {
7872 	u8	   reserved_at_0[0x20];
7873 
7874 	u8         reserved_at_20[0x1b];
7875 	u8         self_lb_en[0x1];
7876 	u8         reserved_at_3c[0x1];
7877 	u8         hash[0x1];
7878 	u8         reserved_at_3e[0x1];
7879 	u8         packet_merge[0x1];
7880 };
7881 
7882 struct mlx5_ifc_modify_tir_out_bits {
7883 	u8         status[0x8];
7884 	u8         reserved_at_8[0x18];
7885 
7886 	u8         syndrome[0x20];
7887 
7888 	u8         reserved_at_40[0x40];
7889 };
7890 
7891 struct mlx5_ifc_modify_tir_in_bits {
7892 	u8         opcode[0x10];
7893 	u8         uid[0x10];
7894 
7895 	u8         reserved_at_20[0x10];
7896 	u8         op_mod[0x10];
7897 
7898 	u8         reserved_at_40[0x8];
7899 	u8         tirn[0x18];
7900 
7901 	u8         reserved_at_60[0x20];
7902 
7903 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7904 
7905 	u8         reserved_at_c0[0x40];
7906 
7907 	struct mlx5_ifc_tirc_bits ctx;
7908 };
7909 
7910 struct mlx5_ifc_modify_sq_out_bits {
7911 	u8         status[0x8];
7912 	u8         reserved_at_8[0x18];
7913 
7914 	u8         syndrome[0x20];
7915 
7916 	u8         reserved_at_40[0x40];
7917 };
7918 
7919 struct mlx5_ifc_modify_sq_in_bits {
7920 	u8         opcode[0x10];
7921 	u8         uid[0x10];
7922 
7923 	u8         reserved_at_20[0x10];
7924 	u8         op_mod[0x10];
7925 
7926 	u8         sq_state[0x4];
7927 	u8         reserved_at_44[0x4];
7928 	u8         sqn[0x18];
7929 
7930 	u8         reserved_at_60[0x20];
7931 
7932 	u8         modify_bitmask[0x40];
7933 
7934 	u8         reserved_at_c0[0x40];
7935 
7936 	struct mlx5_ifc_sqc_bits ctx;
7937 };
7938 
7939 struct mlx5_ifc_modify_scheduling_element_out_bits {
7940 	u8         status[0x8];
7941 	u8         reserved_at_8[0x18];
7942 
7943 	u8         syndrome[0x20];
7944 
7945 	u8         reserved_at_40[0x1c0];
7946 };
7947 
7948 enum {
7949 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7950 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7951 };
7952 
7953 struct mlx5_ifc_modify_scheduling_element_in_bits {
7954 	u8         opcode[0x10];
7955 	u8         reserved_at_10[0x10];
7956 
7957 	u8         reserved_at_20[0x10];
7958 	u8         op_mod[0x10];
7959 
7960 	u8         scheduling_hierarchy[0x8];
7961 	u8         reserved_at_48[0x18];
7962 
7963 	u8         scheduling_element_id[0x20];
7964 
7965 	u8         reserved_at_80[0x20];
7966 
7967 	u8         modify_bitmask[0x20];
7968 
7969 	u8         reserved_at_c0[0x40];
7970 
7971 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7972 
7973 	u8         reserved_at_300[0x100];
7974 };
7975 
7976 struct mlx5_ifc_modify_rqt_out_bits {
7977 	u8         status[0x8];
7978 	u8         reserved_at_8[0x18];
7979 
7980 	u8         syndrome[0x20];
7981 
7982 	u8         reserved_at_40[0x40];
7983 };
7984 
7985 struct mlx5_ifc_rqt_bitmask_bits {
7986 	u8	   reserved_at_0[0x20];
7987 
7988 	u8         reserved_at_20[0x1f];
7989 	u8         rqn_list[0x1];
7990 };
7991 
7992 struct mlx5_ifc_modify_rqt_in_bits {
7993 	u8         opcode[0x10];
7994 	u8         uid[0x10];
7995 
7996 	u8         reserved_at_20[0x10];
7997 	u8         op_mod[0x10];
7998 
7999 	u8         reserved_at_40[0x8];
8000 	u8         rqtn[0x18];
8001 
8002 	u8         reserved_at_60[0x20];
8003 
8004 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
8005 
8006 	u8         reserved_at_c0[0x40];
8007 
8008 	struct mlx5_ifc_rqtc_bits ctx;
8009 };
8010 
8011 struct mlx5_ifc_modify_rq_out_bits {
8012 	u8         status[0x8];
8013 	u8         reserved_at_8[0x18];
8014 
8015 	u8         syndrome[0x20];
8016 
8017 	u8         reserved_at_40[0x40];
8018 };
8019 
8020 enum {
8021 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
8022 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
8023 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
8024 };
8025 
8026 struct mlx5_ifc_modify_rq_in_bits {
8027 	u8         opcode[0x10];
8028 	u8         uid[0x10];
8029 
8030 	u8         reserved_at_20[0x10];
8031 	u8         op_mod[0x10];
8032 
8033 	u8         rq_state[0x4];
8034 	u8         reserved_at_44[0x4];
8035 	u8         rqn[0x18];
8036 
8037 	u8         reserved_at_60[0x20];
8038 
8039 	u8         modify_bitmask[0x40];
8040 
8041 	u8         reserved_at_c0[0x40];
8042 
8043 	struct mlx5_ifc_rqc_bits ctx;
8044 };
8045 
8046 struct mlx5_ifc_modify_rmp_out_bits {
8047 	u8         status[0x8];
8048 	u8         reserved_at_8[0x18];
8049 
8050 	u8         syndrome[0x20];
8051 
8052 	u8         reserved_at_40[0x40];
8053 };
8054 
8055 struct mlx5_ifc_rmp_bitmask_bits {
8056 	u8	   reserved_at_0[0x20];
8057 
8058 	u8         reserved_at_20[0x1f];
8059 	u8         lwm[0x1];
8060 };
8061 
8062 struct mlx5_ifc_modify_rmp_in_bits {
8063 	u8         opcode[0x10];
8064 	u8         uid[0x10];
8065 
8066 	u8         reserved_at_20[0x10];
8067 	u8         op_mod[0x10];
8068 
8069 	u8         rmp_state[0x4];
8070 	u8         reserved_at_44[0x4];
8071 	u8         rmpn[0x18];
8072 
8073 	u8         reserved_at_60[0x20];
8074 
8075 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
8076 
8077 	u8         reserved_at_c0[0x40];
8078 
8079 	struct mlx5_ifc_rmpc_bits ctx;
8080 };
8081 
8082 struct mlx5_ifc_modify_nic_vport_context_out_bits {
8083 	u8         status[0x8];
8084 	u8         reserved_at_8[0x18];
8085 
8086 	u8         syndrome[0x20];
8087 
8088 	u8         reserved_at_40[0x40];
8089 };
8090 
8091 struct mlx5_ifc_modify_nic_vport_field_select_bits {
8092 	u8         reserved_at_0[0x12];
8093 	u8	   affiliation[0x1];
8094 	u8	   reserved_at_13[0x1];
8095 	u8         disable_uc_local_lb[0x1];
8096 	u8         disable_mc_local_lb[0x1];
8097 	u8         node_guid[0x1];
8098 	u8         port_guid[0x1];
8099 	u8         min_inline[0x1];
8100 	u8         mtu[0x1];
8101 	u8         change_event[0x1];
8102 	u8         promisc[0x1];
8103 	u8         permanent_address[0x1];
8104 	u8         addresses_list[0x1];
8105 	u8         roce_en[0x1];
8106 	u8         reserved_at_1f[0x1];
8107 };
8108 
8109 struct mlx5_ifc_modify_nic_vport_context_in_bits {
8110 	u8         opcode[0x10];
8111 	u8         reserved_at_10[0x10];
8112 
8113 	u8         reserved_at_20[0x10];
8114 	u8         op_mod[0x10];
8115 
8116 	u8         other_vport[0x1];
8117 	u8         reserved_at_41[0xf];
8118 	u8         vport_number[0x10];
8119 
8120 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
8121 
8122 	u8         reserved_at_80[0x780];
8123 
8124 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
8125 };
8126 
8127 struct mlx5_ifc_modify_hca_vport_context_out_bits {
8128 	u8         status[0x8];
8129 	u8         reserved_at_8[0x18];
8130 
8131 	u8         syndrome[0x20];
8132 
8133 	u8         reserved_at_40[0x40];
8134 };
8135 
8136 struct mlx5_ifc_modify_hca_vport_context_in_bits {
8137 	u8         opcode[0x10];
8138 	u8         reserved_at_10[0x10];
8139 
8140 	u8         reserved_at_20[0x10];
8141 	u8         op_mod[0x10];
8142 
8143 	u8         other_vport[0x1];
8144 	u8         reserved_at_41[0xb];
8145 	u8         port_num[0x4];
8146 	u8         vport_number[0x10];
8147 
8148 	u8         reserved_at_60[0x20];
8149 
8150 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
8151 };
8152 
8153 struct mlx5_ifc_modify_cq_out_bits {
8154 	u8         status[0x8];
8155 	u8         reserved_at_8[0x18];
8156 
8157 	u8         syndrome[0x20];
8158 
8159 	u8         reserved_at_40[0x40];
8160 };
8161 
8162 enum {
8163 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
8164 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
8165 };
8166 
8167 struct mlx5_ifc_modify_cq_in_bits {
8168 	u8         opcode[0x10];
8169 	u8         uid[0x10];
8170 
8171 	u8         reserved_at_20[0x10];
8172 	u8         op_mod[0x10];
8173 
8174 	u8         reserved_at_40[0x8];
8175 	u8         cqn[0x18];
8176 
8177 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
8178 
8179 	struct mlx5_ifc_cqc_bits cq_context;
8180 
8181 	u8         reserved_at_280[0x60];
8182 
8183 	u8         cq_umem_valid[0x1];
8184 	u8         reserved_at_2e1[0x1f];
8185 
8186 	u8         reserved_at_300[0x580];
8187 
8188 	u8         pas[][0x40];
8189 };
8190 
8191 struct mlx5_ifc_modify_cong_status_out_bits {
8192 	u8         status[0x8];
8193 	u8         reserved_at_8[0x18];
8194 
8195 	u8         syndrome[0x20];
8196 
8197 	u8         reserved_at_40[0x40];
8198 };
8199 
8200 struct mlx5_ifc_modify_cong_status_in_bits {
8201 	u8         opcode[0x10];
8202 	u8         reserved_at_10[0x10];
8203 
8204 	u8         reserved_at_20[0x10];
8205 	u8         op_mod[0x10];
8206 
8207 	u8         reserved_at_40[0x18];
8208 	u8         priority[0x4];
8209 	u8         cong_protocol[0x4];
8210 
8211 	u8         enable[0x1];
8212 	u8         tag_enable[0x1];
8213 	u8         reserved_at_62[0x1e];
8214 };
8215 
8216 struct mlx5_ifc_modify_cong_params_out_bits {
8217 	u8         status[0x8];
8218 	u8         reserved_at_8[0x18];
8219 
8220 	u8         syndrome[0x20];
8221 
8222 	u8         reserved_at_40[0x40];
8223 };
8224 
8225 struct mlx5_ifc_modify_cong_params_in_bits {
8226 	u8         opcode[0x10];
8227 	u8         reserved_at_10[0x10];
8228 
8229 	u8         reserved_at_20[0x10];
8230 	u8         op_mod[0x10];
8231 
8232 	u8         reserved_at_40[0x1c];
8233 	u8         cong_protocol[0x4];
8234 
8235 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
8236 
8237 	u8         reserved_at_80[0x80];
8238 
8239 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
8240 };
8241 
8242 struct mlx5_ifc_manage_pages_out_bits {
8243 	u8         status[0x8];
8244 	u8         reserved_at_8[0x18];
8245 
8246 	u8         syndrome[0x20];
8247 
8248 	u8         output_num_entries[0x20];
8249 
8250 	u8         reserved_at_60[0x20];
8251 
8252 	u8         pas[][0x40];
8253 };
8254 
8255 enum {
8256 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
8257 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
8258 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
8259 };
8260 
8261 struct mlx5_ifc_manage_pages_in_bits {
8262 	u8         opcode[0x10];
8263 	u8         reserved_at_10[0x10];
8264 
8265 	u8         reserved_at_20[0x10];
8266 	u8         op_mod[0x10];
8267 
8268 	u8         embedded_cpu_function[0x1];
8269 	u8         reserved_at_41[0xf];
8270 	u8         function_id[0x10];
8271 
8272 	u8         input_num_entries[0x20];
8273 
8274 	u8         pas[][0x40];
8275 };
8276 
8277 struct mlx5_ifc_mad_ifc_out_bits {
8278 	u8         status[0x8];
8279 	u8         reserved_at_8[0x18];
8280 
8281 	u8         syndrome[0x20];
8282 
8283 	u8         reserved_at_40[0x40];
8284 
8285 	u8         response_mad_packet[256][0x8];
8286 };
8287 
8288 struct mlx5_ifc_mad_ifc_in_bits {
8289 	u8         opcode[0x10];
8290 	u8         reserved_at_10[0x10];
8291 
8292 	u8         reserved_at_20[0x10];
8293 	u8         op_mod[0x10];
8294 
8295 	u8         remote_lid[0x10];
8296 	u8         plane_index[0x8];
8297 	u8         port[0x8];
8298 
8299 	u8         reserved_at_60[0x20];
8300 
8301 	u8         mad[256][0x8];
8302 };
8303 
8304 struct mlx5_ifc_init_hca_out_bits {
8305 	u8         status[0x8];
8306 	u8         reserved_at_8[0x18];
8307 
8308 	u8         syndrome[0x20];
8309 
8310 	u8         reserved_at_40[0x40];
8311 };
8312 
8313 struct mlx5_ifc_init_hca_in_bits {
8314 	u8         opcode[0x10];
8315 	u8         reserved_at_10[0x10];
8316 
8317 	u8         reserved_at_20[0x10];
8318 	u8         op_mod[0x10];
8319 
8320 	u8         reserved_at_40[0x20];
8321 
8322 	u8         reserved_at_60[0x2];
8323 	u8         sw_vhca_id[0xe];
8324 	u8         reserved_at_70[0x10];
8325 
8326 	u8	   sw_owner_id[4][0x20];
8327 };
8328 
8329 struct mlx5_ifc_init2rtr_qp_out_bits {
8330 	u8         status[0x8];
8331 	u8         reserved_at_8[0x18];
8332 
8333 	u8         syndrome[0x20];
8334 
8335 	u8         reserved_at_40[0x20];
8336 	u8         ece[0x20];
8337 };
8338 
8339 struct mlx5_ifc_init2rtr_qp_in_bits {
8340 	u8         opcode[0x10];
8341 	u8         uid[0x10];
8342 
8343 	u8         reserved_at_20[0x10];
8344 	u8         op_mod[0x10];
8345 
8346 	u8         reserved_at_40[0x8];
8347 	u8         qpn[0x18];
8348 
8349 	u8         reserved_at_60[0x20];
8350 
8351 	u8         opt_param_mask[0x20];
8352 
8353 	u8         ece[0x20];
8354 
8355 	struct mlx5_ifc_qpc_bits qpc;
8356 
8357 	u8         reserved_at_800[0x80];
8358 };
8359 
8360 struct mlx5_ifc_init2init_qp_out_bits {
8361 	u8         status[0x8];
8362 	u8         reserved_at_8[0x18];
8363 
8364 	u8         syndrome[0x20];
8365 
8366 	u8         reserved_at_40[0x20];
8367 	u8         ece[0x20];
8368 };
8369 
8370 struct mlx5_ifc_init2init_qp_in_bits {
8371 	u8         opcode[0x10];
8372 	u8         uid[0x10];
8373 
8374 	u8         reserved_at_20[0x10];
8375 	u8         op_mod[0x10];
8376 
8377 	u8         reserved_at_40[0x8];
8378 	u8         qpn[0x18];
8379 
8380 	u8         reserved_at_60[0x20];
8381 
8382 	u8         opt_param_mask[0x20];
8383 
8384 	u8         ece[0x20];
8385 
8386 	struct mlx5_ifc_qpc_bits qpc;
8387 
8388 	u8         reserved_at_800[0x80];
8389 };
8390 
8391 struct mlx5_ifc_get_dropped_packet_log_out_bits {
8392 	u8         status[0x8];
8393 	u8         reserved_at_8[0x18];
8394 
8395 	u8         syndrome[0x20];
8396 
8397 	u8         reserved_at_40[0x40];
8398 
8399 	u8         packet_headers_log[128][0x8];
8400 
8401 	u8         packet_syndrome[64][0x8];
8402 };
8403 
8404 struct mlx5_ifc_get_dropped_packet_log_in_bits {
8405 	u8         opcode[0x10];
8406 	u8         reserved_at_10[0x10];
8407 
8408 	u8         reserved_at_20[0x10];
8409 	u8         op_mod[0x10];
8410 
8411 	u8         reserved_at_40[0x40];
8412 };
8413 
8414 struct mlx5_ifc_gen_eqe_in_bits {
8415 	u8         opcode[0x10];
8416 	u8         reserved_at_10[0x10];
8417 
8418 	u8         reserved_at_20[0x10];
8419 	u8         op_mod[0x10];
8420 
8421 	u8         reserved_at_40[0x18];
8422 	u8         eq_number[0x8];
8423 
8424 	u8         reserved_at_60[0x20];
8425 
8426 	u8         eqe[64][0x8];
8427 };
8428 
8429 struct mlx5_ifc_gen_eq_out_bits {
8430 	u8         status[0x8];
8431 	u8         reserved_at_8[0x18];
8432 
8433 	u8         syndrome[0x20];
8434 
8435 	u8         reserved_at_40[0x40];
8436 };
8437 
8438 struct mlx5_ifc_enable_hca_out_bits {
8439 	u8         status[0x8];
8440 	u8         reserved_at_8[0x18];
8441 
8442 	u8         syndrome[0x20];
8443 
8444 	u8         reserved_at_40[0x20];
8445 };
8446 
8447 struct mlx5_ifc_enable_hca_in_bits {
8448 	u8         opcode[0x10];
8449 	u8         reserved_at_10[0x10];
8450 
8451 	u8         reserved_at_20[0x10];
8452 	u8         op_mod[0x10];
8453 
8454 	u8         embedded_cpu_function[0x1];
8455 	u8         reserved_at_41[0xf];
8456 	u8         function_id[0x10];
8457 
8458 	u8         reserved_at_60[0x20];
8459 };
8460 
8461 struct mlx5_ifc_drain_dct_out_bits {
8462 	u8         status[0x8];
8463 	u8         reserved_at_8[0x18];
8464 
8465 	u8         syndrome[0x20];
8466 
8467 	u8         reserved_at_40[0x40];
8468 };
8469 
8470 struct mlx5_ifc_drain_dct_in_bits {
8471 	u8         opcode[0x10];
8472 	u8         uid[0x10];
8473 
8474 	u8         reserved_at_20[0x10];
8475 	u8         op_mod[0x10];
8476 
8477 	u8         reserved_at_40[0x8];
8478 	u8         dctn[0x18];
8479 
8480 	u8         reserved_at_60[0x20];
8481 };
8482 
8483 struct mlx5_ifc_disable_hca_out_bits {
8484 	u8         status[0x8];
8485 	u8         reserved_at_8[0x18];
8486 
8487 	u8         syndrome[0x20];
8488 
8489 	u8         reserved_at_40[0x20];
8490 };
8491 
8492 struct mlx5_ifc_disable_hca_in_bits {
8493 	u8         opcode[0x10];
8494 	u8         reserved_at_10[0x10];
8495 
8496 	u8         reserved_at_20[0x10];
8497 	u8         op_mod[0x10];
8498 
8499 	u8         embedded_cpu_function[0x1];
8500 	u8         reserved_at_41[0xf];
8501 	u8         function_id[0x10];
8502 
8503 	u8         reserved_at_60[0x20];
8504 };
8505 
8506 struct mlx5_ifc_detach_from_mcg_out_bits {
8507 	u8         status[0x8];
8508 	u8         reserved_at_8[0x18];
8509 
8510 	u8         syndrome[0x20];
8511 
8512 	u8         reserved_at_40[0x40];
8513 };
8514 
8515 struct mlx5_ifc_detach_from_mcg_in_bits {
8516 	u8         opcode[0x10];
8517 	u8         uid[0x10];
8518 
8519 	u8         reserved_at_20[0x10];
8520 	u8         op_mod[0x10];
8521 
8522 	u8         reserved_at_40[0x8];
8523 	u8         qpn[0x18];
8524 
8525 	u8         reserved_at_60[0x20];
8526 
8527 	u8         multicast_gid[16][0x8];
8528 };
8529 
8530 struct mlx5_ifc_destroy_xrq_out_bits {
8531 	u8         status[0x8];
8532 	u8         reserved_at_8[0x18];
8533 
8534 	u8         syndrome[0x20];
8535 
8536 	u8         reserved_at_40[0x40];
8537 };
8538 
8539 struct mlx5_ifc_destroy_xrq_in_bits {
8540 	u8         opcode[0x10];
8541 	u8         uid[0x10];
8542 
8543 	u8         reserved_at_20[0x10];
8544 	u8         op_mod[0x10];
8545 
8546 	u8         reserved_at_40[0x8];
8547 	u8         xrqn[0x18];
8548 
8549 	u8         reserved_at_60[0x20];
8550 };
8551 
8552 struct mlx5_ifc_destroy_xrc_srq_out_bits {
8553 	u8         status[0x8];
8554 	u8         reserved_at_8[0x18];
8555 
8556 	u8         syndrome[0x20];
8557 
8558 	u8         reserved_at_40[0x40];
8559 };
8560 
8561 struct mlx5_ifc_destroy_xrc_srq_in_bits {
8562 	u8         opcode[0x10];
8563 	u8         uid[0x10];
8564 
8565 	u8         reserved_at_20[0x10];
8566 	u8         op_mod[0x10];
8567 
8568 	u8         reserved_at_40[0x8];
8569 	u8         xrc_srqn[0x18];
8570 
8571 	u8         reserved_at_60[0x20];
8572 };
8573 
8574 struct mlx5_ifc_destroy_tis_out_bits {
8575 	u8         status[0x8];
8576 	u8         reserved_at_8[0x18];
8577 
8578 	u8         syndrome[0x20];
8579 
8580 	u8         reserved_at_40[0x40];
8581 };
8582 
8583 struct mlx5_ifc_destroy_tis_in_bits {
8584 	u8         opcode[0x10];
8585 	u8         uid[0x10];
8586 
8587 	u8         reserved_at_20[0x10];
8588 	u8         op_mod[0x10];
8589 
8590 	u8         reserved_at_40[0x8];
8591 	u8         tisn[0x18];
8592 
8593 	u8         reserved_at_60[0x20];
8594 };
8595 
8596 struct mlx5_ifc_destroy_tir_out_bits {
8597 	u8         status[0x8];
8598 	u8         reserved_at_8[0x18];
8599 
8600 	u8         syndrome[0x20];
8601 
8602 	u8         reserved_at_40[0x40];
8603 };
8604 
8605 struct mlx5_ifc_destroy_tir_in_bits {
8606 	u8         opcode[0x10];
8607 	u8         uid[0x10];
8608 
8609 	u8         reserved_at_20[0x10];
8610 	u8         op_mod[0x10];
8611 
8612 	u8         reserved_at_40[0x8];
8613 	u8         tirn[0x18];
8614 
8615 	u8         reserved_at_60[0x20];
8616 };
8617 
8618 struct mlx5_ifc_destroy_srq_out_bits {
8619 	u8         status[0x8];
8620 	u8         reserved_at_8[0x18];
8621 
8622 	u8         syndrome[0x20];
8623 
8624 	u8         reserved_at_40[0x40];
8625 };
8626 
8627 struct mlx5_ifc_destroy_srq_in_bits {
8628 	u8         opcode[0x10];
8629 	u8         uid[0x10];
8630 
8631 	u8         reserved_at_20[0x10];
8632 	u8         op_mod[0x10];
8633 
8634 	u8         reserved_at_40[0x8];
8635 	u8         srqn[0x18];
8636 
8637 	u8         reserved_at_60[0x20];
8638 };
8639 
8640 struct mlx5_ifc_destroy_sq_out_bits {
8641 	u8         status[0x8];
8642 	u8         reserved_at_8[0x18];
8643 
8644 	u8         syndrome[0x20];
8645 
8646 	u8         reserved_at_40[0x40];
8647 };
8648 
8649 struct mlx5_ifc_destroy_sq_in_bits {
8650 	u8         opcode[0x10];
8651 	u8         uid[0x10];
8652 
8653 	u8         reserved_at_20[0x10];
8654 	u8         op_mod[0x10];
8655 
8656 	u8         reserved_at_40[0x8];
8657 	u8         sqn[0x18];
8658 
8659 	u8         reserved_at_60[0x20];
8660 };
8661 
8662 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8663 	u8         status[0x8];
8664 	u8         reserved_at_8[0x18];
8665 
8666 	u8         syndrome[0x20];
8667 
8668 	u8         reserved_at_40[0x1c0];
8669 };
8670 
8671 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8672 	u8         opcode[0x10];
8673 	u8         reserved_at_10[0x10];
8674 
8675 	u8         reserved_at_20[0x10];
8676 	u8         op_mod[0x10];
8677 
8678 	u8         scheduling_hierarchy[0x8];
8679 	u8         reserved_at_48[0x18];
8680 
8681 	u8         scheduling_element_id[0x20];
8682 
8683 	u8         reserved_at_80[0x180];
8684 };
8685 
8686 struct mlx5_ifc_destroy_rqt_out_bits {
8687 	u8         status[0x8];
8688 	u8         reserved_at_8[0x18];
8689 
8690 	u8         syndrome[0x20];
8691 
8692 	u8         reserved_at_40[0x40];
8693 };
8694 
8695 struct mlx5_ifc_destroy_rqt_in_bits {
8696 	u8         opcode[0x10];
8697 	u8         uid[0x10];
8698 
8699 	u8         reserved_at_20[0x10];
8700 	u8         op_mod[0x10];
8701 
8702 	u8         reserved_at_40[0x8];
8703 	u8         rqtn[0x18];
8704 
8705 	u8         reserved_at_60[0x20];
8706 };
8707 
8708 struct mlx5_ifc_destroy_rq_out_bits {
8709 	u8         status[0x8];
8710 	u8         reserved_at_8[0x18];
8711 
8712 	u8         syndrome[0x20];
8713 
8714 	u8         reserved_at_40[0x40];
8715 };
8716 
8717 struct mlx5_ifc_destroy_rq_in_bits {
8718 	u8         opcode[0x10];
8719 	u8         uid[0x10];
8720 
8721 	u8         reserved_at_20[0x10];
8722 	u8         op_mod[0x10];
8723 
8724 	u8         reserved_at_40[0x8];
8725 	u8         rqn[0x18];
8726 
8727 	u8         reserved_at_60[0x20];
8728 };
8729 
8730 struct mlx5_ifc_set_delay_drop_params_in_bits {
8731 	u8         opcode[0x10];
8732 	u8         reserved_at_10[0x10];
8733 
8734 	u8         reserved_at_20[0x10];
8735 	u8         op_mod[0x10];
8736 
8737 	u8         reserved_at_40[0x20];
8738 
8739 	u8         reserved_at_60[0x10];
8740 	u8         delay_drop_timeout[0x10];
8741 };
8742 
8743 struct mlx5_ifc_set_delay_drop_params_out_bits {
8744 	u8         status[0x8];
8745 	u8         reserved_at_8[0x18];
8746 
8747 	u8         syndrome[0x20];
8748 
8749 	u8         reserved_at_40[0x40];
8750 };
8751 
8752 struct mlx5_ifc_destroy_rmp_out_bits {
8753 	u8         status[0x8];
8754 	u8         reserved_at_8[0x18];
8755 
8756 	u8         syndrome[0x20];
8757 
8758 	u8         reserved_at_40[0x40];
8759 };
8760 
8761 struct mlx5_ifc_destroy_rmp_in_bits {
8762 	u8         opcode[0x10];
8763 	u8         uid[0x10];
8764 
8765 	u8         reserved_at_20[0x10];
8766 	u8         op_mod[0x10];
8767 
8768 	u8         reserved_at_40[0x8];
8769 	u8         rmpn[0x18];
8770 
8771 	u8         reserved_at_60[0x20];
8772 };
8773 
8774 struct mlx5_ifc_destroy_qp_out_bits {
8775 	u8         status[0x8];
8776 	u8         reserved_at_8[0x18];
8777 
8778 	u8         syndrome[0x20];
8779 
8780 	u8         reserved_at_40[0x40];
8781 };
8782 
8783 struct mlx5_ifc_destroy_qp_in_bits {
8784 	u8         opcode[0x10];
8785 	u8         uid[0x10];
8786 
8787 	u8         reserved_at_20[0x10];
8788 	u8         op_mod[0x10];
8789 
8790 	u8         reserved_at_40[0x8];
8791 	u8         qpn[0x18];
8792 
8793 	u8         reserved_at_60[0x20];
8794 };
8795 
8796 struct mlx5_ifc_destroy_psv_out_bits {
8797 	u8         status[0x8];
8798 	u8         reserved_at_8[0x18];
8799 
8800 	u8         syndrome[0x20];
8801 
8802 	u8         reserved_at_40[0x40];
8803 };
8804 
8805 struct mlx5_ifc_destroy_psv_in_bits {
8806 	u8         opcode[0x10];
8807 	u8         reserved_at_10[0x10];
8808 
8809 	u8         reserved_at_20[0x10];
8810 	u8         op_mod[0x10];
8811 
8812 	u8         reserved_at_40[0x8];
8813 	u8         psvn[0x18];
8814 
8815 	u8         reserved_at_60[0x20];
8816 };
8817 
8818 struct mlx5_ifc_destroy_mkey_out_bits {
8819 	u8         status[0x8];
8820 	u8         reserved_at_8[0x18];
8821 
8822 	u8         syndrome[0x20];
8823 
8824 	u8         reserved_at_40[0x40];
8825 };
8826 
8827 struct mlx5_ifc_destroy_mkey_in_bits {
8828 	u8         opcode[0x10];
8829 	u8         uid[0x10];
8830 
8831 	u8         reserved_at_20[0x10];
8832 	u8         op_mod[0x10];
8833 
8834 	u8         reserved_at_40[0x8];
8835 	u8         mkey_index[0x18];
8836 
8837 	u8         reserved_at_60[0x20];
8838 };
8839 
8840 struct mlx5_ifc_destroy_flow_table_out_bits {
8841 	u8         status[0x8];
8842 	u8         reserved_at_8[0x18];
8843 
8844 	u8         syndrome[0x20];
8845 
8846 	u8         reserved_at_40[0x40];
8847 };
8848 
8849 struct mlx5_ifc_destroy_flow_table_in_bits {
8850 	u8         opcode[0x10];
8851 	u8         reserved_at_10[0x10];
8852 
8853 	u8         reserved_at_20[0x10];
8854 	u8         op_mod[0x10];
8855 
8856 	u8         other_vport[0x1];
8857 	u8         other_eswitch[0x1];
8858 	u8         reserved_at_42[0xe];
8859 	u8         vport_number[0x10];
8860 
8861 	u8         reserved_at_60[0x20];
8862 
8863 	u8         table_type[0x8];
8864 	u8         reserved_at_88[0x8];
8865 	u8         eswitch_owner_vhca_id[0x10];
8866 
8867 	u8         reserved_at_a0[0x8];
8868 	u8         table_id[0x18];
8869 
8870 	u8         reserved_at_c0[0x140];
8871 };
8872 
8873 struct mlx5_ifc_destroy_flow_group_out_bits {
8874 	u8         status[0x8];
8875 	u8         reserved_at_8[0x18];
8876 
8877 	u8         syndrome[0x20];
8878 
8879 	u8         reserved_at_40[0x40];
8880 };
8881 
8882 struct mlx5_ifc_destroy_flow_group_in_bits {
8883 	u8         opcode[0x10];
8884 	u8         reserved_at_10[0x10];
8885 
8886 	u8         reserved_at_20[0x10];
8887 	u8         op_mod[0x10];
8888 
8889 	u8         other_vport[0x1];
8890 	u8         other_eswitch[0x1];
8891 	u8         reserved_at_42[0xe];
8892 	u8         vport_number[0x10];
8893 
8894 	u8         reserved_at_60[0x20];
8895 
8896 	u8         table_type[0x8];
8897 	u8         reserved_at_88[0x8];
8898 	u8         eswitch_owner_vhca_id[0x10];
8899 
8900 	u8         reserved_at_a0[0x8];
8901 	u8         table_id[0x18];
8902 
8903 	u8         group_id[0x20];
8904 
8905 	u8         reserved_at_e0[0x120];
8906 };
8907 
8908 struct mlx5_ifc_destroy_eq_out_bits {
8909 	u8         status[0x8];
8910 	u8         reserved_at_8[0x18];
8911 
8912 	u8         syndrome[0x20];
8913 
8914 	u8         reserved_at_40[0x40];
8915 };
8916 
8917 struct mlx5_ifc_destroy_eq_in_bits {
8918 	u8         opcode[0x10];
8919 	u8         reserved_at_10[0x10];
8920 
8921 	u8         reserved_at_20[0x10];
8922 	u8         op_mod[0x10];
8923 
8924 	u8         reserved_at_40[0x18];
8925 	u8         eq_number[0x8];
8926 
8927 	u8         reserved_at_60[0x20];
8928 };
8929 
8930 struct mlx5_ifc_destroy_dct_out_bits {
8931 	u8         status[0x8];
8932 	u8         reserved_at_8[0x18];
8933 
8934 	u8         syndrome[0x20];
8935 
8936 	u8         reserved_at_40[0x40];
8937 };
8938 
8939 struct mlx5_ifc_destroy_dct_in_bits {
8940 	u8         opcode[0x10];
8941 	u8         uid[0x10];
8942 
8943 	u8         reserved_at_20[0x10];
8944 	u8         op_mod[0x10];
8945 
8946 	u8         reserved_at_40[0x8];
8947 	u8         dctn[0x18];
8948 
8949 	u8         reserved_at_60[0x20];
8950 };
8951 
8952 struct mlx5_ifc_destroy_cq_out_bits {
8953 	u8         status[0x8];
8954 	u8         reserved_at_8[0x18];
8955 
8956 	u8         syndrome[0x20];
8957 
8958 	u8         reserved_at_40[0x40];
8959 };
8960 
8961 struct mlx5_ifc_destroy_cq_in_bits {
8962 	u8         opcode[0x10];
8963 	u8         uid[0x10];
8964 
8965 	u8         reserved_at_20[0x10];
8966 	u8         op_mod[0x10];
8967 
8968 	u8         reserved_at_40[0x8];
8969 	u8         cqn[0x18];
8970 
8971 	u8         reserved_at_60[0x20];
8972 };
8973 
8974 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8975 	u8         status[0x8];
8976 	u8         reserved_at_8[0x18];
8977 
8978 	u8         syndrome[0x20];
8979 
8980 	u8         reserved_at_40[0x40];
8981 };
8982 
8983 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8984 	u8         opcode[0x10];
8985 	u8         reserved_at_10[0x10];
8986 
8987 	u8         reserved_at_20[0x10];
8988 	u8         op_mod[0x10];
8989 
8990 	u8         reserved_at_40[0x20];
8991 
8992 	u8         reserved_at_60[0x10];
8993 	u8         vxlan_udp_port[0x10];
8994 };
8995 
8996 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8997 	u8         status[0x8];
8998 	u8         reserved_at_8[0x18];
8999 
9000 	u8         syndrome[0x20];
9001 
9002 	u8         reserved_at_40[0x40];
9003 };
9004 
9005 struct mlx5_ifc_delete_l2_table_entry_in_bits {
9006 	u8         opcode[0x10];
9007 	u8         reserved_at_10[0x10];
9008 
9009 	u8         reserved_at_20[0x10];
9010 	u8         op_mod[0x10];
9011 
9012 	u8         reserved_at_40[0x60];
9013 
9014 	u8         reserved_at_a0[0x8];
9015 	u8         table_index[0x18];
9016 
9017 	u8         reserved_at_c0[0x140];
9018 };
9019 
9020 struct mlx5_ifc_delete_fte_out_bits {
9021 	u8         status[0x8];
9022 	u8         reserved_at_8[0x18];
9023 
9024 	u8         syndrome[0x20];
9025 
9026 	u8         reserved_at_40[0x40];
9027 };
9028 
9029 struct mlx5_ifc_delete_fte_in_bits {
9030 	u8         opcode[0x10];
9031 	u8         reserved_at_10[0x10];
9032 
9033 	u8         reserved_at_20[0x10];
9034 	u8         op_mod[0x10];
9035 
9036 	u8         other_vport[0x1];
9037 	u8         other_eswitch[0x1];
9038 	u8         reserved_at_42[0xe];
9039 	u8         vport_number[0x10];
9040 
9041 	u8         reserved_at_60[0x20];
9042 
9043 	u8         table_type[0x8];
9044 	u8         reserved_at_88[0x8];
9045 	u8         eswitch_owner_vhca_id[0x10];
9046 
9047 	u8         reserved_at_a0[0x8];
9048 	u8         table_id[0x18];
9049 
9050 	u8         reserved_at_c0[0x40];
9051 
9052 	u8         flow_index[0x20];
9053 
9054 	u8         reserved_at_120[0xe0];
9055 };
9056 
9057 struct mlx5_ifc_dealloc_xrcd_out_bits {
9058 	u8         status[0x8];
9059 	u8         reserved_at_8[0x18];
9060 
9061 	u8         syndrome[0x20];
9062 
9063 	u8         reserved_at_40[0x40];
9064 };
9065 
9066 struct mlx5_ifc_dealloc_xrcd_in_bits {
9067 	u8         opcode[0x10];
9068 	u8         uid[0x10];
9069 
9070 	u8         reserved_at_20[0x10];
9071 	u8         op_mod[0x10];
9072 
9073 	u8         reserved_at_40[0x8];
9074 	u8         xrcd[0x18];
9075 
9076 	u8         reserved_at_60[0x20];
9077 };
9078 
9079 struct mlx5_ifc_dealloc_uar_out_bits {
9080 	u8         status[0x8];
9081 	u8         reserved_at_8[0x18];
9082 
9083 	u8         syndrome[0x20];
9084 
9085 	u8         reserved_at_40[0x40];
9086 };
9087 
9088 struct mlx5_ifc_dealloc_uar_in_bits {
9089 	u8         opcode[0x10];
9090 	u8         uid[0x10];
9091 
9092 	u8         reserved_at_20[0x10];
9093 	u8         op_mod[0x10];
9094 
9095 	u8         reserved_at_40[0x8];
9096 	u8         uar[0x18];
9097 
9098 	u8         reserved_at_60[0x20];
9099 };
9100 
9101 struct mlx5_ifc_dealloc_transport_domain_out_bits {
9102 	u8         status[0x8];
9103 	u8         reserved_at_8[0x18];
9104 
9105 	u8         syndrome[0x20];
9106 
9107 	u8         reserved_at_40[0x40];
9108 };
9109 
9110 struct mlx5_ifc_dealloc_transport_domain_in_bits {
9111 	u8         opcode[0x10];
9112 	u8         uid[0x10];
9113 
9114 	u8         reserved_at_20[0x10];
9115 	u8         op_mod[0x10];
9116 
9117 	u8         reserved_at_40[0x8];
9118 	u8         transport_domain[0x18];
9119 
9120 	u8         reserved_at_60[0x20];
9121 };
9122 
9123 struct mlx5_ifc_dealloc_q_counter_out_bits {
9124 	u8         status[0x8];
9125 	u8         reserved_at_8[0x18];
9126 
9127 	u8         syndrome[0x20];
9128 
9129 	u8         reserved_at_40[0x40];
9130 };
9131 
9132 struct mlx5_ifc_dealloc_q_counter_in_bits {
9133 	u8         opcode[0x10];
9134 	u8         reserved_at_10[0x10];
9135 
9136 	u8         reserved_at_20[0x10];
9137 	u8         op_mod[0x10];
9138 
9139 	u8         reserved_at_40[0x18];
9140 	u8         counter_set_id[0x8];
9141 
9142 	u8         reserved_at_60[0x20];
9143 };
9144 
9145 struct mlx5_ifc_dealloc_pd_out_bits {
9146 	u8         status[0x8];
9147 	u8         reserved_at_8[0x18];
9148 
9149 	u8         syndrome[0x20];
9150 
9151 	u8         reserved_at_40[0x40];
9152 };
9153 
9154 struct mlx5_ifc_dealloc_pd_in_bits {
9155 	u8         opcode[0x10];
9156 	u8         uid[0x10];
9157 
9158 	u8         reserved_at_20[0x10];
9159 	u8         op_mod[0x10];
9160 
9161 	u8         reserved_at_40[0x8];
9162 	u8         pd[0x18];
9163 
9164 	u8         reserved_at_60[0x20];
9165 };
9166 
9167 struct mlx5_ifc_dealloc_flow_counter_out_bits {
9168 	u8         status[0x8];
9169 	u8         reserved_at_8[0x18];
9170 
9171 	u8         syndrome[0x20];
9172 
9173 	u8         reserved_at_40[0x40];
9174 };
9175 
9176 struct mlx5_ifc_dealloc_flow_counter_in_bits {
9177 	u8         opcode[0x10];
9178 	u8         reserved_at_10[0x10];
9179 
9180 	u8         reserved_at_20[0x10];
9181 	u8         op_mod[0x10];
9182 
9183 	u8         flow_counter_id[0x20];
9184 
9185 	u8         reserved_at_60[0x20];
9186 };
9187 
9188 struct mlx5_ifc_create_xrq_out_bits {
9189 	u8         status[0x8];
9190 	u8         reserved_at_8[0x18];
9191 
9192 	u8         syndrome[0x20];
9193 
9194 	u8         reserved_at_40[0x8];
9195 	u8         xrqn[0x18];
9196 
9197 	u8         reserved_at_60[0x20];
9198 };
9199 
9200 struct mlx5_ifc_create_xrq_in_bits {
9201 	u8         opcode[0x10];
9202 	u8         uid[0x10];
9203 
9204 	u8         reserved_at_20[0x10];
9205 	u8         op_mod[0x10];
9206 
9207 	u8         reserved_at_40[0x40];
9208 
9209 	struct mlx5_ifc_xrqc_bits xrq_context;
9210 };
9211 
9212 struct mlx5_ifc_create_xrc_srq_out_bits {
9213 	u8         status[0x8];
9214 	u8         reserved_at_8[0x18];
9215 
9216 	u8         syndrome[0x20];
9217 
9218 	u8         reserved_at_40[0x8];
9219 	u8         xrc_srqn[0x18];
9220 
9221 	u8         reserved_at_60[0x20];
9222 };
9223 
9224 struct mlx5_ifc_create_xrc_srq_in_bits {
9225 	u8         opcode[0x10];
9226 	u8         uid[0x10];
9227 
9228 	u8         reserved_at_20[0x10];
9229 	u8         op_mod[0x10];
9230 
9231 	u8         reserved_at_40[0x40];
9232 
9233 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
9234 
9235 	u8         reserved_at_280[0x60];
9236 
9237 	u8         xrc_srq_umem_valid[0x1];
9238 	u8         reserved_at_2e1[0x1f];
9239 
9240 	u8         reserved_at_300[0x580];
9241 
9242 	u8         pas[][0x40];
9243 };
9244 
9245 struct mlx5_ifc_create_tis_out_bits {
9246 	u8         status[0x8];
9247 	u8         reserved_at_8[0x18];
9248 
9249 	u8         syndrome[0x20];
9250 
9251 	u8         reserved_at_40[0x8];
9252 	u8         tisn[0x18];
9253 
9254 	u8         reserved_at_60[0x20];
9255 };
9256 
9257 struct mlx5_ifc_create_tis_in_bits {
9258 	u8         opcode[0x10];
9259 	u8         uid[0x10];
9260 
9261 	u8         reserved_at_20[0x10];
9262 	u8         op_mod[0x10];
9263 
9264 	u8         reserved_at_40[0xc0];
9265 
9266 	struct mlx5_ifc_tisc_bits ctx;
9267 };
9268 
9269 struct mlx5_ifc_create_tir_out_bits {
9270 	u8         status[0x8];
9271 	u8         icm_address_63_40[0x18];
9272 
9273 	u8         syndrome[0x20];
9274 
9275 	u8         icm_address_39_32[0x8];
9276 	u8         tirn[0x18];
9277 
9278 	u8         icm_address_31_0[0x20];
9279 };
9280 
9281 struct mlx5_ifc_create_tir_in_bits {
9282 	u8         opcode[0x10];
9283 	u8         uid[0x10];
9284 
9285 	u8         reserved_at_20[0x10];
9286 	u8         op_mod[0x10];
9287 
9288 	u8         reserved_at_40[0xc0];
9289 
9290 	struct mlx5_ifc_tirc_bits ctx;
9291 };
9292 
9293 struct mlx5_ifc_create_srq_out_bits {
9294 	u8         status[0x8];
9295 	u8         reserved_at_8[0x18];
9296 
9297 	u8         syndrome[0x20];
9298 
9299 	u8         reserved_at_40[0x8];
9300 	u8         srqn[0x18];
9301 
9302 	u8         reserved_at_60[0x20];
9303 };
9304 
9305 struct mlx5_ifc_create_srq_in_bits {
9306 	u8         opcode[0x10];
9307 	u8         uid[0x10];
9308 
9309 	u8         reserved_at_20[0x10];
9310 	u8         op_mod[0x10];
9311 
9312 	u8         reserved_at_40[0x40];
9313 
9314 	struct mlx5_ifc_srqc_bits srq_context_entry;
9315 
9316 	u8         reserved_at_280[0x600];
9317 
9318 	u8         pas[][0x40];
9319 };
9320 
9321 struct mlx5_ifc_create_sq_out_bits {
9322 	u8         status[0x8];
9323 	u8         reserved_at_8[0x18];
9324 
9325 	u8         syndrome[0x20];
9326 
9327 	u8         reserved_at_40[0x8];
9328 	u8         sqn[0x18];
9329 
9330 	u8         reserved_at_60[0x20];
9331 };
9332 
9333 struct mlx5_ifc_create_sq_in_bits {
9334 	u8         opcode[0x10];
9335 	u8         uid[0x10];
9336 
9337 	u8         reserved_at_20[0x10];
9338 	u8         op_mod[0x10];
9339 
9340 	u8         reserved_at_40[0xc0];
9341 
9342 	struct mlx5_ifc_sqc_bits ctx;
9343 };
9344 
9345 struct mlx5_ifc_create_scheduling_element_out_bits {
9346 	u8         status[0x8];
9347 	u8         reserved_at_8[0x18];
9348 
9349 	u8         syndrome[0x20];
9350 
9351 	u8         reserved_at_40[0x40];
9352 
9353 	u8         scheduling_element_id[0x20];
9354 
9355 	u8         reserved_at_a0[0x160];
9356 };
9357 
9358 struct mlx5_ifc_create_scheduling_element_in_bits {
9359 	u8         opcode[0x10];
9360 	u8         reserved_at_10[0x10];
9361 
9362 	u8         reserved_at_20[0x10];
9363 	u8         op_mod[0x10];
9364 
9365 	u8         scheduling_hierarchy[0x8];
9366 	u8         reserved_at_48[0x18];
9367 
9368 	u8         reserved_at_60[0xa0];
9369 
9370 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9371 
9372 	u8         reserved_at_300[0x100];
9373 };
9374 
9375 struct mlx5_ifc_create_rqt_out_bits {
9376 	u8         status[0x8];
9377 	u8         reserved_at_8[0x18];
9378 
9379 	u8         syndrome[0x20];
9380 
9381 	u8         reserved_at_40[0x8];
9382 	u8         rqtn[0x18];
9383 
9384 	u8         reserved_at_60[0x20];
9385 };
9386 
9387 struct mlx5_ifc_create_rqt_in_bits {
9388 	u8         opcode[0x10];
9389 	u8         uid[0x10];
9390 
9391 	u8         reserved_at_20[0x10];
9392 	u8         op_mod[0x10];
9393 
9394 	u8         reserved_at_40[0xc0];
9395 
9396 	struct mlx5_ifc_rqtc_bits rqt_context;
9397 };
9398 
9399 struct mlx5_ifc_create_rq_out_bits {
9400 	u8         status[0x8];
9401 	u8         reserved_at_8[0x18];
9402 
9403 	u8         syndrome[0x20];
9404 
9405 	u8         reserved_at_40[0x8];
9406 	u8         rqn[0x18];
9407 
9408 	u8         reserved_at_60[0x20];
9409 };
9410 
9411 struct mlx5_ifc_create_rq_in_bits {
9412 	u8         opcode[0x10];
9413 	u8         uid[0x10];
9414 
9415 	u8         reserved_at_20[0x10];
9416 	u8         op_mod[0x10];
9417 
9418 	u8         reserved_at_40[0xc0];
9419 
9420 	struct mlx5_ifc_rqc_bits ctx;
9421 };
9422 
9423 struct mlx5_ifc_create_rmp_out_bits {
9424 	u8         status[0x8];
9425 	u8         reserved_at_8[0x18];
9426 
9427 	u8         syndrome[0x20];
9428 
9429 	u8         reserved_at_40[0x8];
9430 	u8         rmpn[0x18];
9431 
9432 	u8         reserved_at_60[0x20];
9433 };
9434 
9435 struct mlx5_ifc_create_rmp_in_bits {
9436 	u8         opcode[0x10];
9437 	u8         uid[0x10];
9438 
9439 	u8         reserved_at_20[0x10];
9440 	u8         op_mod[0x10];
9441 
9442 	u8         reserved_at_40[0xc0];
9443 
9444 	struct mlx5_ifc_rmpc_bits ctx;
9445 };
9446 
9447 struct mlx5_ifc_create_qp_out_bits {
9448 	u8         status[0x8];
9449 	u8         reserved_at_8[0x18];
9450 
9451 	u8         syndrome[0x20];
9452 
9453 	u8         reserved_at_40[0x8];
9454 	u8         qpn[0x18];
9455 
9456 	u8         ece[0x20];
9457 };
9458 
9459 struct mlx5_ifc_create_qp_in_bits {
9460 	u8         opcode[0x10];
9461 	u8         uid[0x10];
9462 
9463 	u8         reserved_at_20[0x10];
9464 	u8         op_mod[0x10];
9465 
9466 	u8         qpc_ext[0x1];
9467 	u8         reserved_at_41[0x7];
9468 	u8         input_qpn[0x18];
9469 
9470 	u8         reserved_at_60[0x20];
9471 	u8         opt_param_mask[0x20];
9472 
9473 	u8         ece[0x20];
9474 
9475 	struct mlx5_ifc_qpc_bits qpc;
9476 
9477 	u8         wq_umem_offset[0x40];
9478 
9479 	u8         wq_umem_id[0x20];
9480 
9481 	u8         wq_umem_valid[0x1];
9482 	u8         reserved_at_861[0x1f];
9483 
9484 	u8         pas[][0x40];
9485 };
9486 
9487 struct mlx5_ifc_create_psv_out_bits {
9488 	u8         status[0x8];
9489 	u8         reserved_at_8[0x18];
9490 
9491 	u8         syndrome[0x20];
9492 
9493 	u8         reserved_at_40[0x40];
9494 
9495 	u8         reserved_at_80[0x8];
9496 	u8         psv0_index[0x18];
9497 
9498 	u8         reserved_at_a0[0x8];
9499 	u8         psv1_index[0x18];
9500 
9501 	u8         reserved_at_c0[0x8];
9502 	u8         psv2_index[0x18];
9503 
9504 	u8         reserved_at_e0[0x8];
9505 	u8         psv3_index[0x18];
9506 };
9507 
9508 struct mlx5_ifc_create_psv_in_bits {
9509 	u8         opcode[0x10];
9510 	u8         reserved_at_10[0x10];
9511 
9512 	u8         reserved_at_20[0x10];
9513 	u8         op_mod[0x10];
9514 
9515 	u8         num_psv[0x4];
9516 	u8         reserved_at_44[0x4];
9517 	u8         pd[0x18];
9518 
9519 	u8         reserved_at_60[0x20];
9520 };
9521 
9522 struct mlx5_ifc_create_mkey_out_bits {
9523 	u8         status[0x8];
9524 	u8         reserved_at_8[0x18];
9525 
9526 	u8         syndrome[0x20];
9527 
9528 	u8         reserved_at_40[0x8];
9529 	u8         mkey_index[0x18];
9530 
9531 	u8         reserved_at_60[0x20];
9532 };
9533 
9534 struct mlx5_ifc_create_mkey_in_bits {
9535 	u8         opcode[0x10];
9536 	u8         uid[0x10];
9537 
9538 	u8         reserved_at_20[0x10];
9539 	u8         op_mod[0x10];
9540 
9541 	u8         reserved_at_40[0x20];
9542 
9543 	u8         pg_access[0x1];
9544 	u8         mkey_umem_valid[0x1];
9545 	u8         data_direct[0x1];
9546 	u8         reserved_at_63[0x1d];
9547 
9548 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9549 
9550 	u8         reserved_at_280[0x80];
9551 
9552 	u8         translations_octword_actual_size[0x20];
9553 
9554 	u8         reserved_at_320[0x560];
9555 
9556 	u8         klm_pas_mtt[][0x20];
9557 };
9558 
9559 enum {
9560 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9561 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9562 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9563 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9564 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9565 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9566 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9567 };
9568 
9569 struct mlx5_ifc_create_flow_table_out_bits {
9570 	u8         status[0x8];
9571 	u8         icm_address_63_40[0x18];
9572 
9573 	u8         syndrome[0x20];
9574 
9575 	u8         icm_address_39_32[0x8];
9576 	u8         table_id[0x18];
9577 
9578 	u8         icm_address_31_0[0x20];
9579 };
9580 
9581 struct mlx5_ifc_create_flow_table_in_bits {
9582 	u8         opcode[0x10];
9583 	u8         uid[0x10];
9584 
9585 	u8         reserved_at_20[0x10];
9586 	u8         op_mod[0x10];
9587 
9588 	u8         other_vport[0x1];
9589 	u8         other_eswitch[0x1];
9590 	u8         reserved_at_42[0xe];
9591 	u8         vport_number[0x10];
9592 
9593 	u8         reserved_at_60[0x20];
9594 
9595 	u8         table_type[0x8];
9596 	u8         reserved_at_88[0x8];
9597 	u8         eswitch_owner_vhca_id[0x10];
9598 
9599 	u8         reserved_at_a0[0x20];
9600 
9601 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9602 };
9603 
9604 struct mlx5_ifc_create_flow_group_out_bits {
9605 	u8         status[0x8];
9606 	u8         reserved_at_8[0x18];
9607 
9608 	u8         syndrome[0x20];
9609 
9610 	u8         reserved_at_40[0x8];
9611 	u8         group_id[0x18];
9612 
9613 	u8         reserved_at_60[0x20];
9614 };
9615 
9616 enum {
9617 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9618 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9619 };
9620 
9621 enum {
9622 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9623 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9624 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9625 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9626 };
9627 
9628 struct mlx5_ifc_create_flow_group_in_bits {
9629 	u8         opcode[0x10];
9630 	u8         reserved_at_10[0x10];
9631 
9632 	u8         reserved_at_20[0x10];
9633 	u8         op_mod[0x10];
9634 
9635 	u8         other_vport[0x1];
9636 	u8         other_eswitch[0x1];
9637 	u8         reserved_at_42[0xe];
9638 	u8         vport_number[0x10];
9639 
9640 	u8         reserved_at_60[0x20];
9641 
9642 	u8         table_type[0x8];
9643 	u8         reserved_at_88[0x4];
9644 	u8         group_type[0x4];
9645 	u8         eswitch_owner_vhca_id[0x10];
9646 
9647 	u8         reserved_at_a0[0x8];
9648 	u8         table_id[0x18];
9649 
9650 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9651 
9652 	u8         reserved_at_c1[0x1f];
9653 
9654 	u8         start_flow_index[0x20];
9655 
9656 	u8         reserved_at_100[0x20];
9657 
9658 	u8         end_flow_index[0x20];
9659 
9660 	u8         reserved_at_140[0x10];
9661 	u8         match_definer_id[0x10];
9662 
9663 	u8         reserved_at_160[0x80];
9664 
9665 	u8         reserved_at_1e0[0x18];
9666 	u8         match_criteria_enable[0x8];
9667 
9668 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9669 
9670 	u8         reserved_at_1200[0xe00];
9671 };
9672 
9673 struct mlx5_ifc_create_eq_out_bits {
9674 	u8         status[0x8];
9675 	u8         reserved_at_8[0x18];
9676 
9677 	u8         syndrome[0x20];
9678 
9679 	u8         reserved_at_40[0x18];
9680 	u8         eq_number[0x8];
9681 
9682 	u8         reserved_at_60[0x20];
9683 };
9684 
9685 struct mlx5_ifc_create_eq_in_bits {
9686 	u8         opcode[0x10];
9687 	u8         uid[0x10];
9688 
9689 	u8         reserved_at_20[0x10];
9690 	u8         op_mod[0x10];
9691 
9692 	u8         reserved_at_40[0x40];
9693 
9694 	struct mlx5_ifc_eqc_bits eq_context_entry;
9695 
9696 	u8         reserved_at_280[0x40];
9697 
9698 	u8         event_bitmask[4][0x40];
9699 
9700 	u8         reserved_at_3c0[0x4c0];
9701 
9702 	u8         pas[][0x40];
9703 };
9704 
9705 struct mlx5_ifc_create_dct_out_bits {
9706 	u8         status[0x8];
9707 	u8         reserved_at_8[0x18];
9708 
9709 	u8         syndrome[0x20];
9710 
9711 	u8         reserved_at_40[0x8];
9712 	u8         dctn[0x18];
9713 
9714 	u8         ece[0x20];
9715 };
9716 
9717 struct mlx5_ifc_create_dct_in_bits {
9718 	u8         opcode[0x10];
9719 	u8         uid[0x10];
9720 
9721 	u8         reserved_at_20[0x10];
9722 	u8         op_mod[0x10];
9723 
9724 	u8         reserved_at_40[0x40];
9725 
9726 	struct mlx5_ifc_dctc_bits dct_context_entry;
9727 
9728 	u8         reserved_at_280[0x180];
9729 };
9730 
9731 struct mlx5_ifc_create_cq_out_bits {
9732 	u8         status[0x8];
9733 	u8         reserved_at_8[0x18];
9734 
9735 	u8         syndrome[0x20];
9736 
9737 	u8         reserved_at_40[0x8];
9738 	u8         cqn[0x18];
9739 
9740 	u8         reserved_at_60[0x20];
9741 };
9742 
9743 struct mlx5_ifc_create_cq_in_bits {
9744 	u8         opcode[0x10];
9745 	u8         uid[0x10];
9746 
9747 	u8         reserved_at_20[0x10];
9748 	u8         op_mod[0x10];
9749 
9750 	u8         reserved_at_40[0x40];
9751 
9752 	struct mlx5_ifc_cqc_bits cq_context;
9753 
9754 	u8         reserved_at_280[0x60];
9755 
9756 	u8         cq_umem_valid[0x1];
9757 	u8         reserved_at_2e1[0x59f];
9758 
9759 	u8         pas[][0x40];
9760 };
9761 
9762 struct mlx5_ifc_config_int_moderation_out_bits {
9763 	u8         status[0x8];
9764 	u8         reserved_at_8[0x18];
9765 
9766 	u8         syndrome[0x20];
9767 
9768 	u8         reserved_at_40[0x4];
9769 	u8         min_delay[0xc];
9770 	u8         int_vector[0x10];
9771 
9772 	u8         reserved_at_60[0x20];
9773 };
9774 
9775 enum {
9776 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9777 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9778 };
9779 
9780 struct mlx5_ifc_config_int_moderation_in_bits {
9781 	u8         opcode[0x10];
9782 	u8         reserved_at_10[0x10];
9783 
9784 	u8         reserved_at_20[0x10];
9785 	u8         op_mod[0x10];
9786 
9787 	u8         reserved_at_40[0x4];
9788 	u8         min_delay[0xc];
9789 	u8         int_vector[0x10];
9790 
9791 	u8         reserved_at_60[0x20];
9792 };
9793 
9794 struct mlx5_ifc_attach_to_mcg_out_bits {
9795 	u8         status[0x8];
9796 	u8         reserved_at_8[0x18];
9797 
9798 	u8         syndrome[0x20];
9799 
9800 	u8         reserved_at_40[0x40];
9801 };
9802 
9803 struct mlx5_ifc_attach_to_mcg_in_bits {
9804 	u8         opcode[0x10];
9805 	u8         uid[0x10];
9806 
9807 	u8         reserved_at_20[0x10];
9808 	u8         op_mod[0x10];
9809 
9810 	u8         reserved_at_40[0x8];
9811 	u8         qpn[0x18];
9812 
9813 	u8         reserved_at_60[0x20];
9814 
9815 	u8         multicast_gid[16][0x8];
9816 };
9817 
9818 struct mlx5_ifc_arm_xrq_out_bits {
9819 	u8         status[0x8];
9820 	u8         reserved_at_8[0x18];
9821 
9822 	u8         syndrome[0x20];
9823 
9824 	u8         reserved_at_40[0x40];
9825 };
9826 
9827 struct mlx5_ifc_arm_xrq_in_bits {
9828 	u8         opcode[0x10];
9829 	u8         reserved_at_10[0x10];
9830 
9831 	u8         reserved_at_20[0x10];
9832 	u8         op_mod[0x10];
9833 
9834 	u8         reserved_at_40[0x8];
9835 	u8         xrqn[0x18];
9836 
9837 	u8         reserved_at_60[0x10];
9838 	u8         lwm[0x10];
9839 };
9840 
9841 struct mlx5_ifc_arm_xrc_srq_out_bits {
9842 	u8         status[0x8];
9843 	u8         reserved_at_8[0x18];
9844 
9845 	u8         syndrome[0x20];
9846 
9847 	u8         reserved_at_40[0x40];
9848 };
9849 
9850 enum {
9851 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9852 };
9853 
9854 struct mlx5_ifc_arm_xrc_srq_in_bits {
9855 	u8         opcode[0x10];
9856 	u8         uid[0x10];
9857 
9858 	u8         reserved_at_20[0x10];
9859 	u8         op_mod[0x10];
9860 
9861 	u8         reserved_at_40[0x8];
9862 	u8         xrc_srqn[0x18];
9863 
9864 	u8         reserved_at_60[0x10];
9865 	u8         lwm[0x10];
9866 };
9867 
9868 struct mlx5_ifc_arm_rq_out_bits {
9869 	u8         status[0x8];
9870 	u8         reserved_at_8[0x18];
9871 
9872 	u8         syndrome[0x20];
9873 
9874 	u8         reserved_at_40[0x40];
9875 };
9876 
9877 enum {
9878 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9879 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9880 };
9881 
9882 struct mlx5_ifc_arm_rq_in_bits {
9883 	u8         opcode[0x10];
9884 	u8         uid[0x10];
9885 
9886 	u8         reserved_at_20[0x10];
9887 	u8         op_mod[0x10];
9888 
9889 	u8         reserved_at_40[0x8];
9890 	u8         srq_number[0x18];
9891 
9892 	u8         reserved_at_60[0x10];
9893 	u8         lwm[0x10];
9894 };
9895 
9896 struct mlx5_ifc_arm_dct_out_bits {
9897 	u8         status[0x8];
9898 	u8         reserved_at_8[0x18];
9899 
9900 	u8         syndrome[0x20];
9901 
9902 	u8         reserved_at_40[0x40];
9903 };
9904 
9905 struct mlx5_ifc_arm_dct_in_bits {
9906 	u8         opcode[0x10];
9907 	u8         reserved_at_10[0x10];
9908 
9909 	u8         reserved_at_20[0x10];
9910 	u8         op_mod[0x10];
9911 
9912 	u8         reserved_at_40[0x8];
9913 	u8         dct_number[0x18];
9914 
9915 	u8         reserved_at_60[0x20];
9916 };
9917 
9918 struct mlx5_ifc_alloc_xrcd_out_bits {
9919 	u8         status[0x8];
9920 	u8         reserved_at_8[0x18];
9921 
9922 	u8         syndrome[0x20];
9923 
9924 	u8         reserved_at_40[0x8];
9925 	u8         xrcd[0x18];
9926 
9927 	u8         reserved_at_60[0x20];
9928 };
9929 
9930 struct mlx5_ifc_alloc_xrcd_in_bits {
9931 	u8         opcode[0x10];
9932 	u8         uid[0x10];
9933 
9934 	u8         reserved_at_20[0x10];
9935 	u8         op_mod[0x10];
9936 
9937 	u8         reserved_at_40[0x40];
9938 };
9939 
9940 struct mlx5_ifc_alloc_uar_out_bits {
9941 	u8         status[0x8];
9942 	u8         reserved_at_8[0x18];
9943 
9944 	u8         syndrome[0x20];
9945 
9946 	u8         reserved_at_40[0x8];
9947 	u8         uar[0x18];
9948 
9949 	u8         reserved_at_60[0x20];
9950 };
9951 
9952 struct mlx5_ifc_alloc_uar_in_bits {
9953 	u8         opcode[0x10];
9954 	u8         uid[0x10];
9955 
9956 	u8         reserved_at_20[0x10];
9957 	u8         op_mod[0x10];
9958 
9959 	u8         reserved_at_40[0x40];
9960 };
9961 
9962 struct mlx5_ifc_alloc_transport_domain_out_bits {
9963 	u8         status[0x8];
9964 	u8         reserved_at_8[0x18];
9965 
9966 	u8         syndrome[0x20];
9967 
9968 	u8         reserved_at_40[0x8];
9969 	u8         transport_domain[0x18];
9970 
9971 	u8         reserved_at_60[0x20];
9972 };
9973 
9974 struct mlx5_ifc_alloc_transport_domain_in_bits {
9975 	u8         opcode[0x10];
9976 	u8         uid[0x10];
9977 
9978 	u8         reserved_at_20[0x10];
9979 	u8         op_mod[0x10];
9980 
9981 	u8         reserved_at_40[0x40];
9982 };
9983 
9984 struct mlx5_ifc_alloc_q_counter_out_bits {
9985 	u8         status[0x8];
9986 	u8         reserved_at_8[0x18];
9987 
9988 	u8         syndrome[0x20];
9989 
9990 	u8         reserved_at_40[0x18];
9991 	u8         counter_set_id[0x8];
9992 
9993 	u8         reserved_at_60[0x20];
9994 };
9995 
9996 struct mlx5_ifc_alloc_q_counter_in_bits {
9997 	u8         opcode[0x10];
9998 	u8         uid[0x10];
9999 
10000 	u8         reserved_at_20[0x10];
10001 	u8         op_mod[0x10];
10002 
10003 	u8         reserved_at_40[0x40];
10004 };
10005 
10006 struct mlx5_ifc_alloc_pd_out_bits {
10007 	u8         status[0x8];
10008 	u8         reserved_at_8[0x18];
10009 
10010 	u8         syndrome[0x20];
10011 
10012 	u8         reserved_at_40[0x8];
10013 	u8         pd[0x18];
10014 
10015 	u8         reserved_at_60[0x20];
10016 };
10017 
10018 struct mlx5_ifc_alloc_pd_in_bits {
10019 	u8         opcode[0x10];
10020 	u8         uid[0x10];
10021 
10022 	u8         reserved_at_20[0x10];
10023 	u8         op_mod[0x10];
10024 
10025 	u8         reserved_at_40[0x40];
10026 };
10027 
10028 struct mlx5_ifc_alloc_flow_counter_out_bits {
10029 	u8         status[0x8];
10030 	u8         reserved_at_8[0x18];
10031 
10032 	u8         syndrome[0x20];
10033 
10034 	u8         flow_counter_id[0x20];
10035 
10036 	u8         reserved_at_60[0x20];
10037 };
10038 
10039 struct mlx5_ifc_alloc_flow_counter_in_bits {
10040 	u8         opcode[0x10];
10041 	u8         reserved_at_10[0x10];
10042 
10043 	u8         reserved_at_20[0x10];
10044 	u8         op_mod[0x10];
10045 
10046 	u8         reserved_at_40[0x33];
10047 	u8         flow_counter_bulk_log_size[0x5];
10048 	u8         flow_counter_bulk[0x8];
10049 };
10050 
10051 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
10052 	u8         status[0x8];
10053 	u8         reserved_at_8[0x18];
10054 
10055 	u8         syndrome[0x20];
10056 
10057 	u8         reserved_at_40[0x40];
10058 };
10059 
10060 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
10061 	u8         opcode[0x10];
10062 	u8         reserved_at_10[0x10];
10063 
10064 	u8         reserved_at_20[0x10];
10065 	u8         op_mod[0x10];
10066 
10067 	u8         reserved_at_40[0x20];
10068 
10069 	u8         reserved_at_60[0x10];
10070 	u8         vxlan_udp_port[0x10];
10071 };
10072 
10073 struct mlx5_ifc_set_pp_rate_limit_out_bits {
10074 	u8         status[0x8];
10075 	u8         reserved_at_8[0x18];
10076 
10077 	u8         syndrome[0x20];
10078 
10079 	u8         reserved_at_40[0x40];
10080 };
10081 
10082 struct mlx5_ifc_set_pp_rate_limit_context_bits {
10083 	u8         rate_limit[0x20];
10084 
10085 	u8	   burst_upper_bound[0x20];
10086 
10087 	u8         reserved_at_40[0x10];
10088 	u8	   typical_packet_size[0x10];
10089 
10090 	u8         reserved_at_60[0x120];
10091 };
10092 
10093 struct mlx5_ifc_set_pp_rate_limit_in_bits {
10094 	u8         opcode[0x10];
10095 	u8         uid[0x10];
10096 
10097 	u8         reserved_at_20[0x10];
10098 	u8         op_mod[0x10];
10099 
10100 	u8         reserved_at_40[0x10];
10101 	u8         rate_limit_index[0x10];
10102 
10103 	u8         reserved_at_60[0x20];
10104 
10105 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
10106 };
10107 
10108 struct mlx5_ifc_access_register_out_bits {
10109 	u8         status[0x8];
10110 	u8         reserved_at_8[0x18];
10111 
10112 	u8         syndrome[0x20];
10113 
10114 	u8         reserved_at_40[0x40];
10115 
10116 	u8         register_data[][0x20];
10117 };
10118 
10119 enum {
10120 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
10121 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
10122 };
10123 
10124 struct mlx5_ifc_access_register_in_bits {
10125 	u8         opcode[0x10];
10126 	u8         reserved_at_10[0x10];
10127 
10128 	u8         reserved_at_20[0x10];
10129 	u8         op_mod[0x10];
10130 
10131 	u8         reserved_at_40[0x10];
10132 	u8         register_id[0x10];
10133 
10134 	u8         argument[0x20];
10135 
10136 	u8         register_data[][0x20];
10137 };
10138 
10139 struct mlx5_ifc_sltp_reg_bits {
10140 	u8         status[0x4];
10141 	u8         version[0x4];
10142 	u8         local_port[0x8];
10143 	u8         pnat[0x2];
10144 	u8         reserved_at_12[0x2];
10145 	u8         lane[0x4];
10146 	u8         reserved_at_18[0x8];
10147 
10148 	u8         reserved_at_20[0x20];
10149 
10150 	u8         reserved_at_40[0x7];
10151 	u8         polarity[0x1];
10152 	u8         ob_tap0[0x8];
10153 	u8         ob_tap1[0x8];
10154 	u8         ob_tap2[0x8];
10155 
10156 	u8         reserved_at_60[0xc];
10157 	u8         ob_preemp_mode[0x4];
10158 	u8         ob_reg[0x8];
10159 	u8         ob_bias[0x8];
10160 
10161 	u8         reserved_at_80[0x20];
10162 };
10163 
10164 struct mlx5_ifc_slrg_reg_bits {
10165 	u8         status[0x4];
10166 	u8         version[0x4];
10167 	u8         local_port[0x8];
10168 	u8         pnat[0x2];
10169 	u8         reserved_at_12[0x2];
10170 	u8         lane[0x4];
10171 	u8         reserved_at_18[0x8];
10172 
10173 	u8         time_to_link_up[0x10];
10174 	u8         reserved_at_30[0xc];
10175 	u8         grade_lane_speed[0x4];
10176 
10177 	u8         grade_version[0x8];
10178 	u8         grade[0x18];
10179 
10180 	u8         reserved_at_60[0x4];
10181 	u8         height_grade_type[0x4];
10182 	u8         height_grade[0x18];
10183 
10184 	u8         height_dz[0x10];
10185 	u8         height_dv[0x10];
10186 
10187 	u8         reserved_at_a0[0x10];
10188 	u8         height_sigma[0x10];
10189 
10190 	u8         reserved_at_c0[0x20];
10191 
10192 	u8         reserved_at_e0[0x4];
10193 	u8         phase_grade_type[0x4];
10194 	u8         phase_grade[0x18];
10195 
10196 	u8         reserved_at_100[0x8];
10197 	u8         phase_eo_pos[0x8];
10198 	u8         reserved_at_110[0x8];
10199 	u8         phase_eo_neg[0x8];
10200 
10201 	u8         ffe_set_tested[0x10];
10202 	u8         test_errors_per_lane[0x10];
10203 };
10204 
10205 struct mlx5_ifc_pvlc_reg_bits {
10206 	u8         reserved_at_0[0x8];
10207 	u8         local_port[0x8];
10208 	u8         reserved_at_10[0x10];
10209 
10210 	u8         reserved_at_20[0x1c];
10211 	u8         vl_hw_cap[0x4];
10212 
10213 	u8         reserved_at_40[0x1c];
10214 	u8         vl_admin[0x4];
10215 
10216 	u8         reserved_at_60[0x1c];
10217 	u8         vl_operational[0x4];
10218 };
10219 
10220 struct mlx5_ifc_pude_reg_bits {
10221 	u8         swid[0x8];
10222 	u8         local_port[0x8];
10223 	u8         reserved_at_10[0x4];
10224 	u8         admin_status[0x4];
10225 	u8         reserved_at_18[0x4];
10226 	u8         oper_status[0x4];
10227 
10228 	u8         reserved_at_20[0x60];
10229 };
10230 
10231 enum {
10232 	MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7,
10233 };
10234 
10235 struct mlx5_ifc_ptys_reg_bits {
10236 	u8         reserved_at_0[0x1];
10237 	u8         an_disable_admin[0x1];
10238 	u8         an_disable_cap[0x1];
10239 	u8         reserved_at_3[0x5];
10240 	u8         local_port[0x8];
10241 	u8         reserved_at_10[0x8];
10242 	u8         plane_ind[0x4];
10243 	u8         reserved_at_1c[0x1];
10244 	u8         proto_mask[0x3];
10245 
10246 	u8         an_status[0x4];
10247 	u8         reserved_at_24[0xc];
10248 	u8         data_rate_oper[0x10];
10249 
10250 	u8         ext_eth_proto_capability[0x20];
10251 
10252 	u8         eth_proto_capability[0x20];
10253 
10254 	u8         ib_link_width_capability[0x10];
10255 	u8         ib_proto_capability[0x10];
10256 
10257 	u8         ext_eth_proto_admin[0x20];
10258 
10259 	u8         eth_proto_admin[0x20];
10260 
10261 	u8         ib_link_width_admin[0x10];
10262 	u8         ib_proto_admin[0x10];
10263 
10264 	u8         ext_eth_proto_oper[0x20];
10265 
10266 	u8         eth_proto_oper[0x20];
10267 
10268 	u8         ib_link_width_oper[0x10];
10269 	u8         ib_proto_oper[0x10];
10270 
10271 	u8         reserved_at_160[0x8];
10272 	u8         lane_rate_oper[0x14];
10273 	u8         connector_type[0x4];
10274 
10275 	u8         eth_proto_lp_advertise[0x20];
10276 
10277 	u8         reserved_at_1a0[0x60];
10278 };
10279 
10280 struct mlx5_ifc_mlcr_reg_bits {
10281 	u8         reserved_at_0[0x8];
10282 	u8         local_port[0x8];
10283 	u8         reserved_at_10[0x20];
10284 
10285 	u8         beacon_duration[0x10];
10286 	u8         reserved_at_40[0x10];
10287 
10288 	u8         beacon_remain[0x10];
10289 };
10290 
10291 struct mlx5_ifc_ptas_reg_bits {
10292 	u8         reserved_at_0[0x20];
10293 
10294 	u8         algorithm_options[0x10];
10295 	u8         reserved_at_30[0x4];
10296 	u8         repetitions_mode[0x4];
10297 	u8         num_of_repetitions[0x8];
10298 
10299 	u8         grade_version[0x8];
10300 	u8         height_grade_type[0x4];
10301 	u8         phase_grade_type[0x4];
10302 	u8         height_grade_weight[0x8];
10303 	u8         phase_grade_weight[0x8];
10304 
10305 	u8         gisim_measure_bits[0x10];
10306 	u8         adaptive_tap_measure_bits[0x10];
10307 
10308 	u8         ber_bath_high_error_threshold[0x10];
10309 	u8         ber_bath_mid_error_threshold[0x10];
10310 
10311 	u8         ber_bath_low_error_threshold[0x10];
10312 	u8         one_ratio_high_threshold[0x10];
10313 
10314 	u8         one_ratio_high_mid_threshold[0x10];
10315 	u8         one_ratio_low_mid_threshold[0x10];
10316 
10317 	u8         one_ratio_low_threshold[0x10];
10318 	u8         ndeo_error_threshold[0x10];
10319 
10320 	u8         mixer_offset_step_size[0x10];
10321 	u8         reserved_at_110[0x8];
10322 	u8         mix90_phase_for_voltage_bath[0x8];
10323 
10324 	u8         mixer_offset_start[0x10];
10325 	u8         mixer_offset_end[0x10];
10326 
10327 	u8         reserved_at_140[0x15];
10328 	u8         ber_test_time[0xb];
10329 };
10330 
10331 struct mlx5_ifc_pspa_reg_bits {
10332 	u8         swid[0x8];
10333 	u8         local_port[0x8];
10334 	u8         sub_port[0x8];
10335 	u8         reserved_at_18[0x8];
10336 
10337 	u8         reserved_at_20[0x20];
10338 };
10339 
10340 struct mlx5_ifc_pqdr_reg_bits {
10341 	u8         reserved_at_0[0x8];
10342 	u8         local_port[0x8];
10343 	u8         reserved_at_10[0x5];
10344 	u8         prio[0x3];
10345 	u8         reserved_at_18[0x6];
10346 	u8         mode[0x2];
10347 
10348 	u8         reserved_at_20[0x20];
10349 
10350 	u8         reserved_at_40[0x10];
10351 	u8         min_threshold[0x10];
10352 
10353 	u8         reserved_at_60[0x10];
10354 	u8         max_threshold[0x10];
10355 
10356 	u8         reserved_at_80[0x10];
10357 	u8         mark_probability_denominator[0x10];
10358 
10359 	u8         reserved_at_a0[0x60];
10360 };
10361 
10362 struct mlx5_ifc_ppsc_reg_bits {
10363 	u8         reserved_at_0[0x8];
10364 	u8         local_port[0x8];
10365 	u8         reserved_at_10[0x10];
10366 
10367 	u8         reserved_at_20[0x60];
10368 
10369 	u8         reserved_at_80[0x1c];
10370 	u8         wrps_admin[0x4];
10371 
10372 	u8         reserved_at_a0[0x1c];
10373 	u8         wrps_status[0x4];
10374 
10375 	u8         reserved_at_c0[0x8];
10376 	u8         up_threshold[0x8];
10377 	u8         reserved_at_d0[0x8];
10378 	u8         down_threshold[0x8];
10379 
10380 	u8         reserved_at_e0[0x20];
10381 
10382 	u8         reserved_at_100[0x1c];
10383 	u8         srps_admin[0x4];
10384 
10385 	u8         reserved_at_120[0x1c];
10386 	u8         srps_status[0x4];
10387 
10388 	u8         reserved_at_140[0x40];
10389 };
10390 
10391 struct mlx5_ifc_pplr_reg_bits {
10392 	u8         reserved_at_0[0x8];
10393 	u8         local_port[0x8];
10394 	u8         reserved_at_10[0x10];
10395 
10396 	u8         reserved_at_20[0x8];
10397 	u8         lb_cap[0x8];
10398 	u8         reserved_at_30[0x8];
10399 	u8         lb_en[0x8];
10400 };
10401 
10402 struct mlx5_ifc_pplm_reg_bits {
10403 	u8         reserved_at_0[0x8];
10404 	u8	   local_port[0x8];
10405 	u8	   reserved_at_10[0x10];
10406 
10407 	u8	   reserved_at_20[0x20];
10408 
10409 	u8	   port_profile_mode[0x8];
10410 	u8	   static_port_profile[0x8];
10411 	u8	   active_port_profile[0x8];
10412 	u8	   reserved_at_58[0x8];
10413 
10414 	u8	   retransmission_active[0x8];
10415 	u8	   fec_mode_active[0x18];
10416 
10417 	u8	   rs_fec_correction_bypass_cap[0x4];
10418 	u8	   reserved_at_84[0x8];
10419 	u8	   fec_override_cap_56g[0x4];
10420 	u8	   fec_override_cap_100g[0x4];
10421 	u8	   fec_override_cap_50g[0x4];
10422 	u8	   fec_override_cap_25g[0x4];
10423 	u8	   fec_override_cap_10g_40g[0x4];
10424 
10425 	u8	   rs_fec_correction_bypass_admin[0x4];
10426 	u8	   reserved_at_a4[0x8];
10427 	u8	   fec_override_admin_56g[0x4];
10428 	u8	   fec_override_admin_100g[0x4];
10429 	u8	   fec_override_admin_50g[0x4];
10430 	u8	   fec_override_admin_25g[0x4];
10431 	u8	   fec_override_admin_10g_40g[0x4];
10432 
10433 	u8         fec_override_cap_400g_8x[0x10];
10434 	u8         fec_override_cap_200g_4x[0x10];
10435 
10436 	u8         fec_override_cap_100g_2x[0x10];
10437 	u8         fec_override_cap_50g_1x[0x10];
10438 
10439 	u8         fec_override_admin_400g_8x[0x10];
10440 	u8         fec_override_admin_200g_4x[0x10];
10441 
10442 	u8         fec_override_admin_100g_2x[0x10];
10443 	u8         fec_override_admin_50g_1x[0x10];
10444 
10445 	u8         fec_override_cap_800g_8x[0x10];
10446 	u8         fec_override_cap_400g_4x[0x10];
10447 
10448 	u8         fec_override_cap_200g_2x[0x10];
10449 	u8         fec_override_cap_100g_1x[0x10];
10450 
10451 	u8         reserved_at_180[0xa0];
10452 
10453 	u8         fec_override_admin_800g_8x[0x10];
10454 	u8         fec_override_admin_400g_4x[0x10];
10455 
10456 	u8         fec_override_admin_200g_2x[0x10];
10457 	u8         fec_override_admin_100g_1x[0x10];
10458 
10459 	u8         reserved_at_260[0x60];
10460 
10461 	u8         fec_override_cap_1600g_8x[0x10];
10462 	u8         fec_override_cap_800g_4x[0x10];
10463 
10464 	u8         fec_override_cap_400g_2x[0x10];
10465 	u8         fec_override_cap_200g_1x[0x10];
10466 
10467 	u8         fec_override_admin_1600g_8x[0x10];
10468 	u8         fec_override_admin_800g_4x[0x10];
10469 
10470 	u8         fec_override_admin_400g_2x[0x10];
10471 	u8         fec_override_admin_200g_1x[0x10];
10472 
10473 	u8         reserved_at_340[0x80];
10474 };
10475 
10476 struct mlx5_ifc_ppcnt_reg_bits {
10477 	u8         swid[0x8];
10478 	u8         local_port[0x8];
10479 	u8         pnat[0x2];
10480 	u8         reserved_at_12[0x8];
10481 	u8         grp[0x6];
10482 
10483 	u8         clr[0x1];
10484 	u8         reserved_at_21[0x13];
10485 	u8         plane_ind[0x4];
10486 	u8         reserved_at_38[0x3];
10487 	u8         prio_tc[0x5];
10488 
10489 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10490 };
10491 
10492 struct mlx5_ifc_mpein_reg_bits {
10493 	u8         reserved_at_0[0x2];
10494 	u8         depth[0x6];
10495 	u8         pcie_index[0x8];
10496 	u8         node[0x8];
10497 	u8         reserved_at_18[0x8];
10498 
10499 	u8         capability_mask[0x20];
10500 
10501 	u8         reserved_at_40[0x8];
10502 	u8         link_width_enabled[0x8];
10503 	u8         link_speed_enabled[0x10];
10504 
10505 	u8         lane0_physical_position[0x8];
10506 	u8         link_width_active[0x8];
10507 	u8         link_speed_active[0x10];
10508 
10509 	u8         num_of_pfs[0x10];
10510 	u8         num_of_vfs[0x10];
10511 
10512 	u8         bdf0[0x10];
10513 	u8         reserved_at_b0[0x10];
10514 
10515 	u8         max_read_request_size[0x4];
10516 	u8         max_payload_size[0x4];
10517 	u8         reserved_at_c8[0x5];
10518 	u8         pwr_status[0x3];
10519 	u8         port_type[0x4];
10520 	u8         reserved_at_d4[0xb];
10521 	u8         lane_reversal[0x1];
10522 
10523 	u8         reserved_at_e0[0x14];
10524 	u8         pci_power[0xc];
10525 
10526 	u8         reserved_at_100[0x20];
10527 
10528 	u8         device_status[0x10];
10529 	u8         port_state[0x8];
10530 	u8         reserved_at_138[0x8];
10531 
10532 	u8         reserved_at_140[0x10];
10533 	u8         receiver_detect_result[0x10];
10534 
10535 	u8         reserved_at_160[0x20];
10536 };
10537 
10538 struct mlx5_ifc_mpcnt_reg_bits {
10539 	u8         reserved_at_0[0x8];
10540 	u8         pcie_index[0x8];
10541 	u8         reserved_at_10[0xa];
10542 	u8         grp[0x6];
10543 
10544 	u8         clr[0x1];
10545 	u8         reserved_at_21[0x1f];
10546 
10547 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10548 };
10549 
10550 struct mlx5_ifc_ppad_reg_bits {
10551 	u8         reserved_at_0[0x3];
10552 	u8         single_mac[0x1];
10553 	u8         reserved_at_4[0x4];
10554 	u8         local_port[0x8];
10555 	u8         mac_47_32[0x10];
10556 
10557 	u8         mac_31_0[0x20];
10558 
10559 	u8         reserved_at_40[0x40];
10560 };
10561 
10562 struct mlx5_ifc_pmtu_reg_bits {
10563 	u8         reserved_at_0[0x8];
10564 	u8         local_port[0x8];
10565 	u8         reserved_at_10[0x10];
10566 
10567 	u8         max_mtu[0x10];
10568 	u8         reserved_at_30[0x10];
10569 
10570 	u8         admin_mtu[0x10];
10571 	u8         reserved_at_50[0x10];
10572 
10573 	u8         oper_mtu[0x10];
10574 	u8         reserved_at_70[0x10];
10575 };
10576 
10577 struct mlx5_ifc_pmpr_reg_bits {
10578 	u8         reserved_at_0[0x8];
10579 	u8         module[0x8];
10580 	u8         reserved_at_10[0x10];
10581 
10582 	u8         reserved_at_20[0x18];
10583 	u8         attenuation_5g[0x8];
10584 
10585 	u8         reserved_at_40[0x18];
10586 	u8         attenuation_7g[0x8];
10587 
10588 	u8         reserved_at_60[0x18];
10589 	u8         attenuation_12g[0x8];
10590 };
10591 
10592 struct mlx5_ifc_pmpe_reg_bits {
10593 	u8         reserved_at_0[0x8];
10594 	u8         module[0x8];
10595 	u8         reserved_at_10[0xc];
10596 	u8         module_status[0x4];
10597 
10598 	u8         reserved_at_20[0x60];
10599 };
10600 
10601 struct mlx5_ifc_pmpc_reg_bits {
10602 	u8         module_state_updated[32][0x8];
10603 };
10604 
10605 struct mlx5_ifc_pmlpn_reg_bits {
10606 	u8         reserved_at_0[0x4];
10607 	u8         mlpn_status[0x4];
10608 	u8         local_port[0x8];
10609 	u8         reserved_at_10[0x10];
10610 
10611 	u8         e[0x1];
10612 	u8         reserved_at_21[0x1f];
10613 };
10614 
10615 struct mlx5_ifc_pmlp_reg_bits {
10616 	u8         rxtx[0x1];
10617 	u8         reserved_at_1[0x7];
10618 	u8         local_port[0x8];
10619 	u8         reserved_at_10[0x8];
10620 	u8         width[0x8];
10621 
10622 	u8         lane0_module_mapping[0x20];
10623 
10624 	u8         lane1_module_mapping[0x20];
10625 
10626 	u8         lane2_module_mapping[0x20];
10627 
10628 	u8         lane3_module_mapping[0x20];
10629 
10630 	u8         reserved_at_a0[0x160];
10631 };
10632 
10633 struct mlx5_ifc_pmaos_reg_bits {
10634 	u8         reserved_at_0[0x8];
10635 	u8         module[0x8];
10636 	u8         reserved_at_10[0x4];
10637 	u8         admin_status[0x4];
10638 	u8         reserved_at_18[0x4];
10639 	u8         oper_status[0x4];
10640 
10641 	u8         ase[0x1];
10642 	u8         ee[0x1];
10643 	u8         reserved_at_22[0x1c];
10644 	u8         e[0x2];
10645 
10646 	u8         reserved_at_40[0x40];
10647 };
10648 
10649 struct mlx5_ifc_plpc_reg_bits {
10650 	u8         reserved_at_0[0x4];
10651 	u8         profile_id[0xc];
10652 	u8         reserved_at_10[0x4];
10653 	u8         proto_mask[0x4];
10654 	u8         reserved_at_18[0x8];
10655 
10656 	u8         reserved_at_20[0x10];
10657 	u8         lane_speed[0x10];
10658 
10659 	u8         reserved_at_40[0x17];
10660 	u8         lpbf[0x1];
10661 	u8         fec_mode_policy[0x8];
10662 
10663 	u8         retransmission_capability[0x8];
10664 	u8         fec_mode_capability[0x18];
10665 
10666 	u8         retransmission_support_admin[0x8];
10667 	u8         fec_mode_support_admin[0x18];
10668 
10669 	u8         retransmission_request_admin[0x8];
10670 	u8         fec_mode_request_admin[0x18];
10671 
10672 	u8         reserved_at_c0[0x80];
10673 };
10674 
10675 struct mlx5_ifc_plib_reg_bits {
10676 	u8         reserved_at_0[0x8];
10677 	u8         local_port[0x8];
10678 	u8         reserved_at_10[0x8];
10679 	u8         ib_port[0x8];
10680 
10681 	u8         reserved_at_20[0x60];
10682 };
10683 
10684 struct mlx5_ifc_plbf_reg_bits {
10685 	u8         reserved_at_0[0x8];
10686 	u8         local_port[0x8];
10687 	u8         reserved_at_10[0xd];
10688 	u8         lbf_mode[0x3];
10689 
10690 	u8         reserved_at_20[0x20];
10691 };
10692 
10693 struct mlx5_ifc_pipg_reg_bits {
10694 	u8         reserved_at_0[0x8];
10695 	u8         local_port[0x8];
10696 	u8         reserved_at_10[0x10];
10697 
10698 	u8         dic[0x1];
10699 	u8         reserved_at_21[0x19];
10700 	u8         ipg[0x4];
10701 	u8         reserved_at_3e[0x2];
10702 };
10703 
10704 struct mlx5_ifc_pifr_reg_bits {
10705 	u8         reserved_at_0[0x8];
10706 	u8         local_port[0x8];
10707 	u8         reserved_at_10[0x10];
10708 
10709 	u8         reserved_at_20[0xe0];
10710 
10711 	u8         port_filter[8][0x20];
10712 
10713 	u8         port_filter_update_en[8][0x20];
10714 };
10715 
10716 enum {
10717 	MLX5_BUF_OWNERSHIP_UNKNOWN	= 0x0,
10718 	MLX5_BUF_OWNERSHIP_FW_OWNED	= 0x1,
10719 	MLX5_BUF_OWNERSHIP_SW_OWNED	= 0x2,
10720 };
10721 
10722 struct mlx5_ifc_pfcc_reg_bits {
10723 	u8         reserved_at_0[0x4];
10724 	u8	   buf_ownership[0x2];
10725 	u8	   reserved_at_6[0x2];
10726 	u8         local_port[0x8];
10727 	u8         reserved_at_10[0xa];
10728 	u8	   cable_length_mask[0x1];
10729 	u8         ppan_mask_n[0x1];
10730 	u8         minor_stall_mask[0x1];
10731 	u8         critical_stall_mask[0x1];
10732 	u8         reserved_at_1e[0x2];
10733 
10734 	u8         ppan[0x4];
10735 	u8         reserved_at_24[0x4];
10736 	u8         prio_mask_tx[0x8];
10737 	u8         reserved_at_30[0x8];
10738 	u8         prio_mask_rx[0x8];
10739 
10740 	u8         pptx[0x1];
10741 	u8         aptx[0x1];
10742 	u8         pptx_mask_n[0x1];
10743 	u8         reserved_at_43[0x5];
10744 	u8         pfctx[0x8];
10745 	u8         reserved_at_50[0x10];
10746 
10747 	u8         pprx[0x1];
10748 	u8         aprx[0x1];
10749 	u8         pprx_mask_n[0x1];
10750 	u8         reserved_at_63[0x5];
10751 	u8         pfcrx[0x8];
10752 	u8         reserved_at_70[0x10];
10753 
10754 	u8         device_stall_minor_watermark[0x10];
10755 	u8         device_stall_critical_watermark[0x10];
10756 
10757 	u8	   reserved_at_a0[0x18];
10758 	u8	   cable_length[0x8];
10759 
10760 	u8         reserved_at_c0[0x40];
10761 };
10762 
10763 struct mlx5_ifc_pelc_reg_bits {
10764 	u8         op[0x4];
10765 	u8         reserved_at_4[0x4];
10766 	u8         local_port[0x8];
10767 	u8         reserved_at_10[0x10];
10768 
10769 	u8         op_admin[0x8];
10770 	u8         op_capability[0x8];
10771 	u8         op_request[0x8];
10772 	u8         op_active[0x8];
10773 
10774 	u8         admin[0x40];
10775 
10776 	u8         capability[0x40];
10777 
10778 	u8         request[0x40];
10779 
10780 	u8         active[0x40];
10781 
10782 	u8         reserved_at_140[0x80];
10783 };
10784 
10785 struct mlx5_ifc_peir_reg_bits {
10786 	u8         reserved_at_0[0x8];
10787 	u8         local_port[0x8];
10788 	u8         reserved_at_10[0x10];
10789 
10790 	u8         reserved_at_20[0xc];
10791 	u8         error_count[0x4];
10792 	u8         reserved_at_30[0x10];
10793 
10794 	u8         reserved_at_40[0xc];
10795 	u8         lane[0x4];
10796 	u8         reserved_at_50[0x8];
10797 	u8         error_type[0x8];
10798 };
10799 
10800 struct mlx5_ifc_mpegc_reg_bits {
10801 	u8         reserved_at_0[0x30];
10802 	u8         field_select[0x10];
10803 
10804 	u8         tx_overflow_sense[0x1];
10805 	u8         mark_cqe[0x1];
10806 	u8         mark_cnp[0x1];
10807 	u8         reserved_at_43[0x1b];
10808 	u8         tx_lossy_overflow_oper[0x2];
10809 
10810 	u8         reserved_at_60[0x100];
10811 };
10812 
10813 struct mlx5_ifc_mpir_reg_bits {
10814 	u8         sdm[0x1];
10815 	u8         reserved_at_1[0x1b];
10816 	u8         host_buses[0x4];
10817 
10818 	u8         reserved_at_20[0x20];
10819 
10820 	u8         local_port[0x8];
10821 	u8         reserved_at_28[0x18];
10822 
10823 	u8         reserved_at_60[0x20];
10824 };
10825 
10826 enum {
10827 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10828 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10829 };
10830 
10831 enum {
10832 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10833 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10834 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10835 };
10836 
10837 struct mlx5_ifc_mtutc_reg_bits {
10838 	u8         reserved_at_0[0x5];
10839 	u8         freq_adj_units[0x3];
10840 	u8         reserved_at_8[0x3];
10841 	u8         log_max_freq_adjustment[0x5];
10842 
10843 	u8         reserved_at_10[0xc];
10844 	u8         operation[0x4];
10845 
10846 	u8         freq_adjustment[0x20];
10847 
10848 	u8         reserved_at_40[0x40];
10849 
10850 	u8         utc_sec[0x20];
10851 
10852 	u8         reserved_at_a0[0x2];
10853 	u8         utc_nsec[0x1e];
10854 
10855 	u8         time_adjustment[0x20];
10856 };
10857 
10858 struct mlx5_ifc_pcam_enhanced_features_bits {
10859 	u8         reserved_at_0[0x10];
10860 	u8         ppcnt_recovery_counters[0x1];
10861 	u8         reserved_at_11[0x7];
10862 	u8	   cable_length[0x1];
10863 	u8	   reserved_at_19[0x4];
10864 	u8         fec_200G_per_lane_in_pplm[0x1];
10865 	u8         reserved_at_1e[0x2a];
10866 	u8         fec_100G_per_lane_in_pplm[0x1];
10867 	u8         reserved_at_49[0x2];
10868 	u8         shp_pbmc_pbsr_support[0x1];
10869 	u8         reserved_at_4c[0x7];
10870 	u8	   buffer_ownership[0x1];
10871 	u8	   resereved_at_54[0x14];
10872 	u8         fec_50G_per_lane_in_pplm[0x1];
10873 	u8         reserved_at_69[0x4];
10874 	u8         rx_icrc_encapsulated_counter[0x1];
10875 	u8	   reserved_at_6e[0x4];
10876 	u8         ptys_extended_ethernet[0x1];
10877 	u8	   reserved_at_73[0x3];
10878 	u8         pfcc_mask[0x1];
10879 	u8         reserved_at_77[0x3];
10880 	u8         per_lane_error_counters[0x1];
10881 	u8         rx_buffer_fullness_counters[0x1];
10882 	u8         ptys_connector_type[0x1];
10883 	u8         reserved_at_7d[0x1];
10884 	u8         ppcnt_discard_group[0x1];
10885 	u8         ppcnt_statistical_group[0x1];
10886 };
10887 
10888 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10889 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10890 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10891 
10892 	u8         port_access_reg_cap_mask_63[0x1];
10893 	u8         pphcr[0x1];
10894 	u8         port_access_reg_cap_mask_61_to_36[0x1a];
10895 	u8         pplm[0x1];
10896 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10897 
10898 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10899 	u8         pbmc[0x1];
10900 	u8         pptb[0x1];
10901 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10902 	u8         ppcnt[0x1];
10903 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10904 };
10905 
10906 struct mlx5_ifc_pcam_reg_bits {
10907 	u8         reserved_at_0[0x8];
10908 	u8         feature_group[0x8];
10909 	u8         reserved_at_10[0x8];
10910 	u8         access_reg_group[0x8];
10911 
10912 	u8         reserved_at_20[0x20];
10913 
10914 	union {
10915 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10916 		u8         reserved_at_0[0x80];
10917 	} port_access_reg_cap_mask;
10918 
10919 	u8         reserved_at_c0[0x80];
10920 
10921 	union {
10922 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10923 		u8         reserved_at_0[0x80];
10924 	} feature_cap_mask;
10925 
10926 	u8         reserved_at_1c0[0xc0];
10927 };
10928 
10929 struct mlx5_ifc_mcam_enhanced_features_bits {
10930 	u8         reserved_at_0[0x50];
10931 	u8         mtutc_freq_adj_units[0x1];
10932 	u8         mtutc_time_adjustment_extended_range[0x1];
10933 	u8         reserved_at_52[0xb];
10934 	u8         mcia_32dwords[0x1];
10935 	u8         out_pulse_duration_ns[0x1];
10936 	u8         npps_period[0x1];
10937 	u8         reserved_at_60[0xa];
10938 	u8         reset_state[0x1];
10939 	u8         ptpcyc2realtime_modify[0x1];
10940 	u8         reserved_at_6c[0x2];
10941 	u8         pci_status_and_power[0x1];
10942 	u8         reserved_at_6f[0x5];
10943 	u8         mark_tx_action_cnp[0x1];
10944 	u8         mark_tx_action_cqe[0x1];
10945 	u8         dynamic_tx_overflow[0x1];
10946 	u8         reserved_at_77[0x4];
10947 	u8         pcie_outbound_stalled[0x1];
10948 	u8         tx_overflow_buffer_pkt[0x1];
10949 	u8         mtpps_enh_out_per_adj[0x1];
10950 	u8         mtpps_fs[0x1];
10951 	u8         pcie_performance_group[0x1];
10952 };
10953 
10954 struct mlx5_ifc_mcam_access_reg_bits {
10955 	u8         reserved_at_0[0x1c];
10956 	u8         mcda[0x1];
10957 	u8         mcc[0x1];
10958 	u8         mcqi[0x1];
10959 	u8         mcqs[0x1];
10960 
10961 	u8         regs_95_to_90[0x6];
10962 	u8         mpir[0x1];
10963 	u8         regs_88_to_87[0x2];
10964 	u8         mpegc[0x1];
10965 	u8         mtutc[0x1];
10966 	u8         regs_84_to_68[0x11];
10967 	u8         tracer_registers[0x4];
10968 
10969 	u8         regs_63_to_46[0x12];
10970 	u8         mrtc[0x1];
10971 	u8         regs_44_to_41[0x4];
10972 	u8         mfrl[0x1];
10973 	u8         regs_39_to_32[0x8];
10974 
10975 	u8         regs_31_to_11[0x15];
10976 	u8         mtmp[0x1];
10977 	u8         regs_9_to_0[0xa];
10978 };
10979 
10980 struct mlx5_ifc_mcam_access_reg_bits1 {
10981 	u8         regs_127_to_96[0x20];
10982 
10983 	u8         regs_95_to_64[0x20];
10984 
10985 	u8         regs_63_to_32[0x20];
10986 
10987 	u8         regs_31_to_0[0x20];
10988 };
10989 
10990 struct mlx5_ifc_mcam_access_reg_bits2 {
10991 	u8         regs_127_to_99[0x1d];
10992 	u8         mirc[0x1];
10993 	u8         regs_97_to_96[0x2];
10994 
10995 	u8         regs_95_to_87[0x09];
10996 	u8         synce_registers[0x2];
10997 	u8         regs_84_to_64[0x15];
10998 
10999 	u8         regs_63_to_32[0x20];
11000 
11001 	u8         regs_31_to_0[0x20];
11002 };
11003 
11004 struct mlx5_ifc_mcam_access_reg_bits3 {
11005 	u8         regs_127_to_96[0x20];
11006 
11007 	u8         regs_95_to_64[0x20];
11008 
11009 	u8         regs_63_to_32[0x20];
11010 
11011 	u8         regs_31_to_3[0x1d];
11012 	u8         mrtcq[0x1];
11013 	u8         mtctr[0x1];
11014 	u8         mtptm[0x1];
11015 };
11016 
11017 struct mlx5_ifc_mcam_reg_bits {
11018 	u8         reserved_at_0[0x8];
11019 	u8         feature_group[0x8];
11020 	u8         reserved_at_10[0x8];
11021 	u8         access_reg_group[0x8];
11022 
11023 	u8         reserved_at_20[0x20];
11024 
11025 	union {
11026 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
11027 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
11028 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
11029 		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
11030 		u8         reserved_at_0[0x80];
11031 	} mng_access_reg_cap_mask;
11032 
11033 	u8         reserved_at_c0[0x80];
11034 
11035 	union {
11036 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
11037 		u8         reserved_at_0[0x80];
11038 	} mng_feature_cap_mask;
11039 
11040 	u8         reserved_at_1c0[0x80];
11041 };
11042 
11043 struct mlx5_ifc_qcam_access_reg_cap_mask {
11044 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
11045 	u8         qpdpm[0x1];
11046 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
11047 	u8         qdpm[0x1];
11048 	u8         qpts[0x1];
11049 	u8         qcap[0x1];
11050 	u8         qcam_access_reg_cap_mask_0[0x1];
11051 };
11052 
11053 struct mlx5_ifc_qcam_qos_feature_cap_mask {
11054 	u8         qcam_qos_feature_cap_mask_127_to_5[0x7B];
11055 	u8         qetcr_qshr_max_bw_val_msb[0x1];
11056 	u8         qcam_qos_feature_cap_mask_3_to_1[0x3];
11057 	u8         qpts_trust_both[0x1];
11058 };
11059 
11060 struct mlx5_ifc_qcam_reg_bits {
11061 	u8         reserved_at_0[0x8];
11062 	u8         feature_group[0x8];
11063 	u8         reserved_at_10[0x8];
11064 	u8         access_reg_group[0x8];
11065 	u8         reserved_at_20[0x20];
11066 
11067 	union {
11068 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
11069 		u8  reserved_at_0[0x80];
11070 	} qos_access_reg_cap_mask;
11071 
11072 	u8         reserved_at_c0[0x80];
11073 
11074 	union {
11075 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
11076 		u8  reserved_at_0[0x80];
11077 	} qos_feature_cap_mask;
11078 
11079 	u8         reserved_at_1c0[0x80];
11080 };
11081 
11082 struct mlx5_ifc_core_dump_reg_bits {
11083 	u8         reserved_at_0[0x18];
11084 	u8         core_dump_type[0x8];
11085 
11086 	u8         reserved_at_20[0x30];
11087 	u8         vhca_id[0x10];
11088 
11089 	u8         reserved_at_60[0x8];
11090 	u8         qpn[0x18];
11091 	u8         reserved_at_80[0x180];
11092 };
11093 
11094 struct mlx5_ifc_pcap_reg_bits {
11095 	u8         reserved_at_0[0x8];
11096 	u8         local_port[0x8];
11097 	u8         reserved_at_10[0x10];
11098 
11099 	u8         port_capability_mask[4][0x20];
11100 };
11101 
11102 struct mlx5_ifc_paos_reg_bits {
11103 	u8         swid[0x8];
11104 	u8         local_port[0x8];
11105 	u8         reserved_at_10[0x4];
11106 	u8         admin_status[0x4];
11107 	u8         reserved_at_18[0x4];
11108 	u8         oper_status[0x4];
11109 
11110 	u8         ase[0x1];
11111 	u8         ee[0x1];
11112 	u8         reserved_at_22[0x1c];
11113 	u8         e[0x2];
11114 
11115 	u8         reserved_at_40[0x40];
11116 };
11117 
11118 struct mlx5_ifc_pamp_reg_bits {
11119 	u8         reserved_at_0[0x8];
11120 	u8         opamp_group[0x8];
11121 	u8         reserved_at_10[0xc];
11122 	u8         opamp_group_type[0x4];
11123 
11124 	u8         start_index[0x10];
11125 	u8         reserved_at_30[0x4];
11126 	u8         num_of_indices[0xc];
11127 
11128 	u8         index_data[18][0x10];
11129 };
11130 
11131 struct mlx5_ifc_pcmr_reg_bits {
11132 	u8         reserved_at_0[0x8];
11133 	u8         local_port[0x8];
11134 	u8         reserved_at_10[0x10];
11135 
11136 	u8         entropy_force_cap[0x1];
11137 	u8         entropy_calc_cap[0x1];
11138 	u8         entropy_gre_calc_cap[0x1];
11139 	u8         reserved_at_23[0xf];
11140 	u8         rx_ts_over_crc_cap[0x1];
11141 	u8         reserved_at_33[0xb];
11142 	u8         fcs_cap[0x1];
11143 	u8         reserved_at_3f[0x1];
11144 
11145 	u8         entropy_force[0x1];
11146 	u8         entropy_calc[0x1];
11147 	u8         entropy_gre_calc[0x1];
11148 	u8         reserved_at_43[0xf];
11149 	u8         rx_ts_over_crc[0x1];
11150 	u8         reserved_at_53[0xb];
11151 	u8         fcs_chk[0x1];
11152 	u8         reserved_at_5f[0x1];
11153 };
11154 
11155 struct mlx5_ifc_lane_2_module_mapping_bits {
11156 	u8         reserved_at_0[0x4];
11157 	u8         rx_lane[0x4];
11158 	u8         reserved_at_8[0x4];
11159 	u8         tx_lane[0x4];
11160 	u8         reserved_at_10[0x8];
11161 	u8         module[0x8];
11162 };
11163 
11164 struct mlx5_ifc_bufferx_reg_bits {
11165 	u8         reserved_at_0[0x6];
11166 	u8         lossy[0x1];
11167 	u8         epsb[0x1];
11168 	u8         reserved_at_8[0x8];
11169 	u8         size[0x10];
11170 
11171 	u8         xoff_threshold[0x10];
11172 	u8         xon_threshold[0x10];
11173 };
11174 
11175 struct mlx5_ifc_set_node_in_bits {
11176 	u8         node_description[64][0x8];
11177 };
11178 
11179 struct mlx5_ifc_register_power_settings_bits {
11180 	u8         reserved_at_0[0x18];
11181 	u8         power_settings_level[0x8];
11182 
11183 	u8         reserved_at_20[0x60];
11184 };
11185 
11186 struct mlx5_ifc_register_host_endianness_bits {
11187 	u8         he[0x1];
11188 	u8         reserved_at_1[0x1f];
11189 
11190 	u8         reserved_at_20[0x60];
11191 };
11192 
11193 struct mlx5_ifc_umr_pointer_desc_argument_bits {
11194 	u8         reserved_at_0[0x20];
11195 
11196 	u8         mkey[0x20];
11197 
11198 	u8         addressh_63_32[0x20];
11199 
11200 	u8         addressl_31_0[0x20];
11201 };
11202 
11203 struct mlx5_ifc_ud_adrs_vector_bits {
11204 	u8         dc_key[0x40];
11205 
11206 	u8         ext[0x1];
11207 	u8         reserved_at_41[0x7];
11208 	u8         destination_qp_dct[0x18];
11209 
11210 	u8         static_rate[0x4];
11211 	u8         sl_eth_prio[0x4];
11212 	u8         fl[0x1];
11213 	u8         mlid[0x7];
11214 	u8         rlid_udp_sport[0x10];
11215 
11216 	u8         reserved_at_80[0x20];
11217 
11218 	u8         rmac_47_16[0x20];
11219 
11220 	u8         rmac_15_0[0x10];
11221 	u8         tclass[0x8];
11222 	u8         hop_limit[0x8];
11223 
11224 	u8         reserved_at_e0[0x1];
11225 	u8         grh[0x1];
11226 	u8         reserved_at_e2[0x2];
11227 	u8         src_addr_index[0x8];
11228 	u8         flow_label[0x14];
11229 
11230 	u8         rgid_rip[16][0x8];
11231 };
11232 
11233 struct mlx5_ifc_pages_req_event_bits {
11234 	u8         reserved_at_0[0x10];
11235 	u8         function_id[0x10];
11236 
11237 	u8         num_pages[0x20];
11238 
11239 	u8         reserved_at_40[0xa0];
11240 };
11241 
11242 struct mlx5_ifc_eqe_bits {
11243 	u8         reserved_at_0[0x8];
11244 	u8         event_type[0x8];
11245 	u8         reserved_at_10[0x8];
11246 	u8         event_sub_type[0x8];
11247 
11248 	u8         reserved_at_20[0xe0];
11249 
11250 	union mlx5_ifc_event_auto_bits event_data;
11251 
11252 	u8         reserved_at_1e0[0x10];
11253 	u8         signature[0x8];
11254 	u8         reserved_at_1f8[0x7];
11255 	u8         owner[0x1];
11256 };
11257 
11258 enum {
11259 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
11260 };
11261 
11262 struct mlx5_ifc_cmd_queue_entry_bits {
11263 	u8         type[0x8];
11264 	u8         reserved_at_8[0x18];
11265 
11266 	u8         input_length[0x20];
11267 
11268 	u8         input_mailbox_pointer_63_32[0x20];
11269 
11270 	u8         input_mailbox_pointer_31_9[0x17];
11271 	u8         reserved_at_77[0x9];
11272 
11273 	u8         command_input_inline_data[16][0x8];
11274 
11275 	u8         command_output_inline_data[16][0x8];
11276 
11277 	u8         output_mailbox_pointer_63_32[0x20];
11278 
11279 	u8         output_mailbox_pointer_31_9[0x17];
11280 	u8         reserved_at_1b7[0x9];
11281 
11282 	u8         output_length[0x20];
11283 
11284 	u8         token[0x8];
11285 	u8         signature[0x8];
11286 	u8         reserved_at_1f0[0x8];
11287 	u8         status[0x7];
11288 	u8         ownership[0x1];
11289 };
11290 
11291 struct mlx5_ifc_cmd_out_bits {
11292 	u8         status[0x8];
11293 	u8         reserved_at_8[0x18];
11294 
11295 	u8         syndrome[0x20];
11296 
11297 	u8         command_output[0x20];
11298 };
11299 
11300 struct mlx5_ifc_cmd_in_bits {
11301 	u8         opcode[0x10];
11302 	u8         reserved_at_10[0x10];
11303 
11304 	u8         reserved_at_20[0x10];
11305 	u8         op_mod[0x10];
11306 
11307 	u8         command[][0x20];
11308 };
11309 
11310 struct mlx5_ifc_cmd_if_box_bits {
11311 	u8         mailbox_data[512][0x8];
11312 
11313 	u8         reserved_at_1000[0x180];
11314 
11315 	u8         next_pointer_63_32[0x20];
11316 
11317 	u8         next_pointer_31_10[0x16];
11318 	u8         reserved_at_11b6[0xa];
11319 
11320 	u8         block_number[0x20];
11321 
11322 	u8         reserved_at_11e0[0x8];
11323 	u8         token[0x8];
11324 	u8         ctrl_signature[0x8];
11325 	u8         signature[0x8];
11326 };
11327 
11328 struct mlx5_ifc_mtt_bits {
11329 	u8         ptag_63_32[0x20];
11330 
11331 	u8         ptag_31_8[0x18];
11332 	u8         reserved_at_38[0x6];
11333 	u8         wr_en[0x1];
11334 	u8         rd_en[0x1];
11335 };
11336 
11337 struct mlx5_ifc_query_wol_rol_out_bits {
11338 	u8         status[0x8];
11339 	u8         reserved_at_8[0x18];
11340 
11341 	u8         syndrome[0x20];
11342 
11343 	u8         reserved_at_40[0x10];
11344 	u8         rol_mode[0x8];
11345 	u8         wol_mode[0x8];
11346 
11347 	u8         reserved_at_60[0x20];
11348 };
11349 
11350 struct mlx5_ifc_query_wol_rol_in_bits {
11351 	u8         opcode[0x10];
11352 	u8         reserved_at_10[0x10];
11353 
11354 	u8         reserved_at_20[0x10];
11355 	u8         op_mod[0x10];
11356 
11357 	u8         reserved_at_40[0x40];
11358 };
11359 
11360 struct mlx5_ifc_set_wol_rol_out_bits {
11361 	u8         status[0x8];
11362 	u8         reserved_at_8[0x18];
11363 
11364 	u8         syndrome[0x20];
11365 
11366 	u8         reserved_at_40[0x40];
11367 };
11368 
11369 struct mlx5_ifc_set_wol_rol_in_bits {
11370 	u8         opcode[0x10];
11371 	u8         reserved_at_10[0x10];
11372 
11373 	u8         reserved_at_20[0x10];
11374 	u8         op_mod[0x10];
11375 
11376 	u8         rol_mode_valid[0x1];
11377 	u8         wol_mode_valid[0x1];
11378 	u8         reserved_at_42[0xe];
11379 	u8         rol_mode[0x8];
11380 	u8         wol_mode[0x8];
11381 
11382 	u8         reserved_at_60[0x20];
11383 };
11384 
11385 enum {
11386 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11387 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11388 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11389 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11390 };
11391 
11392 enum {
11393 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11394 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11395 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11396 };
11397 
11398 enum {
11399 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11400 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11401 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11402 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11403 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11404 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11405 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11406 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11407 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11408 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11409 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11410 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11411 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR           = 0x13,
11412 };
11413 
11414 struct mlx5_ifc_initial_seg_bits {
11415 	u8         fw_rev_minor[0x10];
11416 	u8         fw_rev_major[0x10];
11417 
11418 	u8         cmd_interface_rev[0x10];
11419 	u8         fw_rev_subminor[0x10];
11420 
11421 	u8         reserved_at_40[0x40];
11422 
11423 	u8         cmdq_phy_addr_63_32[0x20];
11424 
11425 	u8         cmdq_phy_addr_31_12[0x14];
11426 	u8         reserved_at_b4[0x2];
11427 	u8         nic_interface[0x2];
11428 	u8         log_cmdq_size[0x4];
11429 	u8         log_cmdq_stride[0x4];
11430 
11431 	u8         command_doorbell_vector[0x20];
11432 
11433 	u8         reserved_at_e0[0xf00];
11434 
11435 	u8         initializing[0x1];
11436 	u8         reserved_at_fe1[0x4];
11437 	u8         nic_interface_supported[0x3];
11438 	u8         embedded_cpu[0x1];
11439 	u8         reserved_at_fe9[0x17];
11440 
11441 	struct mlx5_ifc_health_buffer_bits health_buffer;
11442 
11443 	u8         no_dram_nic_offset[0x20];
11444 
11445 	u8         reserved_at_1220[0x6e40];
11446 
11447 	u8         reserved_at_8060[0x1f];
11448 	u8         clear_int[0x1];
11449 
11450 	u8         health_syndrome[0x8];
11451 	u8         health_counter[0x18];
11452 
11453 	u8         reserved_at_80a0[0x17fc0];
11454 };
11455 
11456 struct mlx5_ifc_mtpps_reg_bits {
11457 	u8         reserved_at_0[0xc];
11458 	u8         cap_number_of_pps_pins[0x4];
11459 	u8         reserved_at_10[0x4];
11460 	u8         cap_max_num_of_pps_in_pins[0x4];
11461 	u8         reserved_at_18[0x4];
11462 	u8         cap_max_num_of_pps_out_pins[0x4];
11463 
11464 	u8         reserved_at_20[0x13];
11465 	u8         cap_log_min_npps_period[0x5];
11466 	u8         reserved_at_38[0x3];
11467 	u8         cap_log_min_out_pulse_duration_ns[0x5];
11468 
11469 	u8         reserved_at_40[0x4];
11470 	u8         cap_pin_3_mode[0x4];
11471 	u8         reserved_at_48[0x4];
11472 	u8         cap_pin_2_mode[0x4];
11473 	u8         reserved_at_50[0x4];
11474 	u8         cap_pin_1_mode[0x4];
11475 	u8         reserved_at_58[0x4];
11476 	u8         cap_pin_0_mode[0x4];
11477 
11478 	u8         reserved_at_60[0x4];
11479 	u8         cap_pin_7_mode[0x4];
11480 	u8         reserved_at_68[0x4];
11481 	u8         cap_pin_6_mode[0x4];
11482 	u8         reserved_at_70[0x4];
11483 	u8         cap_pin_5_mode[0x4];
11484 	u8         reserved_at_78[0x4];
11485 	u8         cap_pin_4_mode[0x4];
11486 
11487 	u8         field_select[0x20];
11488 	u8         reserved_at_a0[0x20];
11489 
11490 	u8         npps_period[0x40];
11491 
11492 	u8         enable[0x1];
11493 	u8         reserved_at_101[0xb];
11494 	u8         pattern[0x4];
11495 	u8         reserved_at_110[0x4];
11496 	u8         pin_mode[0x4];
11497 	u8         pin[0x8];
11498 
11499 	u8         reserved_at_120[0x2];
11500 	u8         out_pulse_duration_ns[0x1e];
11501 
11502 	u8         time_stamp[0x40];
11503 
11504 	u8         out_pulse_duration[0x10];
11505 	u8         out_periodic_adjustment[0x10];
11506 	u8         enhanced_out_periodic_adjustment[0x20];
11507 
11508 	u8         reserved_at_1c0[0x20];
11509 };
11510 
11511 struct mlx5_ifc_mtppse_reg_bits {
11512 	u8         reserved_at_0[0x18];
11513 	u8         pin[0x8];
11514 	u8         event_arm[0x1];
11515 	u8         reserved_at_21[0x1b];
11516 	u8         event_generation_mode[0x4];
11517 	u8         reserved_at_40[0x40];
11518 };
11519 
11520 struct mlx5_ifc_mcqs_reg_bits {
11521 	u8         last_index_flag[0x1];
11522 	u8         reserved_at_1[0x7];
11523 	u8         fw_device[0x8];
11524 	u8         component_index[0x10];
11525 
11526 	u8         reserved_at_20[0x10];
11527 	u8         identifier[0x10];
11528 
11529 	u8         reserved_at_40[0x17];
11530 	u8         component_status[0x5];
11531 	u8         component_update_state[0x4];
11532 
11533 	u8         last_update_state_changer_type[0x4];
11534 	u8         last_update_state_changer_host_id[0x4];
11535 	u8         reserved_at_68[0x18];
11536 };
11537 
11538 struct mlx5_ifc_mcqi_cap_bits {
11539 	u8         supported_info_bitmask[0x20];
11540 
11541 	u8         component_size[0x20];
11542 
11543 	u8         max_component_size[0x20];
11544 
11545 	u8         log_mcda_word_size[0x4];
11546 	u8         reserved_at_64[0xc];
11547 	u8         mcda_max_write_size[0x10];
11548 
11549 	u8         rd_en[0x1];
11550 	u8         reserved_at_81[0x1];
11551 	u8         match_chip_id[0x1];
11552 	u8         match_psid[0x1];
11553 	u8         check_user_timestamp[0x1];
11554 	u8         match_base_guid_mac[0x1];
11555 	u8         reserved_at_86[0x1a];
11556 };
11557 
11558 struct mlx5_ifc_mcqi_version_bits {
11559 	u8         reserved_at_0[0x2];
11560 	u8         build_time_valid[0x1];
11561 	u8         user_defined_time_valid[0x1];
11562 	u8         reserved_at_4[0x14];
11563 	u8         version_string_length[0x8];
11564 
11565 	u8         version[0x20];
11566 
11567 	u8         build_time[0x40];
11568 
11569 	u8         user_defined_time[0x40];
11570 
11571 	u8         build_tool_version[0x20];
11572 
11573 	u8         reserved_at_e0[0x20];
11574 
11575 	u8         version_string[92][0x8];
11576 };
11577 
11578 struct mlx5_ifc_mcqi_activation_method_bits {
11579 	u8         pending_server_ac_power_cycle[0x1];
11580 	u8         pending_server_dc_power_cycle[0x1];
11581 	u8         pending_server_reboot[0x1];
11582 	u8         pending_fw_reset[0x1];
11583 	u8         auto_activate[0x1];
11584 	u8         all_hosts_sync[0x1];
11585 	u8         device_hw_reset[0x1];
11586 	u8         reserved_at_7[0x19];
11587 };
11588 
11589 union mlx5_ifc_mcqi_reg_data_bits {
11590 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11591 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11592 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11593 };
11594 
11595 struct mlx5_ifc_mcqi_reg_bits {
11596 	u8         read_pending_component[0x1];
11597 	u8         reserved_at_1[0xf];
11598 	u8         component_index[0x10];
11599 
11600 	u8         reserved_at_20[0x20];
11601 
11602 	u8         reserved_at_40[0x1b];
11603 	u8         info_type[0x5];
11604 
11605 	u8         info_size[0x20];
11606 
11607 	u8         offset[0x20];
11608 
11609 	u8         reserved_at_a0[0x10];
11610 	u8         data_size[0x10];
11611 
11612 	union mlx5_ifc_mcqi_reg_data_bits data[];
11613 };
11614 
11615 struct mlx5_ifc_mcc_reg_bits {
11616 	u8         reserved_at_0[0x4];
11617 	u8         time_elapsed_since_last_cmd[0xc];
11618 	u8         reserved_at_10[0x8];
11619 	u8         instruction[0x8];
11620 
11621 	u8         reserved_at_20[0x10];
11622 	u8         component_index[0x10];
11623 
11624 	u8         reserved_at_40[0x8];
11625 	u8         update_handle[0x18];
11626 
11627 	u8         handle_owner_type[0x4];
11628 	u8         handle_owner_host_id[0x4];
11629 	u8         reserved_at_68[0x1];
11630 	u8         control_progress[0x7];
11631 	u8         error_code[0x8];
11632 	u8         reserved_at_78[0x4];
11633 	u8         control_state[0x4];
11634 
11635 	u8         component_size[0x20];
11636 
11637 	u8         reserved_at_a0[0x60];
11638 };
11639 
11640 struct mlx5_ifc_mcda_reg_bits {
11641 	u8         reserved_at_0[0x8];
11642 	u8         update_handle[0x18];
11643 
11644 	u8         offset[0x20];
11645 
11646 	u8         reserved_at_40[0x10];
11647 	u8         size[0x10];
11648 
11649 	u8         reserved_at_60[0x20];
11650 
11651 	u8         data[][0x20];
11652 };
11653 
11654 enum {
11655 	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11656 	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11657 };
11658 
11659 enum {
11660 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11661 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11662 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11663 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11664 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11665 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11666 };
11667 
11668 enum {
11669 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11670 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11671 };
11672 
11673 enum {
11674 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11675 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11676 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11677 };
11678 
11679 struct mlx5_ifc_mfrl_reg_bits {
11680 	u8         reserved_at_0[0x20];
11681 
11682 	u8         reserved_at_20[0x2];
11683 	u8         pci_sync_for_fw_update_start[0x1];
11684 	u8         pci_sync_for_fw_update_resp[0x2];
11685 	u8         rst_type_sel[0x3];
11686 	u8         pci_reset_req_method[0x3];
11687 	u8         reserved_at_2b[0x1];
11688 	u8         reset_state[0x4];
11689 	u8         reset_type[0x8];
11690 	u8         reset_level[0x8];
11691 };
11692 
11693 struct mlx5_ifc_mirc_reg_bits {
11694 	u8         reserved_at_0[0x18];
11695 	u8         status_code[0x8];
11696 
11697 	u8         reserved_at_20[0x20];
11698 };
11699 
11700 struct mlx5_ifc_pddr_monitor_opcode_bits {
11701 	u8         reserved_at_0[0x10];
11702 	u8         monitor_opcode[0x10];
11703 };
11704 
11705 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11706 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11707 	u8         reserved_at_0[0x20];
11708 };
11709 
11710 enum {
11711 	/* Monitor opcodes */
11712 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11713 };
11714 
11715 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11716 	u8         reserved_at_0[0x10];
11717 	u8         group_opcode[0x10];
11718 
11719 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11720 
11721 	u8         reserved_at_40[0x20];
11722 
11723 	u8         status_message[59][0x20];
11724 };
11725 
11726 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11727 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11728 	u8         reserved_at_0[0x7c0];
11729 };
11730 
11731 enum {
11732 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11733 };
11734 
11735 struct mlx5_ifc_pddr_reg_bits {
11736 	u8         reserved_at_0[0x8];
11737 	u8         local_port[0x8];
11738 	u8         pnat[0x2];
11739 	u8         reserved_at_12[0xe];
11740 
11741 	u8         reserved_at_20[0x18];
11742 	u8         page_select[0x8];
11743 
11744 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11745 };
11746 
11747 struct mlx5_ifc_mrtc_reg_bits {
11748 	u8         time_synced[0x1];
11749 	u8         reserved_at_1[0x1f];
11750 
11751 	u8         reserved_at_20[0x20];
11752 
11753 	u8         time_h[0x20];
11754 
11755 	u8         time_l[0x20];
11756 };
11757 
11758 struct mlx5_ifc_mtcap_reg_bits {
11759 	u8         reserved_at_0[0x19];
11760 	u8         sensor_count[0x7];
11761 
11762 	u8         reserved_at_20[0x20];
11763 
11764 	u8         sensor_map[0x40];
11765 };
11766 
11767 struct mlx5_ifc_mtmp_reg_bits {
11768 	u8         reserved_at_0[0x14];
11769 	u8         sensor_index[0xc];
11770 
11771 	u8         reserved_at_20[0x10];
11772 	u8         temperature[0x10];
11773 
11774 	u8         mte[0x1];
11775 	u8         mtr[0x1];
11776 	u8         reserved_at_42[0xe];
11777 	u8         max_temperature[0x10];
11778 
11779 	u8         tee[0x2];
11780 	u8         reserved_at_62[0xe];
11781 	u8         temp_threshold_hi[0x10];
11782 
11783 	u8         reserved_at_80[0x10];
11784 	u8         temp_threshold_lo[0x10];
11785 
11786 	u8         reserved_at_a0[0x20];
11787 
11788 	u8         sensor_name_hi[0x20];
11789 	u8         sensor_name_lo[0x20];
11790 };
11791 
11792 struct mlx5_ifc_mtptm_reg_bits {
11793 	u8         reserved_at_0[0x10];
11794 	u8         psta[0x1];
11795 	u8         reserved_at_11[0xf];
11796 
11797 	u8         reserved_at_20[0x60];
11798 };
11799 
11800 enum {
11801 	MLX5_MTCTR_REQUEST_NOP = 0x0,
11802 	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11803 	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11804 	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11805 };
11806 
11807 struct mlx5_ifc_mtctr_reg_bits {
11808 	u8         first_clock_timestamp_request[0x8];
11809 	u8         second_clock_timestamp_request[0x8];
11810 	u8         reserved_at_10[0x10];
11811 
11812 	u8         first_clock_valid[0x1];
11813 	u8         second_clock_valid[0x1];
11814 	u8         reserved_at_22[0x1e];
11815 
11816 	u8         first_clock_timestamp[0x40];
11817 	u8         second_clock_timestamp[0x40];
11818 };
11819 
11820 struct mlx5_ifc_bin_range_layout_bits {
11821 	u8         reserved_at_0[0xa];
11822 	u8         high_val[0x6];
11823 	u8         reserved_at_10[0xa];
11824 	u8         low_val[0x6];
11825 };
11826 
11827 struct mlx5_ifc_pphcr_reg_bits {
11828 	u8         active_hist_type[0x4];
11829 	u8         reserved_at_4[0x4];
11830 	u8         local_port[0x8];
11831 	u8         reserved_at_10[0x10];
11832 
11833 	u8         reserved_at_20[0x8];
11834 	u8         num_of_bins[0x8];
11835 	u8         reserved_at_30[0x10];
11836 
11837 	u8         reserved_at_40[0x40];
11838 
11839 	struct mlx5_ifc_bin_range_layout_bits bin_range[16];
11840 };
11841 
11842 union mlx5_ifc_ports_control_registers_document_bits {
11843 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11844 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11845 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11846 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11847 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11848 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11849 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11850 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11851 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11852 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11853 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11854 	struct mlx5_ifc_paos_reg_bits paos_reg;
11855 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11856 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11857 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11858 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11859 	struct mlx5_ifc_peir_reg_bits peir_reg;
11860 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11861 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11862 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11863 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11864 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11865 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11866 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11867 	struct mlx5_ifc_plib_reg_bits plib_reg;
11868 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11869 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11870 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11871 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11872 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11873 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11874 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11875 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11876 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11877 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11878 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11879 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11880 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11881 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11882 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11883 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11884 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11885 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11886 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11887 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11888 	struct mlx5_ifc_pude_reg_bits pude_reg;
11889 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11890 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11891 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11892 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11893 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11894 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11895 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11896 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11897 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11898 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11899 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11900 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11901 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11902 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11903 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11904 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11905 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11906 	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11907 	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11908 	struct mlx5_ifc_pphcr_reg_bits pphcr_reg;
11909 	u8         reserved_at_0[0x60e0];
11910 };
11911 
11912 union mlx5_ifc_debug_enhancements_document_bits {
11913 	struct mlx5_ifc_health_buffer_bits health_buffer;
11914 	u8         reserved_at_0[0x200];
11915 };
11916 
11917 union mlx5_ifc_uplink_pci_interface_document_bits {
11918 	struct mlx5_ifc_initial_seg_bits initial_seg;
11919 	u8         reserved_at_0[0x20060];
11920 };
11921 
11922 struct mlx5_ifc_set_flow_table_root_out_bits {
11923 	u8         status[0x8];
11924 	u8         reserved_at_8[0x18];
11925 
11926 	u8         syndrome[0x20];
11927 
11928 	u8         reserved_at_40[0x40];
11929 };
11930 
11931 struct mlx5_ifc_set_flow_table_root_in_bits {
11932 	u8         opcode[0x10];
11933 	u8         reserved_at_10[0x10];
11934 
11935 	u8         reserved_at_20[0x10];
11936 	u8         op_mod[0x10];
11937 
11938 	u8         other_vport[0x1];
11939 	u8         other_eswitch[0x1];
11940 	u8         reserved_at_42[0xe];
11941 	u8         vport_number[0x10];
11942 
11943 	u8         reserved_at_60[0x10];
11944 	u8         eswitch_owner_vhca_id[0x10];
11945 
11946 	u8         table_type[0x8];
11947 	u8         reserved_at_88[0x7];
11948 	u8         table_of_other_vport[0x1];
11949 	u8         table_vport_number[0x10];
11950 
11951 	u8         reserved_at_a0[0x8];
11952 	u8         table_id[0x18];
11953 
11954 	u8         reserved_at_c0[0x8];
11955 	u8         underlay_qpn[0x18];
11956 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11957 	u8         reserved_at_e1[0xf];
11958 	u8         table_eswitch_owner_vhca_id[0x10];
11959 	u8         reserved_at_100[0x100];
11960 };
11961 
11962 enum {
11963 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11964 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11965 };
11966 
11967 struct mlx5_ifc_modify_flow_table_out_bits {
11968 	u8         status[0x8];
11969 	u8         reserved_at_8[0x18];
11970 
11971 	u8         syndrome[0x20];
11972 
11973 	u8         reserved_at_40[0x40];
11974 };
11975 
11976 struct mlx5_ifc_modify_flow_table_in_bits {
11977 	u8         opcode[0x10];
11978 	u8         reserved_at_10[0x10];
11979 
11980 	u8         reserved_at_20[0x10];
11981 	u8         op_mod[0x10];
11982 
11983 	u8         other_vport[0x1];
11984 	u8         other_eswitch[0x1];
11985 	u8         reserved_at_42[0xe];
11986 	u8         vport_number[0x10];
11987 
11988 	u8         reserved_at_60[0x10];
11989 	u8         modify_field_select[0x10];
11990 
11991 	u8         table_type[0x8];
11992 	u8         reserved_at_88[0x8];
11993 	u8         eswitch_owner_vhca_id[0x10];
11994 
11995 	u8         reserved_at_a0[0x8];
11996 	u8         table_id[0x18];
11997 
11998 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11999 };
12000 
12001 struct mlx5_ifc_ets_tcn_config_reg_bits {
12002 	u8         g[0x1];
12003 	u8         b[0x1];
12004 	u8         r[0x1];
12005 	u8         reserved_at_3[0x9];
12006 	u8         group[0x4];
12007 	u8         reserved_at_10[0x9];
12008 	u8         bw_allocation[0x7];
12009 
12010 	u8         reserved_at_20[0xc];
12011 	u8         max_bw_units[0x4];
12012 	u8         max_bw_value[0x10];
12013 };
12014 
12015 struct mlx5_ifc_ets_global_config_reg_bits {
12016 	u8         reserved_at_0[0x2];
12017 	u8         r[0x1];
12018 	u8         reserved_at_3[0x1d];
12019 
12020 	u8         reserved_at_20[0xc];
12021 	u8         max_bw_units[0x4];
12022 	u8         reserved_at_30[0x8];
12023 	u8         max_bw_value[0x8];
12024 };
12025 
12026 struct mlx5_ifc_qetc_reg_bits {
12027 	u8                                         reserved_at_0[0x8];
12028 	u8                                         port_number[0x8];
12029 	u8                                         reserved_at_10[0x30];
12030 
12031 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
12032 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
12033 };
12034 
12035 struct mlx5_ifc_qpdpm_dscp_reg_bits {
12036 	u8         e[0x1];
12037 	u8         reserved_at_01[0x0b];
12038 	u8         prio[0x04];
12039 };
12040 
12041 struct mlx5_ifc_qpdpm_reg_bits {
12042 	u8                                     reserved_at_0[0x8];
12043 	u8                                     local_port[0x8];
12044 	u8                                     reserved_at_10[0x10];
12045 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
12046 };
12047 
12048 struct mlx5_ifc_qpts_reg_bits {
12049 	u8         reserved_at_0[0x8];
12050 	u8         local_port[0x8];
12051 	u8         reserved_at_10[0x2d];
12052 	u8         trust_state[0x3];
12053 };
12054 
12055 struct mlx5_ifc_pptb_reg_bits {
12056 	u8         reserved_at_0[0x2];
12057 	u8         mm[0x2];
12058 	u8         reserved_at_4[0x4];
12059 	u8         local_port[0x8];
12060 	u8         reserved_at_10[0x6];
12061 	u8         cm[0x1];
12062 	u8         um[0x1];
12063 	u8         pm[0x8];
12064 
12065 	u8         prio_x_buff[0x20];
12066 
12067 	u8         pm_msb[0x8];
12068 	u8         reserved_at_48[0x10];
12069 	u8         ctrl_buff[0x4];
12070 	u8         untagged_buff[0x4];
12071 };
12072 
12073 struct mlx5_ifc_sbcam_reg_bits {
12074 	u8         reserved_at_0[0x8];
12075 	u8         feature_group[0x8];
12076 	u8         reserved_at_10[0x8];
12077 	u8         access_reg_group[0x8];
12078 
12079 	u8         reserved_at_20[0x20];
12080 
12081 	u8         sb_access_reg_cap_mask[4][0x20];
12082 
12083 	u8         reserved_at_c0[0x80];
12084 
12085 	u8         sb_feature_cap_mask[4][0x20];
12086 
12087 	u8         reserved_at_1c0[0x40];
12088 
12089 	u8         cap_total_buffer_size[0x20];
12090 
12091 	u8         cap_cell_size[0x10];
12092 	u8         cap_max_pg_buffers[0x8];
12093 	u8         cap_num_pool_supported[0x8];
12094 
12095 	u8         reserved_at_240[0x8];
12096 	u8         cap_sbsr_stat_size[0x8];
12097 	u8         cap_max_tclass_data[0x8];
12098 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
12099 };
12100 
12101 struct mlx5_ifc_pbmc_reg_bits {
12102 	u8         reserved_at_0[0x8];
12103 	u8         local_port[0x8];
12104 	u8         reserved_at_10[0x10];
12105 
12106 	u8         xoff_timer_value[0x10];
12107 	u8         xoff_refresh[0x10];
12108 
12109 	u8         reserved_at_40[0x9];
12110 	u8         fullness_threshold[0x7];
12111 	u8         port_buffer_size[0x10];
12112 
12113 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
12114 	struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool;
12115 
12116 	u8         reserved_at_320[0x40];
12117 };
12118 
12119 struct mlx5_ifc_sbpr_reg_bits {
12120 	u8         desc[0x1];
12121 	u8         snap[0x1];
12122 	u8         reserved_at_2[0x4];
12123 	u8         dir[0x2];
12124 	u8         reserved_at_8[0x14];
12125 	u8         pool[0x4];
12126 
12127 	u8         infi_size[0x1];
12128 	u8         reserved_at_21[0x7];
12129 	u8         size[0x18];
12130 
12131 	u8         reserved_at_40[0x1c];
12132 	u8         mode[0x4];
12133 
12134 	u8         reserved_at_60[0x8];
12135 	u8         buff_occupancy[0x18];
12136 
12137 	u8         clr[0x1];
12138 	u8         reserved_at_81[0x7];
12139 	u8         max_buff_occupancy[0x18];
12140 
12141 	u8         reserved_at_a0[0x8];
12142 	u8         ext_buff_occupancy[0x18];
12143 };
12144 
12145 struct mlx5_ifc_sbcm_reg_bits {
12146 	u8         desc[0x1];
12147 	u8         snap[0x1];
12148 	u8         reserved_at_2[0x6];
12149 	u8         local_port[0x8];
12150 	u8         pnat[0x2];
12151 	u8         pg_buff[0x6];
12152 	u8         reserved_at_18[0x6];
12153 	u8         dir[0x2];
12154 
12155 	u8         reserved_at_20[0x1f];
12156 	u8         exc[0x1];
12157 
12158 	u8         reserved_at_40[0x40];
12159 
12160 	u8         reserved_at_80[0x8];
12161 	u8         buff_occupancy[0x18];
12162 
12163 	u8         clr[0x1];
12164 	u8         reserved_at_a1[0x7];
12165 	u8         max_buff_occupancy[0x18];
12166 
12167 	u8         reserved_at_c0[0x8];
12168 	u8         min_buff[0x18];
12169 
12170 	u8         infi_max[0x1];
12171 	u8         reserved_at_e1[0x7];
12172 	u8         max_buff[0x18];
12173 
12174 	u8         reserved_at_100[0x20];
12175 
12176 	u8         reserved_at_120[0x1c];
12177 	u8         pool[0x4];
12178 };
12179 
12180 struct mlx5_ifc_qtct_reg_bits {
12181 	u8         reserved_at_0[0x8];
12182 	u8         port_number[0x8];
12183 	u8         reserved_at_10[0xd];
12184 	u8         prio[0x3];
12185 
12186 	u8         reserved_at_20[0x1d];
12187 	u8         tclass[0x3];
12188 };
12189 
12190 struct mlx5_ifc_mcia_reg_bits {
12191 	u8         l[0x1];
12192 	u8         reserved_at_1[0x7];
12193 	u8         module[0x8];
12194 	u8         reserved_at_10[0x8];
12195 	u8         status[0x8];
12196 
12197 	u8         i2c_device_address[0x8];
12198 	u8         page_number[0x8];
12199 	u8         device_address[0x10];
12200 
12201 	u8         reserved_at_40[0x10];
12202 	u8         size[0x10];
12203 
12204 	u8         reserved_at_60[0x20];
12205 
12206 	u8         dword_0[0x20];
12207 	u8         dword_1[0x20];
12208 	u8         dword_2[0x20];
12209 	u8         dword_3[0x20];
12210 	u8         dword_4[0x20];
12211 	u8         dword_5[0x20];
12212 	u8         dword_6[0x20];
12213 	u8         dword_7[0x20];
12214 	u8         dword_8[0x20];
12215 	u8         dword_9[0x20];
12216 	u8         dword_10[0x20];
12217 	u8         dword_11[0x20];
12218 };
12219 
12220 struct mlx5_ifc_dcbx_param_bits {
12221 	u8         dcbx_cee_cap[0x1];
12222 	u8         dcbx_ieee_cap[0x1];
12223 	u8         dcbx_standby_cap[0x1];
12224 	u8         reserved_at_3[0x5];
12225 	u8         port_number[0x8];
12226 	u8         reserved_at_10[0xa];
12227 	u8         max_application_table_size[6];
12228 	u8         reserved_at_20[0x15];
12229 	u8         version_oper[0x3];
12230 	u8         reserved_at_38[5];
12231 	u8         version_admin[0x3];
12232 	u8         willing_admin[0x1];
12233 	u8         reserved_at_41[0x3];
12234 	u8         pfc_cap_oper[0x4];
12235 	u8         reserved_at_48[0x4];
12236 	u8         pfc_cap_admin[0x4];
12237 	u8         reserved_at_50[0x4];
12238 	u8         num_of_tc_oper[0x4];
12239 	u8         reserved_at_58[0x4];
12240 	u8         num_of_tc_admin[0x4];
12241 	u8         remote_willing[0x1];
12242 	u8         reserved_at_61[3];
12243 	u8         remote_pfc_cap[4];
12244 	u8         reserved_at_68[0x14];
12245 	u8         remote_num_of_tc[0x4];
12246 	u8         reserved_at_80[0x18];
12247 	u8         error[0x8];
12248 	u8         reserved_at_a0[0x160];
12249 };
12250 
12251 enum {
12252 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
12253 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
12254 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
12255 };
12256 
12257 struct mlx5_ifc_lagc_bits {
12258 	u8         fdb_selection_mode[0x1];
12259 	u8         reserved_at_1[0x14];
12260 	u8         port_select_mode[0x3];
12261 	u8         reserved_at_18[0x5];
12262 	u8         lag_state[0x3];
12263 
12264 	u8         reserved_at_20[0xc];
12265 	u8         active_port[0x4];
12266 	u8         reserved_at_30[0x4];
12267 	u8         tx_remap_affinity_2[0x4];
12268 	u8         reserved_at_38[0x4];
12269 	u8         tx_remap_affinity_1[0x4];
12270 };
12271 
12272 struct mlx5_ifc_create_lag_out_bits {
12273 	u8         status[0x8];
12274 	u8         reserved_at_8[0x18];
12275 
12276 	u8         syndrome[0x20];
12277 
12278 	u8         reserved_at_40[0x40];
12279 };
12280 
12281 struct mlx5_ifc_create_lag_in_bits {
12282 	u8         opcode[0x10];
12283 	u8         reserved_at_10[0x10];
12284 
12285 	u8         reserved_at_20[0x10];
12286 	u8         op_mod[0x10];
12287 
12288 	struct mlx5_ifc_lagc_bits ctx;
12289 };
12290 
12291 struct mlx5_ifc_modify_lag_out_bits {
12292 	u8         status[0x8];
12293 	u8         reserved_at_8[0x18];
12294 
12295 	u8         syndrome[0x20];
12296 
12297 	u8         reserved_at_40[0x40];
12298 };
12299 
12300 struct mlx5_ifc_modify_lag_in_bits {
12301 	u8         opcode[0x10];
12302 	u8         reserved_at_10[0x10];
12303 
12304 	u8         reserved_at_20[0x10];
12305 	u8         op_mod[0x10];
12306 
12307 	u8         reserved_at_40[0x20];
12308 	u8         field_select[0x20];
12309 
12310 	struct mlx5_ifc_lagc_bits ctx;
12311 };
12312 
12313 struct mlx5_ifc_query_lag_out_bits {
12314 	u8         status[0x8];
12315 	u8         reserved_at_8[0x18];
12316 
12317 	u8         syndrome[0x20];
12318 
12319 	struct mlx5_ifc_lagc_bits ctx;
12320 };
12321 
12322 struct mlx5_ifc_query_lag_in_bits {
12323 	u8         opcode[0x10];
12324 	u8         reserved_at_10[0x10];
12325 
12326 	u8         reserved_at_20[0x10];
12327 	u8         op_mod[0x10];
12328 
12329 	u8         reserved_at_40[0x40];
12330 };
12331 
12332 struct mlx5_ifc_destroy_lag_out_bits {
12333 	u8         status[0x8];
12334 	u8         reserved_at_8[0x18];
12335 
12336 	u8         syndrome[0x20];
12337 
12338 	u8         reserved_at_40[0x40];
12339 };
12340 
12341 struct mlx5_ifc_destroy_lag_in_bits {
12342 	u8         opcode[0x10];
12343 	u8         reserved_at_10[0x10];
12344 
12345 	u8         reserved_at_20[0x10];
12346 	u8         op_mod[0x10];
12347 
12348 	u8         reserved_at_40[0x40];
12349 };
12350 
12351 struct mlx5_ifc_create_vport_lag_out_bits {
12352 	u8         status[0x8];
12353 	u8         reserved_at_8[0x18];
12354 
12355 	u8         syndrome[0x20];
12356 
12357 	u8         reserved_at_40[0x40];
12358 };
12359 
12360 struct mlx5_ifc_create_vport_lag_in_bits {
12361 	u8         opcode[0x10];
12362 	u8         reserved_at_10[0x10];
12363 
12364 	u8         reserved_at_20[0x10];
12365 	u8         op_mod[0x10];
12366 
12367 	u8         reserved_at_40[0x40];
12368 };
12369 
12370 struct mlx5_ifc_destroy_vport_lag_out_bits {
12371 	u8         status[0x8];
12372 	u8         reserved_at_8[0x18];
12373 
12374 	u8         syndrome[0x20];
12375 
12376 	u8         reserved_at_40[0x40];
12377 };
12378 
12379 struct mlx5_ifc_destroy_vport_lag_in_bits {
12380 	u8         opcode[0x10];
12381 	u8         reserved_at_10[0x10];
12382 
12383 	u8         reserved_at_20[0x10];
12384 	u8         op_mod[0x10];
12385 
12386 	u8         reserved_at_40[0x40];
12387 };
12388 
12389 enum {
12390 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
12391 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12392 };
12393 
12394 struct mlx5_ifc_modify_memic_in_bits {
12395 	u8         opcode[0x10];
12396 	u8         uid[0x10];
12397 
12398 	u8         reserved_at_20[0x10];
12399 	u8         op_mod[0x10];
12400 
12401 	u8         reserved_at_40[0x20];
12402 
12403 	u8         reserved_at_60[0x18];
12404 	u8         memic_operation_type[0x8];
12405 
12406 	u8         memic_start_addr[0x40];
12407 
12408 	u8         reserved_at_c0[0x140];
12409 };
12410 
12411 struct mlx5_ifc_modify_memic_out_bits {
12412 	u8         status[0x8];
12413 	u8         reserved_at_8[0x18];
12414 
12415 	u8         syndrome[0x20];
12416 
12417 	u8         reserved_at_40[0x40];
12418 
12419 	u8         memic_operation_addr[0x40];
12420 
12421 	u8         reserved_at_c0[0x140];
12422 };
12423 
12424 struct mlx5_ifc_alloc_memic_in_bits {
12425 	u8         opcode[0x10];
12426 	u8         reserved_at_10[0x10];
12427 
12428 	u8         reserved_at_20[0x10];
12429 	u8         op_mod[0x10];
12430 
12431 	u8         reserved_at_30[0x20];
12432 
12433 	u8	   reserved_at_40[0x18];
12434 	u8	   log_memic_addr_alignment[0x8];
12435 
12436 	u8         range_start_addr[0x40];
12437 
12438 	u8         range_size[0x20];
12439 
12440 	u8         memic_size[0x20];
12441 };
12442 
12443 struct mlx5_ifc_alloc_memic_out_bits {
12444 	u8         status[0x8];
12445 	u8         reserved_at_8[0x18];
12446 
12447 	u8         syndrome[0x20];
12448 
12449 	u8         memic_start_addr[0x40];
12450 };
12451 
12452 struct mlx5_ifc_dealloc_memic_in_bits {
12453 	u8         opcode[0x10];
12454 	u8         reserved_at_10[0x10];
12455 
12456 	u8         reserved_at_20[0x10];
12457 	u8         op_mod[0x10];
12458 
12459 	u8         reserved_at_40[0x40];
12460 
12461 	u8         memic_start_addr[0x40];
12462 
12463 	u8         memic_size[0x20];
12464 
12465 	u8         reserved_at_e0[0x20];
12466 };
12467 
12468 struct mlx5_ifc_dealloc_memic_out_bits {
12469 	u8         status[0x8];
12470 	u8         reserved_at_8[0x18];
12471 
12472 	u8         syndrome[0x20];
12473 
12474 	u8         reserved_at_40[0x40];
12475 };
12476 
12477 struct mlx5_ifc_umem_bits {
12478 	u8         reserved_at_0[0x80];
12479 
12480 	u8         ats[0x1];
12481 	u8         reserved_at_81[0x1a];
12482 	u8         log_page_size[0x5];
12483 
12484 	u8         page_offset[0x20];
12485 
12486 	u8         num_of_mtt[0x40];
12487 
12488 	struct mlx5_ifc_mtt_bits  mtt[];
12489 };
12490 
12491 struct mlx5_ifc_uctx_bits {
12492 	u8         cap[0x20];
12493 
12494 	u8         reserved_at_20[0x160];
12495 };
12496 
12497 struct mlx5_ifc_sw_icm_bits {
12498 	u8         modify_field_select[0x40];
12499 
12500 	u8	   reserved_at_40[0x18];
12501 	u8         log_sw_icm_size[0x8];
12502 
12503 	u8         reserved_at_60[0x20];
12504 
12505 	u8         sw_icm_start_addr[0x40];
12506 
12507 	u8         reserved_at_c0[0x140];
12508 };
12509 
12510 struct mlx5_ifc_geneve_tlv_option_bits {
12511 	u8         modify_field_select[0x40];
12512 
12513 	u8         reserved_at_40[0x18];
12514 	u8         geneve_option_fte_index[0x8];
12515 
12516 	u8         option_class[0x10];
12517 	u8         option_type[0x8];
12518 	u8         reserved_at_78[0x3];
12519 	u8         option_data_length[0x5];
12520 
12521 	u8         reserved_at_80[0x180];
12522 };
12523 
12524 struct mlx5_ifc_create_umem_in_bits {
12525 	u8         opcode[0x10];
12526 	u8         uid[0x10];
12527 
12528 	u8         reserved_at_20[0x10];
12529 	u8         op_mod[0x10];
12530 
12531 	u8         reserved_at_40[0x40];
12532 
12533 	struct mlx5_ifc_umem_bits  umem;
12534 };
12535 
12536 struct mlx5_ifc_create_umem_out_bits {
12537 	u8         status[0x8];
12538 	u8         reserved_at_8[0x18];
12539 
12540 	u8         syndrome[0x20];
12541 
12542 	u8         reserved_at_40[0x8];
12543 	u8         umem_id[0x18];
12544 
12545 	u8         reserved_at_60[0x20];
12546 };
12547 
12548 struct mlx5_ifc_destroy_umem_in_bits {
12549 	u8        opcode[0x10];
12550 	u8        uid[0x10];
12551 
12552 	u8        reserved_at_20[0x10];
12553 	u8        op_mod[0x10];
12554 
12555 	u8        reserved_at_40[0x8];
12556 	u8        umem_id[0x18];
12557 
12558 	u8        reserved_at_60[0x20];
12559 };
12560 
12561 struct mlx5_ifc_destroy_umem_out_bits {
12562 	u8        status[0x8];
12563 	u8        reserved_at_8[0x18];
12564 
12565 	u8        syndrome[0x20];
12566 
12567 	u8        reserved_at_40[0x40];
12568 };
12569 
12570 struct mlx5_ifc_create_uctx_in_bits {
12571 	u8         opcode[0x10];
12572 	u8         reserved_at_10[0x10];
12573 
12574 	u8         reserved_at_20[0x10];
12575 	u8         op_mod[0x10];
12576 
12577 	u8         reserved_at_40[0x40];
12578 
12579 	struct mlx5_ifc_uctx_bits  uctx;
12580 };
12581 
12582 struct mlx5_ifc_create_uctx_out_bits {
12583 	u8         status[0x8];
12584 	u8         reserved_at_8[0x18];
12585 
12586 	u8         syndrome[0x20];
12587 
12588 	u8         reserved_at_40[0x10];
12589 	u8         uid[0x10];
12590 
12591 	u8         reserved_at_60[0x20];
12592 };
12593 
12594 struct mlx5_ifc_destroy_uctx_in_bits {
12595 	u8         opcode[0x10];
12596 	u8         reserved_at_10[0x10];
12597 
12598 	u8         reserved_at_20[0x10];
12599 	u8         op_mod[0x10];
12600 
12601 	u8         reserved_at_40[0x10];
12602 	u8         uid[0x10];
12603 
12604 	u8         reserved_at_60[0x20];
12605 };
12606 
12607 struct mlx5_ifc_destroy_uctx_out_bits {
12608 	u8         status[0x8];
12609 	u8         reserved_at_8[0x18];
12610 
12611 	u8         syndrome[0x20];
12612 
12613 	u8          reserved_at_40[0x40];
12614 };
12615 
12616 struct mlx5_ifc_create_sw_icm_in_bits {
12617 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12618 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12619 };
12620 
12621 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12622 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12623 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12624 };
12625 
12626 struct mlx5_ifc_mtrc_string_db_param_bits {
12627 	u8         string_db_base_address[0x20];
12628 
12629 	u8         reserved_at_20[0x8];
12630 	u8         string_db_size[0x18];
12631 };
12632 
12633 struct mlx5_ifc_mtrc_cap_bits {
12634 	u8         trace_owner[0x1];
12635 	u8         trace_to_memory[0x1];
12636 	u8         reserved_at_2[0x4];
12637 	u8         trc_ver[0x2];
12638 	u8         reserved_at_8[0x14];
12639 	u8         num_string_db[0x4];
12640 
12641 	u8         first_string_trace[0x8];
12642 	u8         num_string_trace[0x8];
12643 	u8         reserved_at_30[0x28];
12644 
12645 	u8         log_max_trace_buffer_size[0x8];
12646 
12647 	u8         reserved_at_60[0x20];
12648 
12649 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12650 
12651 	u8         reserved_at_280[0x180];
12652 };
12653 
12654 struct mlx5_ifc_mtrc_conf_bits {
12655 	u8         reserved_at_0[0x1c];
12656 	u8         trace_mode[0x4];
12657 	u8         reserved_at_20[0x18];
12658 	u8         log_trace_buffer_size[0x8];
12659 	u8         trace_mkey[0x20];
12660 	u8         reserved_at_60[0x3a0];
12661 };
12662 
12663 struct mlx5_ifc_mtrc_stdb_bits {
12664 	u8         string_db_index[0x4];
12665 	u8         reserved_at_4[0x4];
12666 	u8         read_size[0x18];
12667 	u8         start_offset[0x20];
12668 	u8         string_db_data[];
12669 };
12670 
12671 struct mlx5_ifc_mtrc_ctrl_bits {
12672 	u8         trace_status[0x2];
12673 	u8         reserved_at_2[0x2];
12674 	u8         arm_event[0x1];
12675 	u8         reserved_at_5[0xb];
12676 	u8         modify_field_select[0x10];
12677 	u8         reserved_at_20[0x2b];
12678 	u8         current_timestamp52_32[0x15];
12679 	u8         current_timestamp31_0[0x20];
12680 	u8         reserved_at_80[0x180];
12681 };
12682 
12683 struct mlx5_ifc_host_params_context_bits {
12684 	u8         host_number[0x8];
12685 	u8         reserved_at_8[0x5];
12686 	u8         host_pf_not_exist[0x1];
12687 	u8         reserved_at_14[0x1];
12688 	u8         host_pf_disabled[0x1];
12689 	u8         host_num_of_vfs[0x10];
12690 
12691 	u8         host_total_vfs[0x10];
12692 	u8         host_pci_bus[0x10];
12693 
12694 	u8         reserved_at_40[0x10];
12695 	u8         host_pci_device[0x10];
12696 
12697 	u8         reserved_at_60[0x10];
12698 	u8         host_pci_function[0x10];
12699 
12700 	u8         reserved_at_80[0x180];
12701 };
12702 
12703 struct mlx5_ifc_query_esw_functions_in_bits {
12704 	u8         opcode[0x10];
12705 	u8         reserved_at_10[0x10];
12706 
12707 	u8         reserved_at_20[0x10];
12708 	u8         op_mod[0x10];
12709 
12710 	u8         reserved_at_40[0x40];
12711 };
12712 
12713 struct mlx5_ifc_query_esw_functions_out_bits {
12714 	u8         status[0x8];
12715 	u8         reserved_at_8[0x18];
12716 
12717 	u8         syndrome[0x20];
12718 
12719 	u8         reserved_at_40[0x40];
12720 
12721 	struct mlx5_ifc_host_params_context_bits host_params_context;
12722 
12723 	u8         reserved_at_280[0x180];
12724 	u8         host_sf_enable[][0x40];
12725 };
12726 
12727 struct mlx5_ifc_sf_partition_bits {
12728 	u8         reserved_at_0[0x10];
12729 	u8         log_num_sf[0x8];
12730 	u8         log_sf_bar_size[0x8];
12731 };
12732 
12733 struct mlx5_ifc_query_sf_partitions_out_bits {
12734 	u8         status[0x8];
12735 	u8         reserved_at_8[0x18];
12736 
12737 	u8         syndrome[0x20];
12738 
12739 	u8         reserved_at_40[0x18];
12740 	u8         num_sf_partitions[0x8];
12741 
12742 	u8         reserved_at_60[0x20];
12743 
12744 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12745 };
12746 
12747 struct mlx5_ifc_query_sf_partitions_in_bits {
12748 	u8         opcode[0x10];
12749 	u8         reserved_at_10[0x10];
12750 
12751 	u8         reserved_at_20[0x10];
12752 	u8         op_mod[0x10];
12753 
12754 	u8         reserved_at_40[0x40];
12755 };
12756 
12757 struct mlx5_ifc_dealloc_sf_out_bits {
12758 	u8         status[0x8];
12759 	u8         reserved_at_8[0x18];
12760 
12761 	u8         syndrome[0x20];
12762 
12763 	u8         reserved_at_40[0x40];
12764 };
12765 
12766 struct mlx5_ifc_dealloc_sf_in_bits {
12767 	u8         opcode[0x10];
12768 	u8         reserved_at_10[0x10];
12769 
12770 	u8         reserved_at_20[0x10];
12771 	u8         op_mod[0x10];
12772 
12773 	u8         reserved_at_40[0x10];
12774 	u8         function_id[0x10];
12775 
12776 	u8         reserved_at_60[0x20];
12777 };
12778 
12779 struct mlx5_ifc_alloc_sf_out_bits {
12780 	u8         status[0x8];
12781 	u8         reserved_at_8[0x18];
12782 
12783 	u8         syndrome[0x20];
12784 
12785 	u8         reserved_at_40[0x40];
12786 };
12787 
12788 struct mlx5_ifc_alloc_sf_in_bits {
12789 	u8         opcode[0x10];
12790 	u8         reserved_at_10[0x10];
12791 
12792 	u8         reserved_at_20[0x10];
12793 	u8         op_mod[0x10];
12794 
12795 	u8         reserved_at_40[0x10];
12796 	u8         function_id[0x10];
12797 
12798 	u8         reserved_at_60[0x20];
12799 };
12800 
12801 struct mlx5_ifc_affiliated_event_header_bits {
12802 	u8         reserved_at_0[0x10];
12803 	u8         obj_type[0x10];
12804 
12805 	u8         obj_id[0x20];
12806 };
12807 
12808 enum {
12809 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12810 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12811 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12812 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12813 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12814 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12815 	MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12816 	MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58,
12817 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12818 };
12819 
12820 enum {
12821 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =
12822 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY),
12823 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =
12824 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC),
12825 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =
12826 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER),
12827 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =
12828 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO),
12829 };
12830 
12831 enum {
12832 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =
12833 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
12834 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =
12835 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
12836 };
12837 
12838 enum {
12839 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12840 };
12841 
12842 enum {
12843 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12844 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12845 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12846 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12847 };
12848 
12849 enum {
12850 	MLX5_IPSEC_ASO_MODE              = 0x0,
12851 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12852 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12853 };
12854 
12855 enum {
12856 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12857 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12858 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12859 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12860 };
12861 
12862 struct mlx5_ifc_ipsec_aso_bits {
12863 	u8         valid[0x1];
12864 	u8         reserved_at_201[0x1];
12865 	u8         mode[0x2];
12866 	u8         window_sz[0x2];
12867 	u8         soft_lft_arm[0x1];
12868 	u8         hard_lft_arm[0x1];
12869 	u8         remove_flow_enable[0x1];
12870 	u8         esn_event_arm[0x1];
12871 	u8         reserved_at_20a[0x16];
12872 
12873 	u8         remove_flow_pkt_cnt[0x20];
12874 
12875 	u8         remove_flow_soft_lft[0x20];
12876 
12877 	u8         reserved_at_260[0x80];
12878 
12879 	u8         mode_parameter[0x20];
12880 
12881 	u8         replay_protection_window[0x100];
12882 };
12883 
12884 struct mlx5_ifc_ipsec_obj_bits {
12885 	u8         modify_field_select[0x40];
12886 	u8         full_offload[0x1];
12887 	u8         reserved_at_41[0x1];
12888 	u8         esn_en[0x1];
12889 	u8         esn_overlap[0x1];
12890 	u8         reserved_at_44[0x2];
12891 	u8         icv_length[0x2];
12892 	u8         reserved_at_48[0x4];
12893 	u8         aso_return_reg[0x4];
12894 	u8         reserved_at_50[0x10];
12895 
12896 	u8         esn_msb[0x20];
12897 
12898 	u8         reserved_at_80[0x8];
12899 	u8         dekn[0x18];
12900 
12901 	u8         salt[0x20];
12902 
12903 	u8         implicit_iv[0x40];
12904 
12905 	u8         reserved_at_100[0x8];
12906 	u8         ipsec_aso_access_pd[0x18];
12907 	u8         reserved_at_120[0xe0];
12908 
12909 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12910 };
12911 
12912 struct mlx5_ifc_create_ipsec_obj_in_bits {
12913 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12914 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12915 };
12916 
12917 enum {
12918 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12919 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12920 };
12921 
12922 struct mlx5_ifc_query_ipsec_obj_out_bits {
12923 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12924 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12925 };
12926 
12927 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12928 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12929 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12930 };
12931 
12932 enum {
12933 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12934 };
12935 
12936 enum {
12937 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12938 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12939 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12940 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12941 };
12942 
12943 #define MLX5_MACSEC_ASO_INC_SN  0x2
12944 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12945 
12946 struct mlx5_ifc_macsec_aso_bits {
12947 	u8    valid[0x1];
12948 	u8    reserved_at_1[0x1];
12949 	u8    mode[0x2];
12950 	u8    window_size[0x2];
12951 	u8    soft_lifetime_arm[0x1];
12952 	u8    hard_lifetime_arm[0x1];
12953 	u8    remove_flow_enable[0x1];
12954 	u8    epn_event_arm[0x1];
12955 	u8    reserved_at_a[0x16];
12956 
12957 	u8    remove_flow_packet_count[0x20];
12958 
12959 	u8    remove_flow_soft_lifetime[0x20];
12960 
12961 	u8    reserved_at_60[0x80];
12962 
12963 	u8    mode_parameter[0x20];
12964 
12965 	u8    replay_protection_window[8][0x20];
12966 };
12967 
12968 struct mlx5_ifc_macsec_offload_obj_bits {
12969 	u8    modify_field_select[0x40];
12970 
12971 	u8    confidentiality_en[0x1];
12972 	u8    reserved_at_41[0x1];
12973 	u8    epn_en[0x1];
12974 	u8    epn_overlap[0x1];
12975 	u8    reserved_at_44[0x2];
12976 	u8    confidentiality_offset[0x2];
12977 	u8    reserved_at_48[0x4];
12978 	u8    aso_return_reg[0x4];
12979 	u8    reserved_at_50[0x10];
12980 
12981 	u8    epn_msb[0x20];
12982 
12983 	u8    reserved_at_80[0x8];
12984 	u8    dekn[0x18];
12985 
12986 	u8    reserved_at_a0[0x20];
12987 
12988 	u8    sci[0x40];
12989 
12990 	u8    reserved_at_100[0x8];
12991 	u8    macsec_aso_access_pd[0x18];
12992 
12993 	u8    reserved_at_120[0x60];
12994 
12995 	u8    salt[3][0x20];
12996 
12997 	u8    reserved_at_1e0[0x20];
12998 
12999 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
13000 };
13001 
13002 struct mlx5_ifc_create_macsec_obj_in_bits {
13003 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13004 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
13005 };
13006 
13007 struct mlx5_ifc_modify_macsec_obj_in_bits {
13008 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13009 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
13010 };
13011 
13012 enum {
13013 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
13014 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
13015 };
13016 
13017 struct mlx5_ifc_query_macsec_obj_out_bits {
13018 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13019 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
13020 };
13021 
13022 struct mlx5_ifc_wrapped_dek_bits {
13023 	u8         gcm_iv[0x60];
13024 
13025 	u8         reserved_at_60[0x20];
13026 
13027 	u8         const0[0x1];
13028 	u8         key_size[0x1];
13029 	u8         reserved_at_82[0x2];
13030 	u8         key2_invalid[0x1];
13031 	u8         reserved_at_85[0x3];
13032 	u8         pd[0x18];
13033 
13034 	u8         key_purpose[0x5];
13035 	u8         reserved_at_a5[0x13];
13036 	u8         kek_id[0x8];
13037 
13038 	u8         reserved_at_c0[0x40];
13039 
13040 	u8         key1[0x8][0x20];
13041 
13042 	u8         key2[0x8][0x20];
13043 
13044 	u8         reserved_at_300[0x40];
13045 
13046 	u8         const1[0x1];
13047 	u8         reserved_at_341[0x1f];
13048 
13049 	u8         reserved_at_360[0x20];
13050 
13051 	u8         auth_tag[0x80];
13052 };
13053 
13054 struct mlx5_ifc_encryption_key_obj_bits {
13055 	u8         modify_field_select[0x40];
13056 
13057 	u8         state[0x8];
13058 	u8         sw_wrapped[0x1];
13059 	u8         reserved_at_49[0xb];
13060 	u8         key_size[0x4];
13061 	u8         reserved_at_58[0x4];
13062 	u8         key_purpose[0x4];
13063 
13064 	u8         reserved_at_60[0x8];
13065 	u8         pd[0x18];
13066 
13067 	u8         reserved_at_80[0x100];
13068 
13069 	u8         opaque[0x40];
13070 
13071 	u8         reserved_at_1c0[0x40];
13072 
13073 	u8         key[8][0x80];
13074 
13075 	u8         sw_wrapped_dek[8][0x80];
13076 
13077 	u8         reserved_at_a00[0x600];
13078 };
13079 
13080 struct mlx5_ifc_create_encryption_key_in_bits {
13081 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13082 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
13083 };
13084 
13085 struct mlx5_ifc_modify_encryption_key_in_bits {
13086 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13087 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
13088 };
13089 
13090 enum {
13091 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
13092 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
13093 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
13094 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
13095 };
13096 
13097 struct mlx5_ifc_flow_meter_parameters_bits {
13098 	u8         valid[0x1];
13099 	u8         bucket_overflow[0x1];
13100 	u8         start_color[0x2];
13101 	u8         both_buckets_on_green[0x1];
13102 	u8         reserved_at_5[0x1];
13103 	u8         meter_mode[0x2];
13104 	u8         reserved_at_8[0x18];
13105 
13106 	u8         reserved_at_20[0x20];
13107 
13108 	u8         reserved_at_40[0x3];
13109 	u8         cbs_exponent[0x5];
13110 	u8         cbs_mantissa[0x8];
13111 	u8         reserved_at_50[0x3];
13112 	u8         cir_exponent[0x5];
13113 	u8         cir_mantissa[0x8];
13114 
13115 	u8         reserved_at_60[0x20];
13116 
13117 	u8         reserved_at_80[0x3];
13118 	u8         ebs_exponent[0x5];
13119 	u8         ebs_mantissa[0x8];
13120 	u8         reserved_at_90[0x3];
13121 	u8         eir_exponent[0x5];
13122 	u8         eir_mantissa[0x8];
13123 
13124 	u8         reserved_at_a0[0x60];
13125 };
13126 
13127 struct mlx5_ifc_flow_meter_aso_obj_bits {
13128 	u8         modify_field_select[0x40];
13129 
13130 	u8         reserved_at_40[0x40];
13131 
13132 	u8         reserved_at_80[0x8];
13133 	u8         meter_aso_access_pd[0x18];
13134 
13135 	u8         reserved_at_a0[0x160];
13136 
13137 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
13138 };
13139 
13140 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
13141 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13142 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
13143 };
13144 
13145 struct mlx5_ifc_int_kek_obj_bits {
13146 	u8         modify_field_select[0x40];
13147 
13148 	u8         state[0x8];
13149 	u8         auto_gen[0x1];
13150 	u8         reserved_at_49[0xb];
13151 	u8         key_size[0x4];
13152 	u8         reserved_at_58[0x8];
13153 
13154 	u8         reserved_at_60[0x8];
13155 	u8         pd[0x18];
13156 
13157 	u8         reserved_at_80[0x180];
13158 	u8         key[8][0x80];
13159 
13160 	u8         reserved_at_600[0x200];
13161 };
13162 
13163 struct mlx5_ifc_create_int_kek_obj_in_bits {
13164 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13165 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13166 };
13167 
13168 struct mlx5_ifc_create_int_kek_obj_out_bits {
13169 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13170 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13171 };
13172 
13173 struct mlx5_ifc_sampler_obj_bits {
13174 	u8         modify_field_select[0x40];
13175 
13176 	u8         table_type[0x8];
13177 	u8         level[0x8];
13178 	u8         reserved_at_50[0xf];
13179 	u8         ignore_flow_level[0x1];
13180 
13181 	u8         sample_ratio[0x20];
13182 
13183 	u8         reserved_at_80[0x8];
13184 	u8         sample_table_id[0x18];
13185 
13186 	u8         reserved_at_a0[0x8];
13187 	u8         default_table_id[0x18];
13188 
13189 	u8         sw_steering_icm_address_rx[0x40];
13190 	u8         sw_steering_icm_address_tx[0x40];
13191 
13192 	u8         reserved_at_140[0xa0];
13193 };
13194 
13195 struct mlx5_ifc_create_sampler_obj_in_bits {
13196 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13197 	struct mlx5_ifc_sampler_obj_bits sampler_object;
13198 };
13199 
13200 struct mlx5_ifc_query_sampler_obj_out_bits {
13201 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13202 	struct mlx5_ifc_sampler_obj_bits sampler_object;
13203 };
13204 
13205 enum {
13206 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
13207 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
13208 };
13209 
13210 enum {
13211 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
13212 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
13213 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
13214 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6,
13215 };
13216 
13217 struct mlx5_ifc_tls_static_params_bits {
13218 	u8         const_2[0x2];
13219 	u8         tls_version[0x4];
13220 	u8         const_1[0x2];
13221 	u8         reserved_at_8[0x14];
13222 	u8         encryption_standard[0x4];
13223 
13224 	u8         reserved_at_20[0x20];
13225 
13226 	u8         initial_record_number[0x40];
13227 
13228 	u8         resync_tcp_sn[0x20];
13229 
13230 	u8         gcm_iv[0x20];
13231 
13232 	u8         implicit_iv[0x40];
13233 
13234 	u8         reserved_at_100[0x8];
13235 	u8         dek_index[0x18];
13236 
13237 	u8         reserved_at_120[0xe0];
13238 };
13239 
13240 struct mlx5_ifc_tls_progress_params_bits {
13241 	u8         next_record_tcp_sn[0x20];
13242 
13243 	u8         hw_resync_tcp_sn[0x20];
13244 
13245 	u8         record_tracker_state[0x2];
13246 	u8         auth_state[0x2];
13247 	u8         reserved_at_44[0x4];
13248 	u8         hw_offset_record_number[0x18];
13249 };
13250 
13251 enum {
13252 	MLX5_MTT_PERM_READ	= 1 << 0,
13253 	MLX5_MTT_PERM_WRITE	= 1 << 1,
13254 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
13255 };
13256 
13257 enum {
13258 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
13259 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
13260 };
13261 
13262 struct mlx5_ifc_suspend_vhca_in_bits {
13263 	u8         opcode[0x10];
13264 	u8         uid[0x10];
13265 
13266 	u8         reserved_at_20[0x10];
13267 	u8         op_mod[0x10];
13268 
13269 	u8         reserved_at_40[0x10];
13270 	u8         vhca_id[0x10];
13271 
13272 	u8         reserved_at_60[0x20];
13273 };
13274 
13275 struct mlx5_ifc_suspend_vhca_out_bits {
13276 	u8         status[0x8];
13277 	u8         reserved_at_8[0x18];
13278 
13279 	u8         syndrome[0x20];
13280 
13281 	u8         reserved_at_40[0x40];
13282 };
13283 
13284 enum {
13285 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
13286 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
13287 };
13288 
13289 struct mlx5_ifc_resume_vhca_in_bits {
13290 	u8         opcode[0x10];
13291 	u8         uid[0x10];
13292 
13293 	u8         reserved_at_20[0x10];
13294 	u8         op_mod[0x10];
13295 
13296 	u8         reserved_at_40[0x10];
13297 	u8         vhca_id[0x10];
13298 
13299 	u8         reserved_at_60[0x20];
13300 };
13301 
13302 struct mlx5_ifc_resume_vhca_out_bits {
13303 	u8         status[0x8];
13304 	u8         reserved_at_8[0x18];
13305 
13306 	u8         syndrome[0x20];
13307 
13308 	u8         reserved_at_40[0x40];
13309 };
13310 
13311 struct mlx5_ifc_query_vhca_migration_state_in_bits {
13312 	u8         opcode[0x10];
13313 	u8         uid[0x10];
13314 
13315 	u8         reserved_at_20[0x10];
13316 	u8         op_mod[0x10];
13317 
13318 	u8         incremental[0x1];
13319 	u8         chunk[0x1];
13320 	u8         reserved_at_42[0xe];
13321 	u8         vhca_id[0x10];
13322 
13323 	u8         reserved_at_60[0x20];
13324 };
13325 
13326 enum {
13327 	MLX5_QUERY_VHCA_MIG_STATE_UNINITIALIZED = 0x0,
13328 	MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_IDLE = 0x1,
13329 	MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_READY = 0x2,
13330 	MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_DIRTY = 0x3,
13331 	MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_INIT = 0x4,
13332 };
13333 
13334 struct mlx5_ifc_query_vhca_migration_state_out_bits {
13335 	u8         status[0x8];
13336 	u8         reserved_at_8[0x18];
13337 
13338 	u8         syndrome[0x20];
13339 
13340 	u8         reserved_at_40[0x20];
13341 
13342 	u8         migration_state[0x4];
13343 	u8         reserved_at_64[0x1c];
13344 
13345 	u8         required_umem_size[0x20];
13346 
13347 	u8         reserved_at_a0[0x20];
13348 
13349 	u8         remaining_total_size[0x40];
13350 
13351 	u8         reserved_at_100[0x100];
13352 };
13353 
13354 struct mlx5_ifc_save_vhca_state_in_bits {
13355 	u8         opcode[0x10];
13356 	u8         uid[0x10];
13357 
13358 	u8         reserved_at_20[0x10];
13359 	u8         op_mod[0x10];
13360 
13361 	u8         incremental[0x1];
13362 	u8         set_track[0x1];
13363 	u8         reserved_at_42[0xe];
13364 	u8         vhca_id[0x10];
13365 
13366 	u8         reserved_at_60[0x20];
13367 
13368 	u8         va[0x40];
13369 
13370 	u8         mkey[0x20];
13371 
13372 	u8         size[0x20];
13373 };
13374 
13375 struct mlx5_ifc_save_vhca_state_out_bits {
13376 	u8         status[0x8];
13377 	u8         reserved_at_8[0x18];
13378 
13379 	u8         syndrome[0x20];
13380 
13381 	u8         actual_image_size[0x20];
13382 
13383 	u8         next_required_umem_size[0x20];
13384 };
13385 
13386 struct mlx5_ifc_load_vhca_state_in_bits {
13387 	u8         opcode[0x10];
13388 	u8         uid[0x10];
13389 
13390 	u8         reserved_at_20[0x10];
13391 	u8         op_mod[0x10];
13392 
13393 	u8         reserved_at_40[0x10];
13394 	u8         vhca_id[0x10];
13395 
13396 	u8         reserved_at_60[0x20];
13397 
13398 	u8         va[0x40];
13399 
13400 	u8         mkey[0x20];
13401 
13402 	u8         size[0x20];
13403 };
13404 
13405 struct mlx5_ifc_load_vhca_state_out_bits {
13406 	u8         status[0x8];
13407 	u8         reserved_at_8[0x18];
13408 
13409 	u8         syndrome[0x20];
13410 
13411 	u8         reserved_at_40[0x40];
13412 };
13413 
13414 struct mlx5_ifc_adv_rdma_cap_bits {
13415 	u8         rdma_transport_manager[0x1];
13416 	u8         rdma_transport_manager_other_eswitch[0x1];
13417 	u8         reserved_at_2[0x1e];
13418 
13419 	u8         rcx_type[0x8];
13420 	u8         reserved_at_28[0x2];
13421 	u8         ps_entry_log_max_value[0x6];
13422 	u8         reserved_at_30[0x6];
13423 	u8         qp_max_ps_num_entry[0xa];
13424 
13425 	u8         mp_max_num_queues[0x8];
13426 	u8         ps_user_context_max_log_size[0x8];
13427 	u8         message_based_qp_and_striding_wq[0x8];
13428 	u8         reserved_at_58[0x8];
13429 
13430 	u8         max_receive_send_message_size_stride[0x10];
13431 	u8         reserved_at_70[0x10];
13432 
13433 	u8         max_receive_send_message_size_byte[0x20];
13434 
13435 	u8         reserved_at_a0[0x160];
13436 
13437 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
13438 
13439 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
13440 
13441 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
13442 
13443 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
13444 
13445 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
13446 
13447 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
13448 
13449 	u8         reserved_at_800[0x3800];
13450 };
13451 
13452 struct mlx5_ifc_adv_virtualization_cap_bits {
13453 	u8         reserved_at_0[0x3];
13454 	u8         pg_track_log_max_num[0x5];
13455 	u8         pg_track_max_num_range[0x8];
13456 	u8         pg_track_log_min_addr_space[0x8];
13457 	u8         pg_track_log_max_addr_space[0x8];
13458 
13459 	u8         reserved_at_20[0x3];
13460 	u8         pg_track_log_min_msg_size[0x5];
13461 	u8         reserved_at_28[0x3];
13462 	u8         pg_track_log_max_msg_size[0x5];
13463 	u8         reserved_at_30[0x3];
13464 	u8         pg_track_log_min_page_size[0x5];
13465 	u8         reserved_at_38[0x3];
13466 	u8         pg_track_log_max_page_size[0x5];
13467 
13468 	u8         reserved_at_40[0x7c0];
13469 };
13470 
13471 struct mlx5_ifc_page_track_report_entry_bits {
13472 	u8         dirty_address_high[0x20];
13473 
13474 	u8         dirty_address_low[0x20];
13475 };
13476 
13477 enum {
13478 	MLX5_PAGE_TRACK_STATE_TRACKING,
13479 	MLX5_PAGE_TRACK_STATE_REPORTING,
13480 	MLX5_PAGE_TRACK_STATE_ERROR,
13481 };
13482 
13483 struct mlx5_ifc_page_track_range_bits {
13484 	u8         start_address[0x40];
13485 
13486 	u8         length[0x40];
13487 };
13488 
13489 struct mlx5_ifc_page_track_bits {
13490 	u8         modify_field_select[0x40];
13491 
13492 	u8         reserved_at_40[0x10];
13493 	u8         vhca_id[0x10];
13494 
13495 	u8         reserved_at_60[0x20];
13496 
13497 	u8         state[0x4];
13498 	u8         track_type[0x4];
13499 	u8         log_addr_space_size[0x8];
13500 	u8         reserved_at_90[0x3];
13501 	u8         log_page_size[0x5];
13502 	u8         reserved_at_98[0x3];
13503 	u8         log_msg_size[0x5];
13504 
13505 	u8         reserved_at_a0[0x8];
13506 	u8         reporting_qpn[0x18];
13507 
13508 	u8         reserved_at_c0[0x18];
13509 	u8         num_ranges[0x8];
13510 
13511 	u8         reserved_at_e0[0x20];
13512 
13513 	u8         range_start_address[0x40];
13514 
13515 	u8         length[0x40];
13516 
13517 	struct     mlx5_ifc_page_track_range_bits track_range[0];
13518 };
13519 
13520 struct mlx5_ifc_create_page_track_obj_in_bits {
13521 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13522 	struct mlx5_ifc_page_track_bits obj_context;
13523 };
13524 
13525 struct mlx5_ifc_modify_page_track_obj_in_bits {
13526 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13527 	struct mlx5_ifc_page_track_bits obj_context;
13528 };
13529 
13530 struct mlx5_ifc_query_page_track_obj_out_bits {
13531 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13532 	struct mlx5_ifc_page_track_bits obj_context;
13533 };
13534 
13535 struct mlx5_ifc_msecq_reg_bits {
13536 	u8         reserved_at_0[0x20];
13537 
13538 	u8         reserved_at_20[0x12];
13539 	u8         network_option[0x2];
13540 	u8         local_ssm_code[0x4];
13541 	u8         local_enhanced_ssm_code[0x8];
13542 
13543 	u8         local_clock_identity[0x40];
13544 
13545 	u8         reserved_at_80[0x180];
13546 };
13547 
13548 enum {
13549 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13550 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13551 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13552 };
13553 
13554 enum mlx5_msees_admin_status {
13555 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13556 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13557 };
13558 
13559 enum mlx5_msees_oper_status {
13560 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13561 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13562 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13563 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13564 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13565 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13566 };
13567 
13568 enum mlx5_msees_failure_reason {
13569 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13570 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13571 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13572 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13573 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13574 };
13575 
13576 struct mlx5_ifc_msees_reg_bits {
13577 	u8         reserved_at_0[0x8];
13578 	u8         local_port[0x8];
13579 	u8         pnat[0x2];
13580 	u8         lp_msb[0x2];
13581 	u8         reserved_at_14[0xc];
13582 
13583 	u8         field_select[0x20];
13584 
13585 	u8         admin_status[0x4];
13586 	u8         oper_status[0x4];
13587 	u8         ho_acq[0x1];
13588 	u8         reserved_at_49[0xc];
13589 	u8         admin_freq_measure[0x1];
13590 	u8         oper_freq_measure[0x1];
13591 	u8         failure_reason[0x9];
13592 
13593 	u8         frequency_diff[0x20];
13594 
13595 	u8         reserved_at_80[0x180];
13596 };
13597 
13598 struct mlx5_ifc_mrtcq_reg_bits {
13599 	u8         reserved_at_0[0x40];
13600 
13601 	u8         rt_clock_identity[0x40];
13602 
13603 	u8         reserved_at_80[0x180];
13604 };
13605 
13606 struct mlx5_ifc_pcie_cong_event_obj_bits {
13607 	u8         modify_select_field[0x40];
13608 
13609 	u8         inbound_event_en[0x1];
13610 	u8         outbound_event_en[0x1];
13611 	u8         reserved_at_42[0x1e];
13612 
13613 	u8         reserved_at_60[0x1];
13614 	u8         inbound_cong_state[0x3];
13615 	u8         reserved_at_64[0x1];
13616 	u8         outbound_cong_state[0x3];
13617 	u8         reserved_at_68[0x18];
13618 
13619 	u8         inbound_cong_low_threshold[0x10];
13620 	u8         inbound_cong_high_threshold[0x10];
13621 
13622 	u8         outbound_cong_low_threshold[0x10];
13623 	u8         outbound_cong_high_threshold[0x10];
13624 
13625 	u8         reserved_at_e0[0x340];
13626 };
13627 
13628 struct mlx5_ifc_pcie_cong_event_cmd_in_bits {
13629 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13630 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13631 };
13632 
13633 struct mlx5_ifc_pcie_cong_event_cmd_out_bits {
13634 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
13635 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13636 };
13637 
13638 enum mlx5e_pcie_cong_event_mod_field {
13639 	MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0),
13640 	MLX5_PCIE_CONG_EVENT_MOD_THRESH   = BIT(2),
13641 };
13642 
13643 struct mlx5_ifc_psp_rotate_key_in_bits {
13644 	u8         opcode[0x10];
13645 	u8         uid[0x10];
13646 
13647 	u8         reserved_at_20[0x10];
13648 	u8         op_mod[0x10];
13649 
13650 	u8         reserved_at_40[0x40];
13651 };
13652 
13653 struct mlx5_ifc_psp_rotate_key_out_bits {
13654 	u8         status[0x8];
13655 	u8         reserved_at_8[0x18];
13656 
13657 	u8         syndrome[0x20];
13658 
13659 	u8         reserved_at_40[0x40];
13660 };
13661 
13662 enum mlx5_psp_gen_spi_in_key_size {
13663 	MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0,
13664 	MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1,
13665 };
13666 
13667 struct mlx5_ifc_key_spi_bits {
13668 	u8         spi[0x20];
13669 
13670 	u8         reserved_at_20[0x60];
13671 
13672 	u8         key[8][0x20];
13673 };
13674 
13675 struct mlx5_ifc_psp_gen_spi_in_bits {
13676 	u8         opcode[0x10];
13677 	u8         uid[0x10];
13678 
13679 	u8         reserved_at_20[0x10];
13680 	u8         op_mod[0x10];
13681 
13682 	u8         reserved_at_40[0x20];
13683 
13684 	u8         key_size[0x2];
13685 	u8         reserved_at_62[0xe];
13686 	u8         num_of_spi[0x10];
13687 };
13688 
13689 struct mlx5_ifc_psp_gen_spi_out_bits {
13690 	u8         status[0x8];
13691 	u8         reserved_at_8[0x18];
13692 
13693 	u8         syndrome[0x20];
13694 
13695 	u8         reserved_at_40[0x10];
13696 	u8         num_of_spi[0x10];
13697 
13698 	u8         reserved_at_60[0x20];
13699 
13700 	struct mlx5_ifc_key_spi_bits key_spi[];
13701 };
13702 
13703 #endif /* MLX5_IFC_H */
13704