1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright © 2010-2015 Broadcom Corporation
4 */
5
6 #include <linux/clk.h>
7 #include <linux/module.h>
8 #include <linux/init.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/platform_device.h>
12 #include <linux/platform_data/brcmnand.h>
13 #include <linux/err.h>
14 #include <linux/completion.h>
15 #include <linux/interrupt.h>
16 #include <linux/spinlock.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/ioport.h>
19 #include <linux/bug.h>
20 #include <linux/kernel.h>
21 #include <linux/bitops.h>
22 #include <linux/mm.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
29 #include <linux/static_key.h>
30 #include <linux/list.h>
31 #include <linux/log2.h>
32
33 #include "brcmnand.h"
34
35 /*
36 * This flag controls if WP stays on between erase/write commands to mitigate
37 * flash corruption due to power glitches. Values:
38 * 0: NAND_WP is not used or not available
39 * 1: NAND_WP is set by default, cleared for erase/write operations
40 * 2: NAND_WP is always cleared
41 */
42 static int wp_on = 1;
43 module_param(wp_on, int, 0444);
44
45 /***********************************************************************
46 * Definitions
47 ***********************************************************************/
48
49 #define DRV_NAME "brcmnand"
50
51 #define CMD_NULL 0x00
52 #define CMD_PAGE_READ 0x01
53 #define CMD_SPARE_AREA_READ 0x02
54 #define CMD_STATUS_READ 0x03
55 #define CMD_PROGRAM_PAGE 0x04
56 #define CMD_PROGRAM_SPARE_AREA 0x05
57 #define CMD_COPY_BACK 0x06
58 #define CMD_DEVICE_ID_READ 0x07
59 #define CMD_BLOCK_ERASE 0x08
60 #define CMD_FLASH_RESET 0x09
61 #define CMD_BLOCKS_LOCK 0x0a
62 #define CMD_BLOCKS_LOCK_DOWN 0x0b
63 #define CMD_BLOCKS_UNLOCK 0x0c
64 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
65 #define CMD_PARAMETER_READ 0x0e
66 #define CMD_PARAMETER_CHANGE_COL 0x0f
67 #define CMD_LOW_LEVEL_OP 0x10
68
69 struct brcm_nand_dma_desc {
70 u32 next_desc;
71 u32 next_desc_ext;
72 u32 cmd_irq;
73 u32 dram_addr;
74 u32 dram_addr_ext;
75 u32 tfr_len;
76 u32 total_len;
77 u32 flash_addr;
78 u32 flash_addr_ext;
79 u32 cs;
80 u32 pad2[5];
81 u32 status_valid;
82 } __packed;
83
84 /* Bitfields for brcm_nand_dma_desc::status_valid */
85 #define FLASH_DMA_ECC_ERROR (1 << 8)
86 #define FLASH_DMA_CORR_ERROR (1 << 9)
87
88 /* Bitfields for DMA_MODE */
89 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
90 #define FLASH_DMA_MODE_MODE BIT(0) /* link list */
91 #define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \
92 FLASH_DMA_MODE_MODE)
93
94 /* 512B flash cache in the NAND controller HW */
95 #define FC_SHIFT 9U
96 #define FC_BYTES 512U
97 #define FC_WORDS (FC_BYTES >> 2)
98
99 #define BRCMNAND_MIN_PAGESIZE 512
100 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
101 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
102
103 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
104 #define NAND_POLL_STATUS_TIMEOUT_MS 100
105
106 #define EDU_CMD_WRITE 0x00
107 #define EDU_CMD_READ 0x01
108 #define EDU_STATUS_ACTIVE BIT(0)
109 #define EDU_ERR_STATUS_ERRACK BIT(0)
110 #define EDU_DONE_MASK GENMASK(1, 0)
111
112 #define EDU_CONFIG_MODE_NAND BIT(0)
113 #define EDU_CONFIG_SWAP_BYTE BIT(1)
114 #ifdef CONFIG_CPU_BIG_ENDIAN
115 #define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE
116 #else
117 #define EDU_CONFIG_SWAP_CFG 0
118 #endif
119
120 /* edu registers */
121 enum edu_reg {
122 EDU_CONFIG = 0,
123 EDU_DRAM_ADDR,
124 EDU_EXT_ADDR,
125 EDU_LENGTH,
126 EDU_CMD,
127 EDU_STOP,
128 EDU_STATUS,
129 EDU_DONE,
130 EDU_ERR_STATUS,
131 };
132
133 static const u16 edu_regs[] = {
134 [EDU_CONFIG] = 0x00,
135 [EDU_DRAM_ADDR] = 0x04,
136 [EDU_EXT_ADDR] = 0x08,
137 [EDU_LENGTH] = 0x0c,
138 [EDU_CMD] = 0x10,
139 [EDU_STOP] = 0x14,
140 [EDU_STATUS] = 0x18,
141 [EDU_DONE] = 0x1c,
142 [EDU_ERR_STATUS] = 0x20,
143 };
144
145 /* flash_dma registers */
146 enum flash_dma_reg {
147 FLASH_DMA_REVISION = 0,
148 FLASH_DMA_FIRST_DESC,
149 FLASH_DMA_FIRST_DESC_EXT,
150 FLASH_DMA_CTRL,
151 FLASH_DMA_MODE,
152 FLASH_DMA_STATUS,
153 FLASH_DMA_INTERRUPT_DESC,
154 FLASH_DMA_INTERRUPT_DESC_EXT,
155 FLASH_DMA_ERROR_STATUS,
156 FLASH_DMA_CURRENT_DESC,
157 FLASH_DMA_CURRENT_DESC_EXT,
158 };
159
160 /* flash_dma registers v0*/
161 static const u16 flash_dma_regs_v0[] = {
162 [FLASH_DMA_REVISION] = 0x00,
163 [FLASH_DMA_FIRST_DESC] = 0x04,
164 [FLASH_DMA_CTRL] = 0x08,
165 [FLASH_DMA_MODE] = 0x0c,
166 [FLASH_DMA_STATUS] = 0x10,
167 [FLASH_DMA_INTERRUPT_DESC] = 0x14,
168 [FLASH_DMA_ERROR_STATUS] = 0x18,
169 [FLASH_DMA_CURRENT_DESC] = 0x1c,
170 };
171
172 /* flash_dma registers v1*/
173 static const u16 flash_dma_regs_v1[] = {
174 [FLASH_DMA_REVISION] = 0x00,
175 [FLASH_DMA_FIRST_DESC] = 0x04,
176 [FLASH_DMA_FIRST_DESC_EXT] = 0x08,
177 [FLASH_DMA_CTRL] = 0x0c,
178 [FLASH_DMA_MODE] = 0x10,
179 [FLASH_DMA_STATUS] = 0x14,
180 [FLASH_DMA_INTERRUPT_DESC] = 0x18,
181 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c,
182 [FLASH_DMA_ERROR_STATUS] = 0x20,
183 [FLASH_DMA_CURRENT_DESC] = 0x24,
184 [FLASH_DMA_CURRENT_DESC_EXT] = 0x28,
185 };
186
187 /* flash_dma registers v4 */
188 static const u16 flash_dma_regs_v4[] = {
189 [FLASH_DMA_REVISION] = 0x00,
190 [FLASH_DMA_FIRST_DESC] = 0x08,
191 [FLASH_DMA_FIRST_DESC_EXT] = 0x0c,
192 [FLASH_DMA_CTRL] = 0x10,
193 [FLASH_DMA_MODE] = 0x14,
194 [FLASH_DMA_STATUS] = 0x18,
195 [FLASH_DMA_INTERRUPT_DESC] = 0x20,
196 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24,
197 [FLASH_DMA_ERROR_STATUS] = 0x28,
198 [FLASH_DMA_CURRENT_DESC] = 0x30,
199 [FLASH_DMA_CURRENT_DESC_EXT] = 0x34,
200 };
201
202 /* Controller feature flags */
203 enum {
204 BRCMNAND_HAS_1K_SECTORS = BIT(0),
205 BRCMNAND_HAS_PREFETCH = BIT(1),
206 BRCMNAND_HAS_CACHE_MODE = BIT(2),
207 BRCMNAND_HAS_WP = BIT(3),
208 };
209
210 struct brcmnand_host;
211
212 static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key);
213
214 struct brcmnand_controller {
215 struct device *dev;
216 struct nand_controller controller;
217 void __iomem *nand_base;
218 void __iomem *nand_fc; /* flash cache */
219 void __iomem *flash_dma_base;
220 int irq;
221 unsigned int dma_irq;
222 int nand_version;
223
224 /* Some SoCs provide custom interrupt status register(s) */
225 struct brcmnand_soc *soc;
226
227 /* Some SoCs have a gateable clock for the controller */
228 struct clk *clk;
229
230 int cmd_pending;
231 bool dma_pending;
232 bool edu_pending;
233 struct completion done;
234 struct completion dma_done;
235 struct completion edu_done;
236
237 /* List of NAND hosts (one for each chip-select) */
238 struct list_head host_list;
239
240 /* EDU info, per-transaction */
241 const u16 *edu_offsets;
242 void __iomem *edu_base;
243 int edu_irq;
244 int edu_count;
245 u64 edu_dram_addr;
246 u32 edu_ext_addr;
247 u32 edu_cmd;
248 u32 edu_config;
249 int sas; /* spare area size, per flash cache */
250 int sector_size_1k;
251 u8 *oob;
252
253 /* flash_dma reg */
254 const u16 *flash_dma_offsets;
255 struct brcm_nand_dma_desc *dma_desc;
256 dma_addr_t dma_pa;
257
258 int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf,
259 u8 *oob, u32 len, u8 dma_cmd);
260
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
262 u8 flash_cache[FC_BYTES];
263
264 /* Controller revision details */
265 const u16 *reg_offsets;
266 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
267 const u8 *cs_offsets; /* within each chip-select */
268 const u8 *cs0_offsets; /* within CS0, if different */
269 unsigned int max_block_size;
270 const unsigned int *block_sizes;
271 unsigned int max_page_size;
272 const unsigned int *page_sizes;
273 unsigned int page_size_shift;
274 unsigned int max_oob;
275 u32 ecc_level_shift;
276 u32 features;
277
278 /* for low-power standby/resume only */
279 u32 nand_cs_nand_select;
280 u32 nand_cs_nand_xor;
281 u32 corr_stat_threshold;
282 u32 flash_dma_mode;
283 u32 flash_edu_mode;
284 bool pio_poll_mode;
285 };
286
287 struct brcmnand_cfg {
288 u64 device_size;
289 unsigned int block_size;
290 unsigned int page_size;
291 unsigned int spare_area_size;
292 unsigned int device_width;
293 unsigned int col_adr_bytes;
294 unsigned int blk_adr_bytes;
295 unsigned int ful_adr_bytes;
296 unsigned int sector_size_1k;
297 unsigned int ecc_level;
298 /* use for low-power standby/resume only */
299 u32 acc_control;
300 u32 config;
301 u32 config_ext;
302 u32 timing_1;
303 u32 timing_2;
304 };
305
306 struct brcmnand_host {
307 struct list_head node;
308
309 struct nand_chip chip;
310 struct platform_device *pdev;
311 int cs;
312
313 unsigned int last_cmd;
314 unsigned int last_byte;
315 u64 last_addr;
316 struct brcmnand_cfg hwcfg;
317 struct brcmnand_controller *ctrl;
318 };
319
320 enum brcmnand_reg {
321 BRCMNAND_CMD_START = 0,
322 BRCMNAND_CMD_EXT_ADDRESS,
323 BRCMNAND_CMD_ADDRESS,
324 BRCMNAND_INTFC_STATUS,
325 BRCMNAND_CS_SELECT,
326 BRCMNAND_CS_XOR,
327 BRCMNAND_LL_OP,
328 BRCMNAND_CS0_BASE,
329 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
330 BRCMNAND_CORR_THRESHOLD,
331 BRCMNAND_CORR_THRESHOLD_EXT,
332 BRCMNAND_UNCORR_COUNT,
333 BRCMNAND_CORR_COUNT,
334 BRCMNAND_CORR_EXT_ADDR,
335 BRCMNAND_CORR_ADDR,
336 BRCMNAND_UNCORR_EXT_ADDR,
337 BRCMNAND_UNCORR_ADDR,
338 BRCMNAND_SEMAPHORE,
339 BRCMNAND_ID,
340 BRCMNAND_ID_EXT,
341 BRCMNAND_LL_RDATA,
342 BRCMNAND_OOB_READ_BASE,
343 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
344 BRCMNAND_OOB_WRITE_BASE,
345 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
346 BRCMNAND_FC_BASE,
347 };
348
349 /* BRCMNAND v2.1-v2.2 */
350 static const u16 brcmnand_regs_v21[] = {
351 [BRCMNAND_CMD_START] = 0x04,
352 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
353 [BRCMNAND_CMD_ADDRESS] = 0x0c,
354 [BRCMNAND_INTFC_STATUS] = 0x5c,
355 [BRCMNAND_CS_SELECT] = 0x14,
356 [BRCMNAND_CS_XOR] = 0x18,
357 [BRCMNAND_LL_OP] = 0,
358 [BRCMNAND_CS0_BASE] = 0x40,
359 [BRCMNAND_CS1_BASE] = 0,
360 [BRCMNAND_CORR_THRESHOLD] = 0,
361 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
362 [BRCMNAND_UNCORR_COUNT] = 0,
363 [BRCMNAND_CORR_COUNT] = 0,
364 [BRCMNAND_CORR_EXT_ADDR] = 0x60,
365 [BRCMNAND_CORR_ADDR] = 0x64,
366 [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
367 [BRCMNAND_UNCORR_ADDR] = 0x6c,
368 [BRCMNAND_SEMAPHORE] = 0x50,
369 [BRCMNAND_ID] = 0x54,
370 [BRCMNAND_ID_EXT] = 0,
371 [BRCMNAND_LL_RDATA] = 0,
372 [BRCMNAND_OOB_READ_BASE] = 0x20,
373 [BRCMNAND_OOB_READ_10_BASE] = 0,
374 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
375 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
376 [BRCMNAND_FC_BASE] = 0x200,
377 };
378
379 /* BRCMNAND v3.3-v4.0 */
380 static const u16 brcmnand_regs_v33[] = {
381 [BRCMNAND_CMD_START] = 0x04,
382 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
383 [BRCMNAND_CMD_ADDRESS] = 0x0c,
384 [BRCMNAND_INTFC_STATUS] = 0x6c,
385 [BRCMNAND_CS_SELECT] = 0x14,
386 [BRCMNAND_CS_XOR] = 0x18,
387 [BRCMNAND_LL_OP] = 0x178,
388 [BRCMNAND_CS0_BASE] = 0x40,
389 [BRCMNAND_CS1_BASE] = 0xd0,
390 [BRCMNAND_CORR_THRESHOLD] = 0x84,
391 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
392 [BRCMNAND_UNCORR_COUNT] = 0,
393 [BRCMNAND_CORR_COUNT] = 0,
394 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
395 [BRCMNAND_CORR_ADDR] = 0x74,
396 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
397 [BRCMNAND_UNCORR_ADDR] = 0x7c,
398 [BRCMNAND_SEMAPHORE] = 0x58,
399 [BRCMNAND_ID] = 0x60,
400 [BRCMNAND_ID_EXT] = 0x64,
401 [BRCMNAND_LL_RDATA] = 0x17c,
402 [BRCMNAND_OOB_READ_BASE] = 0x20,
403 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
404 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
405 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
406 [BRCMNAND_FC_BASE] = 0x200,
407 };
408
409 /* BRCMNAND v5.0 */
410 static const u16 brcmnand_regs_v50[] = {
411 [BRCMNAND_CMD_START] = 0x04,
412 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
413 [BRCMNAND_CMD_ADDRESS] = 0x0c,
414 [BRCMNAND_INTFC_STATUS] = 0x6c,
415 [BRCMNAND_CS_SELECT] = 0x14,
416 [BRCMNAND_CS_XOR] = 0x18,
417 [BRCMNAND_LL_OP] = 0x178,
418 [BRCMNAND_CS0_BASE] = 0x40,
419 [BRCMNAND_CS1_BASE] = 0xd0,
420 [BRCMNAND_CORR_THRESHOLD] = 0x84,
421 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
422 [BRCMNAND_UNCORR_COUNT] = 0,
423 [BRCMNAND_CORR_COUNT] = 0,
424 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
425 [BRCMNAND_CORR_ADDR] = 0x74,
426 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
427 [BRCMNAND_UNCORR_ADDR] = 0x7c,
428 [BRCMNAND_SEMAPHORE] = 0x58,
429 [BRCMNAND_ID] = 0x60,
430 [BRCMNAND_ID_EXT] = 0x64,
431 [BRCMNAND_LL_RDATA] = 0x17c,
432 [BRCMNAND_OOB_READ_BASE] = 0x20,
433 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
434 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
435 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
436 [BRCMNAND_FC_BASE] = 0x200,
437 };
438
439 /* BRCMNAND v6.0 - v7.1 */
440 static const u16 brcmnand_regs_v60[] = {
441 [BRCMNAND_CMD_START] = 0x04,
442 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
443 [BRCMNAND_CMD_ADDRESS] = 0x0c,
444 [BRCMNAND_INTFC_STATUS] = 0x14,
445 [BRCMNAND_CS_SELECT] = 0x18,
446 [BRCMNAND_CS_XOR] = 0x1c,
447 [BRCMNAND_LL_OP] = 0x20,
448 [BRCMNAND_CS0_BASE] = 0x50,
449 [BRCMNAND_CS1_BASE] = 0,
450 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
451 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
452 [BRCMNAND_UNCORR_COUNT] = 0xfc,
453 [BRCMNAND_CORR_COUNT] = 0x100,
454 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
455 [BRCMNAND_CORR_ADDR] = 0x110,
456 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
457 [BRCMNAND_UNCORR_ADDR] = 0x118,
458 [BRCMNAND_SEMAPHORE] = 0x150,
459 [BRCMNAND_ID] = 0x194,
460 [BRCMNAND_ID_EXT] = 0x198,
461 [BRCMNAND_LL_RDATA] = 0x19c,
462 [BRCMNAND_OOB_READ_BASE] = 0x200,
463 [BRCMNAND_OOB_READ_10_BASE] = 0,
464 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
465 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
466 [BRCMNAND_FC_BASE] = 0x400,
467 };
468
469 /* BRCMNAND v7.1 */
470 static const u16 brcmnand_regs_v71[] = {
471 [BRCMNAND_CMD_START] = 0x04,
472 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
473 [BRCMNAND_CMD_ADDRESS] = 0x0c,
474 [BRCMNAND_INTFC_STATUS] = 0x14,
475 [BRCMNAND_CS_SELECT] = 0x18,
476 [BRCMNAND_CS_XOR] = 0x1c,
477 [BRCMNAND_LL_OP] = 0x20,
478 [BRCMNAND_CS0_BASE] = 0x50,
479 [BRCMNAND_CS1_BASE] = 0,
480 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
481 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
482 [BRCMNAND_UNCORR_COUNT] = 0xfc,
483 [BRCMNAND_CORR_COUNT] = 0x100,
484 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
485 [BRCMNAND_CORR_ADDR] = 0x110,
486 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
487 [BRCMNAND_UNCORR_ADDR] = 0x118,
488 [BRCMNAND_SEMAPHORE] = 0x150,
489 [BRCMNAND_ID] = 0x194,
490 [BRCMNAND_ID_EXT] = 0x198,
491 [BRCMNAND_LL_RDATA] = 0x19c,
492 [BRCMNAND_OOB_READ_BASE] = 0x200,
493 [BRCMNAND_OOB_READ_10_BASE] = 0,
494 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
495 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
496 [BRCMNAND_FC_BASE] = 0x400,
497 };
498
499 /* BRCMNAND v7.2 */
500 static const u16 brcmnand_regs_v72[] = {
501 [BRCMNAND_CMD_START] = 0x04,
502 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
503 [BRCMNAND_CMD_ADDRESS] = 0x0c,
504 [BRCMNAND_INTFC_STATUS] = 0x14,
505 [BRCMNAND_CS_SELECT] = 0x18,
506 [BRCMNAND_CS_XOR] = 0x1c,
507 [BRCMNAND_LL_OP] = 0x20,
508 [BRCMNAND_CS0_BASE] = 0x50,
509 [BRCMNAND_CS1_BASE] = 0,
510 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
511 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
512 [BRCMNAND_UNCORR_COUNT] = 0xfc,
513 [BRCMNAND_CORR_COUNT] = 0x100,
514 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
515 [BRCMNAND_CORR_ADDR] = 0x110,
516 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
517 [BRCMNAND_UNCORR_ADDR] = 0x118,
518 [BRCMNAND_SEMAPHORE] = 0x150,
519 [BRCMNAND_ID] = 0x194,
520 [BRCMNAND_ID_EXT] = 0x198,
521 [BRCMNAND_LL_RDATA] = 0x19c,
522 [BRCMNAND_OOB_READ_BASE] = 0x200,
523 [BRCMNAND_OOB_READ_10_BASE] = 0,
524 [BRCMNAND_OOB_WRITE_BASE] = 0x400,
525 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
526 [BRCMNAND_FC_BASE] = 0x600,
527 };
528
529 enum brcmnand_cs_reg {
530 BRCMNAND_CS_CFG_EXT = 0,
531 BRCMNAND_CS_CFG,
532 BRCMNAND_CS_ACC_CONTROL,
533 BRCMNAND_CS_TIMING1,
534 BRCMNAND_CS_TIMING2,
535 };
536
537 /* Per chip-select offsets for v7.1 */
538 static const u8 brcmnand_cs_offsets_v71[] = {
539 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
540 [BRCMNAND_CS_CFG_EXT] = 0x04,
541 [BRCMNAND_CS_CFG] = 0x08,
542 [BRCMNAND_CS_TIMING1] = 0x0c,
543 [BRCMNAND_CS_TIMING2] = 0x10,
544 };
545
546 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
547 static const u8 brcmnand_cs_offsets[] = {
548 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
549 [BRCMNAND_CS_CFG_EXT] = 0x04,
550 [BRCMNAND_CS_CFG] = 0x04,
551 [BRCMNAND_CS_TIMING1] = 0x08,
552 [BRCMNAND_CS_TIMING2] = 0x0c,
553 };
554
555 /* Per chip-select offset for <= v5.0 on CS0 only */
556 static const u8 brcmnand_cs_offsets_cs0[] = {
557 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
558 [BRCMNAND_CS_CFG_EXT] = 0x08,
559 [BRCMNAND_CS_CFG] = 0x08,
560 [BRCMNAND_CS_TIMING1] = 0x10,
561 [BRCMNAND_CS_TIMING2] = 0x14,
562 };
563
564 /*
565 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
566 * one config register, but once the bitfields overflowed, newer controllers
567 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
568 */
569 enum {
570 CFG_BLK_ADR_BYTES_SHIFT = 8,
571 CFG_COL_ADR_BYTES_SHIFT = 12,
572 CFG_FUL_ADR_BYTES_SHIFT = 16,
573 CFG_BUS_WIDTH_SHIFT = 23,
574 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
575 CFG_DEVICE_SIZE_SHIFT = 24,
576
577 /* Only for v2.1 */
578 CFG_PAGE_SIZE_SHIFT_v2_1 = 30,
579
580 /* Only for pre-v7.1 (with no CFG_EXT register) */
581 CFG_PAGE_SIZE_SHIFT = 20,
582 CFG_BLK_SIZE_SHIFT = 28,
583
584 /* Only for v7.1+ (with CFG_EXT register) */
585 CFG_EXT_PAGE_SIZE_SHIFT = 0,
586 CFG_EXT_BLK_SIZE_SHIFT = 4,
587 };
588
589 /* BRCMNAND_INTFC_STATUS */
590 enum {
591 INTFC_FLASH_STATUS = GENMASK(7, 0),
592
593 INTFC_ERASED = BIT(27),
594 INTFC_OOB_VALID = BIT(28),
595 INTFC_CACHE_VALID = BIT(29),
596 INTFC_FLASH_READY = BIT(30),
597 INTFC_CTLR_READY = BIT(31),
598 };
599
600 /***********************************************************************
601 * NAND ACC CONTROL bitfield
602 *
603 * Some bits have remained constant throughout hardware revision, while
604 * others have shifted around.
605 ***********************************************************************/
606
607 /* Constant for all versions (where supported) */
608 enum {
609 /* See BRCMNAND_HAS_CACHE_MODE */
610 ACC_CONTROL_CACHE_MODE = BIT(22),
611
612 /* See BRCMNAND_HAS_PREFETCH */
613 ACC_CONTROL_PREFETCH = BIT(23),
614
615 ACC_CONTROL_PAGE_HIT = BIT(24),
616 ACC_CONTROL_WR_PREEMPT = BIT(25),
617 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
618 ACC_CONTROL_RD_ERASED = BIT(27),
619 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
620 ACC_CONTROL_WR_ECC = BIT(30),
621 ACC_CONTROL_RD_ECC = BIT(31),
622 };
623
624 #define ACC_CONTROL_ECC_SHIFT 16
625 /* Only for v7.2 */
626 #define ACC_CONTROL_ECC_EXT_SHIFT 13
627
628 static u8 brcmnand_status(struct brcmnand_host *host);
629
brcmnand_non_mmio_ops(struct brcmnand_controller * ctrl)630 static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
631 {
632 #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)
633 return static_branch_unlikely(&brcmnand_soc_has_ops_key);
634 #else
635 return false;
636 #endif
637 }
638
nand_readreg(struct brcmnand_controller * ctrl,u32 offs)639 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
640 {
641 if (brcmnand_non_mmio_ops(ctrl))
642 return brcmnand_soc_read(ctrl->soc, offs);
643 return brcmnand_readl(ctrl->nand_base + offs);
644 }
645
nand_writereg(struct brcmnand_controller * ctrl,u32 offs,u32 val)646 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
647 u32 val)
648 {
649 if (brcmnand_non_mmio_ops(ctrl))
650 brcmnand_soc_write(ctrl->soc, val, offs);
651 else
652 brcmnand_writel(val, ctrl->nand_base + offs);
653 }
654
brcmnand_revision_init(struct brcmnand_controller * ctrl)655 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
656 {
657 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
658 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
659 static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
660 static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
661 static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
662 static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
663 static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
664
665 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
666
667 /* Only support v2.1+ */
668 if (ctrl->nand_version < 0x0201) {
669 dev_err(ctrl->dev, "version %#x not supported\n",
670 ctrl->nand_version);
671 return -ENODEV;
672 }
673
674 /* Register offsets */
675 if (ctrl->nand_version >= 0x0702)
676 ctrl->reg_offsets = brcmnand_regs_v72;
677 else if (ctrl->nand_version == 0x0701)
678 ctrl->reg_offsets = brcmnand_regs_v71;
679 else if (ctrl->nand_version >= 0x0600)
680 ctrl->reg_offsets = brcmnand_regs_v60;
681 else if (ctrl->nand_version >= 0x0500)
682 ctrl->reg_offsets = brcmnand_regs_v50;
683 else if (ctrl->nand_version >= 0x0303)
684 ctrl->reg_offsets = brcmnand_regs_v33;
685 else if (ctrl->nand_version >= 0x0201)
686 ctrl->reg_offsets = brcmnand_regs_v21;
687
688 /* Chip-select stride */
689 if (ctrl->nand_version >= 0x0701)
690 ctrl->reg_spacing = 0x14;
691 else
692 ctrl->reg_spacing = 0x10;
693
694 /* Per chip-select registers */
695 if (ctrl->nand_version >= 0x0701) {
696 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
697 } else {
698 ctrl->cs_offsets = brcmnand_cs_offsets;
699
700 /* v3.3-5.0 have a different CS0 offset layout */
701 if (ctrl->nand_version >= 0x0303 &&
702 ctrl->nand_version <= 0x0500)
703 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
704 }
705
706 /* Page / block sizes */
707 if (ctrl->nand_version >= 0x0701) {
708 /* >= v7.1 use nice power-of-2 values! */
709 ctrl->max_page_size = 16 * 1024;
710 ctrl->max_block_size = 2 * 1024 * 1024;
711 } else {
712 if (ctrl->nand_version >= 0x0304)
713 ctrl->page_sizes = page_sizes_v3_4;
714 else if (ctrl->nand_version >= 0x0202)
715 ctrl->page_sizes = page_sizes_v2_2;
716 else
717 ctrl->page_sizes = page_sizes_v2_1;
718
719 if (ctrl->nand_version >= 0x0202)
720 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
721 else
722 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
723
724 if (ctrl->nand_version >= 0x0600)
725 ctrl->block_sizes = block_sizes_v6;
726 else if (ctrl->nand_version >= 0x0400)
727 ctrl->block_sizes = block_sizes_v4;
728 else if (ctrl->nand_version >= 0x0202)
729 ctrl->block_sizes = block_sizes_v2_2;
730 else
731 ctrl->block_sizes = block_sizes_v2_1;
732
733 if (ctrl->nand_version < 0x0400) {
734 if (ctrl->nand_version < 0x0202)
735 ctrl->max_page_size = 2048;
736 else
737 ctrl->max_page_size = 4096;
738 ctrl->max_block_size = 512 * 1024;
739 }
740 }
741
742 /* Maximum spare area sector size (per 512B) */
743 if (ctrl->nand_version == 0x0702)
744 ctrl->max_oob = 128;
745 else if (ctrl->nand_version >= 0x0600)
746 ctrl->max_oob = 64;
747 else if (ctrl->nand_version >= 0x0500)
748 ctrl->max_oob = 32;
749 else
750 ctrl->max_oob = 16;
751
752 /* v6.0 and newer (except v6.1) have prefetch support */
753 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
754 ctrl->features |= BRCMNAND_HAS_PREFETCH;
755
756 /*
757 * v6.x has cache mode, but it's implemented differently. Ignore it for
758 * now.
759 */
760 if (ctrl->nand_version >= 0x0700)
761 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
762
763 if (ctrl->nand_version >= 0x0500)
764 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
765
766 if (ctrl->nand_version >= 0x0700)
767 ctrl->features |= BRCMNAND_HAS_WP;
768 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
769 ctrl->features |= BRCMNAND_HAS_WP;
770
771 /* v7.2 has different ecc level shift in the acc register */
772 if (ctrl->nand_version == 0x0702)
773 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT;
774 else
775 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT;
776
777 return 0;
778 }
779
brcmnand_flash_dma_revision_init(struct brcmnand_controller * ctrl)780 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)
781 {
782 /* flash_dma register offsets */
783 if (ctrl->nand_version >= 0x0703)
784 ctrl->flash_dma_offsets = flash_dma_regs_v4;
785 else if (ctrl->nand_version == 0x0602)
786 ctrl->flash_dma_offsets = flash_dma_regs_v0;
787 else
788 ctrl->flash_dma_offsets = flash_dma_regs_v1;
789 }
790
brcmnand_read_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg)791 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
792 enum brcmnand_reg reg)
793 {
794 u16 offs = ctrl->reg_offsets[reg];
795
796 if (offs)
797 return nand_readreg(ctrl, offs);
798 else
799 return 0;
800 }
801
brcmnand_write_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 val)802 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
803 enum brcmnand_reg reg, u32 val)
804 {
805 u16 offs = ctrl->reg_offsets[reg];
806
807 if (offs)
808 nand_writereg(ctrl, offs, val);
809 }
810
brcmnand_rmw_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 mask,unsigned int shift,u32 val)811 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
812 enum brcmnand_reg reg, u32 mask, unsigned
813 int shift, u32 val)
814 {
815 u32 tmp = brcmnand_read_reg(ctrl, reg);
816
817 tmp &= ~mask;
818 tmp |= val << shift;
819 brcmnand_write_reg(ctrl, reg, tmp);
820 }
821
brcmnand_read_fc(struct brcmnand_controller * ctrl,int word)822 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
823 {
824 if (brcmnand_non_mmio_ops(ctrl))
825 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR);
826 return __raw_readl(ctrl->nand_fc + word * 4);
827 }
828
brcmnand_write_fc(struct brcmnand_controller * ctrl,int word,u32 val)829 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
830 int word, u32 val)
831 {
832 if (brcmnand_non_mmio_ops(ctrl))
833 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR);
834 else
835 __raw_writel(val, ctrl->nand_fc + word * 4);
836 }
837
edu_writel(struct brcmnand_controller * ctrl,enum edu_reg reg,u32 val)838 static inline void edu_writel(struct brcmnand_controller *ctrl,
839 enum edu_reg reg, u32 val)
840 {
841 u16 offs = ctrl->edu_offsets[reg];
842
843 brcmnand_writel(val, ctrl->edu_base + offs);
844 }
845
edu_readl(struct brcmnand_controller * ctrl,enum edu_reg reg)846 static inline u32 edu_readl(struct brcmnand_controller *ctrl,
847 enum edu_reg reg)
848 {
849 u16 offs = ctrl->edu_offsets[reg];
850
851 return brcmnand_readl(ctrl->edu_base + offs);
852 }
853
brcmnand_clear_ecc_addr(struct brcmnand_controller * ctrl)854 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
855 {
856
857 /* Clear error addresses */
858 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
859 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
860 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
861 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
862 }
863
brcmnand_get_uncorrecc_addr(struct brcmnand_controller * ctrl)864 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl)
865 {
866 u64 err_addr;
867
868 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR);
869 err_addr |= ((u64)(brcmnand_read_reg(ctrl,
870 BRCMNAND_UNCORR_EXT_ADDR)
871 & 0xffff) << 32);
872
873 return err_addr;
874 }
875
brcmnand_get_correcc_addr(struct brcmnand_controller * ctrl)876 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl)
877 {
878 u64 err_addr;
879
880 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR);
881 err_addr |= ((u64)(brcmnand_read_reg(ctrl,
882 BRCMNAND_CORR_EXT_ADDR)
883 & 0xffff) << 32);
884
885 return err_addr;
886 }
887
brcmnand_set_cmd_addr(struct mtd_info * mtd,u64 addr)888 static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr)
889 {
890 struct nand_chip *chip = mtd_to_nand(mtd);
891 struct brcmnand_host *host = nand_get_controller_data(chip);
892 struct brcmnand_controller *ctrl = host->ctrl;
893
894 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
895 (host->cs << 16) | ((addr >> 32) & 0xffff));
896 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
897 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
898 lower_32_bits(addr));
899 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
900 }
901
brcmnand_cs_offset(struct brcmnand_controller * ctrl,int cs,enum brcmnand_cs_reg reg)902 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
903 enum brcmnand_cs_reg reg)
904 {
905 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
906 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
907 u8 cs_offs;
908
909 if (cs == 0 && ctrl->cs0_offsets)
910 cs_offs = ctrl->cs0_offsets[reg];
911 else
912 cs_offs = ctrl->cs_offsets[reg];
913
914 if (cs && offs_cs1)
915 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
916
917 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
918 }
919
brcmnand_count_corrected(struct brcmnand_controller * ctrl)920 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
921 {
922 if (ctrl->nand_version < 0x0600)
923 return 1;
924 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
925 }
926
brcmnand_wr_corr_thresh(struct brcmnand_host * host,u8 val)927 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
928 {
929 struct brcmnand_controller *ctrl = host->ctrl;
930 unsigned int shift = 0, bits;
931 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
932 int cs = host->cs;
933
934 if (!ctrl->reg_offsets[reg])
935 return;
936
937 if (ctrl->nand_version == 0x0702)
938 bits = 7;
939 else if (ctrl->nand_version >= 0x0600)
940 bits = 6;
941 else if (ctrl->nand_version >= 0x0500)
942 bits = 5;
943 else
944 bits = 4;
945
946 if (ctrl->nand_version >= 0x0702) {
947 if (cs >= 4)
948 reg = BRCMNAND_CORR_THRESHOLD_EXT;
949 shift = (cs % 4) * bits;
950 } else if (ctrl->nand_version >= 0x0600) {
951 if (cs >= 5)
952 reg = BRCMNAND_CORR_THRESHOLD_EXT;
953 shift = (cs % 5) * bits;
954 }
955 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
956 }
957
brcmnand_cmd_shift(struct brcmnand_controller * ctrl)958 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
959 {
960 /* Kludge for the BCMA-based NAND controller which does not actually
961 * shift the command
962 */
963 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl))
964 return 0;
965
966 if (ctrl->nand_version < 0x0602)
967 return 24;
968 return 0;
969 }
970
brcmnand_spare_area_mask(struct brcmnand_controller * ctrl)971 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
972 {
973 if (ctrl->nand_version == 0x0702)
974 return GENMASK(7, 0);
975 else if (ctrl->nand_version >= 0x0600)
976 return GENMASK(6, 0);
977 else if (ctrl->nand_version >= 0x0303)
978 return GENMASK(5, 0);
979 else
980 return GENMASK(4, 0);
981 }
982
brcmnand_ecc_level_mask(struct brcmnand_controller * ctrl)983 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
984 {
985 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
986
987 mask <<= ACC_CONTROL_ECC_SHIFT;
988
989 /* v7.2 includes additional ECC levels */
990 if (ctrl->nand_version == 0x0702)
991 mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT;
992
993 return mask;
994 }
995
brcmnand_set_ecc_enabled(struct brcmnand_host * host,int en)996 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
997 {
998 struct brcmnand_controller *ctrl = host->ctrl;
999 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1000 u32 acc_control = nand_readreg(ctrl, offs);
1001 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
1002
1003 if (en) {
1004 acc_control |= ecc_flags; /* enable RD/WR ECC */
1005 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
1006 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift;
1007 } else {
1008 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
1009 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
1010 }
1011
1012 nand_writereg(ctrl, offs, acc_control);
1013 }
1014
brcmnand_sector_1k_shift(struct brcmnand_controller * ctrl)1015 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
1016 {
1017 if (ctrl->nand_version >= 0x0702)
1018 return 9;
1019 else if (ctrl->nand_version >= 0x0600)
1020 return 7;
1021 else if (ctrl->nand_version >= 0x0500)
1022 return 6;
1023 else
1024 return -1;
1025 }
1026
brcmnand_set_sector_size_1k(struct brcmnand_host * host,int val)1027 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
1028 {
1029 struct brcmnand_controller *ctrl = host->ctrl;
1030 int shift = brcmnand_sector_1k_shift(ctrl);
1031 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1032 BRCMNAND_CS_ACC_CONTROL);
1033 u32 tmp;
1034
1035 if (shift < 0)
1036 return;
1037
1038 tmp = nand_readreg(ctrl, acc_control_offs);
1039 tmp &= ~(1 << shift);
1040 tmp |= (!!val) << shift;
1041 nand_writereg(ctrl, acc_control_offs, tmp);
1042 }
1043
1044 /***********************************************************************
1045 * CS_NAND_SELECT
1046 ***********************************************************************/
1047
1048 enum {
1049 CS_SELECT_NAND_WP = BIT(29),
1050 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
1051 };
1052
bcmnand_ctrl_poll_status(struct brcmnand_host * host,u32 mask,u32 expected_val,unsigned long timeout_ms)1053 static int bcmnand_ctrl_poll_status(struct brcmnand_host *host,
1054 u32 mask, u32 expected_val,
1055 unsigned long timeout_ms)
1056 {
1057 struct brcmnand_controller *ctrl = host->ctrl;
1058 unsigned long limit;
1059 u32 val;
1060
1061 if (!timeout_ms)
1062 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
1063
1064 limit = jiffies + msecs_to_jiffies(timeout_ms);
1065 do {
1066 if (mask & INTFC_FLASH_STATUS)
1067 brcmnand_status(host);
1068
1069 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1070 if ((val & mask) == expected_val)
1071 return 0;
1072
1073 cpu_relax();
1074 } while (time_after(limit, jiffies));
1075
1076 /*
1077 * do a final check after time out in case the CPU was busy and the driver
1078 * did not get enough time to perform the polling to avoid false alarms
1079 */
1080 if (mask & INTFC_FLASH_STATUS)
1081 brcmnand_status(host);
1082
1083 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1084 if ((val & mask) == expected_val)
1085 return 0;
1086
1087 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
1088 expected_val, val & mask);
1089
1090 return -ETIMEDOUT;
1091 }
1092
brcmnand_set_wp(struct brcmnand_controller * ctrl,bool en)1093 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
1094 {
1095 u32 val = en ? CS_SELECT_NAND_WP : 0;
1096
1097 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
1098 }
1099
1100 /***********************************************************************
1101 * Flash DMA
1102 ***********************************************************************/
1103
has_flash_dma(struct brcmnand_controller * ctrl)1104 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
1105 {
1106 return ctrl->flash_dma_base;
1107 }
1108
has_edu(struct brcmnand_controller * ctrl)1109 static inline bool has_edu(struct brcmnand_controller *ctrl)
1110 {
1111 return ctrl->edu_base;
1112 }
1113
use_dma(struct brcmnand_controller * ctrl)1114 static inline bool use_dma(struct brcmnand_controller *ctrl)
1115 {
1116 return has_flash_dma(ctrl) || has_edu(ctrl);
1117 }
1118
disable_ctrl_irqs(struct brcmnand_controller * ctrl)1119 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl)
1120 {
1121 if (ctrl->pio_poll_mode)
1122 return;
1123
1124 if (has_flash_dma(ctrl)) {
1125 ctrl->flash_dma_base = NULL;
1126 disable_irq(ctrl->dma_irq);
1127 }
1128
1129 disable_irq(ctrl->irq);
1130 ctrl->pio_poll_mode = true;
1131 }
1132
flash_dma_buf_ok(const void * buf)1133 static inline bool flash_dma_buf_ok(const void *buf)
1134 {
1135 return buf && !is_vmalloc_addr(buf) &&
1136 likely(IS_ALIGNED((uintptr_t)buf, 4));
1137 }
1138
flash_dma_writel(struct brcmnand_controller * ctrl,enum flash_dma_reg dma_reg,u32 val)1139 static inline void flash_dma_writel(struct brcmnand_controller *ctrl,
1140 enum flash_dma_reg dma_reg, u32 val)
1141 {
1142 u16 offs = ctrl->flash_dma_offsets[dma_reg];
1143
1144 brcmnand_writel(val, ctrl->flash_dma_base + offs);
1145 }
1146
flash_dma_readl(struct brcmnand_controller * ctrl,enum flash_dma_reg dma_reg)1147 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl,
1148 enum flash_dma_reg dma_reg)
1149 {
1150 u16 offs = ctrl->flash_dma_offsets[dma_reg];
1151
1152 return brcmnand_readl(ctrl->flash_dma_base + offs);
1153 }
1154
1155 /* Low-level operation types: command, address, write, or read */
1156 enum brcmnand_llop_type {
1157 LL_OP_CMD,
1158 LL_OP_ADDR,
1159 LL_OP_WR,
1160 LL_OP_RD,
1161 };
1162
1163 /***********************************************************************
1164 * Internal support functions
1165 ***********************************************************************/
1166
is_hamming_ecc(struct brcmnand_controller * ctrl,struct brcmnand_cfg * cfg)1167 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
1168 struct brcmnand_cfg *cfg)
1169 {
1170 if (ctrl->nand_version <= 0x0701)
1171 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
1172 cfg->ecc_level == 15;
1173 else
1174 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
1175 cfg->ecc_level == 15) ||
1176 (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
1177 }
1178
1179 /*
1180 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
1181 * the layout/configuration.
1182 * Returns -ERRCODE on failure.
1183 */
brcmnand_hamming_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1184 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
1185 struct mtd_oob_region *oobregion)
1186 {
1187 struct nand_chip *chip = mtd_to_nand(mtd);
1188 struct brcmnand_host *host = nand_get_controller_data(chip);
1189 struct brcmnand_cfg *cfg = &host->hwcfg;
1190 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1191 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1192
1193 if (section >= sectors)
1194 return -ERANGE;
1195
1196 oobregion->offset = (section * sas) + 6;
1197 oobregion->length = 3;
1198
1199 return 0;
1200 }
1201
brcmnand_hamming_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1202 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
1203 struct mtd_oob_region *oobregion)
1204 {
1205 struct nand_chip *chip = mtd_to_nand(mtd);
1206 struct brcmnand_host *host = nand_get_controller_data(chip);
1207 struct brcmnand_cfg *cfg = &host->hwcfg;
1208 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1209 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1210 u32 next;
1211
1212 if (section > sectors)
1213 return -ERANGE;
1214
1215 next = (section * sas);
1216 if (section < sectors)
1217 next += 6;
1218
1219 if (section) {
1220 oobregion->offset = ((section - 1) * sas) + 9;
1221 } else {
1222 if (cfg->page_size > 512) {
1223 /* Large page NAND uses first 2 bytes for BBI */
1224 oobregion->offset = 2;
1225 } else {
1226 /* Small page NAND uses last byte before ECC for BBI */
1227 oobregion->offset = 0;
1228 next--;
1229 }
1230 }
1231
1232 oobregion->length = next - oobregion->offset;
1233
1234 return 0;
1235 }
1236
1237 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
1238 .ecc = brcmnand_hamming_ooblayout_ecc,
1239 .free = brcmnand_hamming_ooblayout_free,
1240 };
1241
brcmnand_bch_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1242 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
1243 struct mtd_oob_region *oobregion)
1244 {
1245 struct nand_chip *chip = mtd_to_nand(mtd);
1246 struct brcmnand_host *host = nand_get_controller_data(chip);
1247 struct brcmnand_cfg *cfg = &host->hwcfg;
1248 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1249 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1250
1251 if (section >= sectors)
1252 return -ERANGE;
1253
1254 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes;
1255 oobregion->length = chip->ecc.bytes;
1256
1257 return 0;
1258 }
1259
brcmnand_bch_ooblayout_free_lp(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1260 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
1261 struct mtd_oob_region *oobregion)
1262 {
1263 struct nand_chip *chip = mtd_to_nand(mtd);
1264 struct brcmnand_host *host = nand_get_controller_data(chip);
1265 struct brcmnand_cfg *cfg = &host->hwcfg;
1266 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1267 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1268
1269 if (section >= sectors)
1270 return -ERANGE;
1271
1272 if (sas <= chip->ecc.bytes)
1273 return 0;
1274
1275 oobregion->offset = section * sas;
1276 oobregion->length = sas - chip->ecc.bytes;
1277
1278 if (!section) {
1279 oobregion->offset++;
1280 oobregion->length--;
1281 }
1282
1283 return 0;
1284 }
1285
brcmnand_bch_ooblayout_free_sp(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1286 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
1287 struct mtd_oob_region *oobregion)
1288 {
1289 struct nand_chip *chip = mtd_to_nand(mtd);
1290 struct brcmnand_host *host = nand_get_controller_data(chip);
1291 struct brcmnand_cfg *cfg = &host->hwcfg;
1292 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1293
1294 if (section > 1 || sas - chip->ecc.bytes < 6 ||
1295 (section && sas - chip->ecc.bytes == 6))
1296 return -ERANGE;
1297
1298 if (!section) {
1299 oobregion->offset = 0;
1300 oobregion->length = 5;
1301 } else {
1302 oobregion->offset = 6;
1303 oobregion->length = sas - chip->ecc.bytes - 6;
1304 }
1305
1306 return 0;
1307 }
1308
1309 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
1310 .ecc = brcmnand_bch_ooblayout_ecc,
1311 .free = brcmnand_bch_ooblayout_free_lp,
1312 };
1313
1314 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
1315 .ecc = brcmnand_bch_ooblayout_ecc,
1316 .free = brcmnand_bch_ooblayout_free_sp,
1317 };
1318
brcmstb_choose_ecc_layout(struct brcmnand_host * host)1319 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
1320 {
1321 struct brcmnand_cfg *p = &host->hwcfg;
1322 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1323 struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1324 unsigned int ecc_level = p->ecc_level;
1325 int sas = p->spare_area_size << p->sector_size_1k;
1326 int sectors = p->page_size / (512 << p->sector_size_1k);
1327
1328 if (p->sector_size_1k)
1329 ecc_level <<= 1;
1330
1331 if (is_hamming_ecc(host->ctrl, p)) {
1332 ecc->bytes = 3 * sectors;
1333 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
1334 return 0;
1335 }
1336
1337 /*
1338 * CONTROLLER_VERSION:
1339 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1340 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1341 * But we will just be conservative.
1342 */
1343 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1344 if (p->page_size == 512)
1345 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
1346 else
1347 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
1348
1349 if (ecc->bytes >= sas) {
1350 dev_err(&host->pdev->dev,
1351 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1352 ecc->bytes, sas);
1353 return -EINVAL;
1354 }
1355
1356 return 0;
1357 }
1358
brcmnand_wp(struct mtd_info * mtd,int wp)1359 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1360 {
1361 struct nand_chip *chip = mtd_to_nand(mtd);
1362 struct brcmnand_host *host = nand_get_controller_data(chip);
1363 struct brcmnand_controller *ctrl = host->ctrl;
1364
1365 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1366 static int old_wp = -1;
1367 int ret;
1368
1369 if (old_wp != wp) {
1370 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1371 old_wp = wp;
1372 }
1373
1374 /*
1375 * make sure ctrl/flash ready before and after
1376 * changing state of #WP pin
1377 */
1378 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY |
1379 NAND_STATUS_READY,
1380 NAND_CTRL_RDY |
1381 NAND_STATUS_READY, 0);
1382 if (ret)
1383 return;
1384
1385 brcmnand_set_wp(ctrl, wp);
1386 /* force controller operation to update internal copy of NAND chip status */
1387 brcmnand_status(host);
1388 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1389 ret = bcmnand_ctrl_poll_status(host,
1390 NAND_CTRL_RDY |
1391 NAND_STATUS_READY |
1392 NAND_STATUS_WP,
1393 NAND_CTRL_RDY |
1394 NAND_STATUS_READY |
1395 (wp ? 0 : NAND_STATUS_WP), 0);
1396
1397 if (ret)
1398 dev_err_ratelimited(&host->pdev->dev,
1399 "nand #WP expected %s\n",
1400 wp ? "on" : "off");
1401 }
1402 }
1403
1404 /* Helper functions for reading and writing OOB registers */
oob_reg_read(struct brcmnand_controller * ctrl,u32 offs)1405 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1406 {
1407 u16 offset0, offset10, reg_offs;
1408
1409 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1410 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1411
1412 if (offs >= ctrl->max_oob)
1413 return 0x77;
1414
1415 if (offs >= 16 && offset10)
1416 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1417 else
1418 reg_offs = offset0 + (offs & ~0x03);
1419
1420 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1421 }
1422
oob_reg_write(struct brcmnand_controller * ctrl,u32 offs,u32 data)1423 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1424 u32 data)
1425 {
1426 u16 offset0, offset10, reg_offs;
1427
1428 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1429 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1430
1431 if (offs >= ctrl->max_oob)
1432 return;
1433
1434 if (offs >= 16 && offset10)
1435 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1436 else
1437 reg_offs = offset0 + (offs & ~0x03);
1438
1439 nand_writereg(ctrl, reg_offs, data);
1440 }
1441
1442 /*
1443 * read_oob_from_regs - read data from OOB registers
1444 * @ctrl: NAND controller
1445 * @i: sub-page sector index
1446 * @oob: buffer to read to
1447 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1448 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1449 */
read_oob_from_regs(struct brcmnand_controller * ctrl,int i,u8 * oob,int sas,int sector_1k)1450 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1451 int sas, int sector_1k)
1452 {
1453 int tbytes = sas << sector_1k;
1454 int j;
1455
1456 /* Adjust OOB values for 1K sector size */
1457 if (sector_1k && (i & 0x01))
1458 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1459 tbytes = min_t(int, tbytes, ctrl->max_oob);
1460
1461 for (j = 0; j < tbytes; j++)
1462 oob[j] = oob_reg_read(ctrl, j);
1463 return tbytes;
1464 }
1465
1466 /*
1467 * write_oob_to_regs - write data to OOB registers
1468 * @i: sub-page sector index
1469 * @oob: buffer to write from
1470 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1471 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1472 */
write_oob_to_regs(struct brcmnand_controller * ctrl,int i,const u8 * oob,int sas,int sector_1k)1473 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1474 const u8 *oob, int sas, int sector_1k)
1475 {
1476 int tbytes = sas << sector_1k;
1477 int j, k = 0;
1478 u32 last = 0xffffffff;
1479 u8 *plast = (u8 *)&last;
1480
1481 /* Adjust OOB values for 1K sector size */
1482 if (sector_1k && (i & 0x01))
1483 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1484 tbytes = min_t(int, tbytes, ctrl->max_oob);
1485
1486 /*
1487 * tbytes may not be multiple of words. Make sure we don't read out of
1488 * the boundary and stop at last word.
1489 */
1490 for (j = 0; (j + 3) < tbytes; j += 4)
1491 oob_reg_write(ctrl, j,
1492 (oob[j + 0] << 24) |
1493 (oob[j + 1] << 16) |
1494 (oob[j + 2] << 8) |
1495 (oob[j + 3] << 0));
1496
1497 /* handle the remaing bytes */
1498 while (j < tbytes)
1499 plast[k++] = oob[j++];
1500
1501 if (tbytes & 0x3)
1502 oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last));
1503
1504 return tbytes;
1505 }
1506
brcmnand_edu_init(struct brcmnand_controller * ctrl)1507 static void brcmnand_edu_init(struct brcmnand_controller *ctrl)
1508 {
1509 /* initialize edu */
1510 edu_writel(ctrl, EDU_ERR_STATUS, 0);
1511 edu_readl(ctrl, EDU_ERR_STATUS);
1512 edu_writel(ctrl, EDU_DONE, 0);
1513 edu_writel(ctrl, EDU_DONE, 0);
1514 edu_writel(ctrl, EDU_DONE, 0);
1515 edu_writel(ctrl, EDU_DONE, 0);
1516 edu_readl(ctrl, EDU_DONE);
1517 }
1518
1519 /* edu irq */
brcmnand_edu_irq(int irq,void * data)1520 static irqreturn_t brcmnand_edu_irq(int irq, void *data)
1521 {
1522 struct brcmnand_controller *ctrl = data;
1523
1524 if (ctrl->edu_count) {
1525 ctrl->edu_count--;
1526 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK))
1527 udelay(1);
1528 edu_writel(ctrl, EDU_DONE, 0);
1529 edu_readl(ctrl, EDU_DONE);
1530 }
1531
1532 if (ctrl->edu_count) {
1533 ctrl->edu_dram_addr += FC_BYTES;
1534 ctrl->edu_ext_addr += FC_BYTES;
1535
1536 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
1537 edu_readl(ctrl, EDU_DRAM_ADDR);
1538 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
1539 edu_readl(ctrl, EDU_EXT_ADDR);
1540
1541 if (ctrl->oob) {
1542 if (ctrl->edu_cmd == EDU_CMD_READ) {
1543 ctrl->oob += read_oob_from_regs(ctrl,
1544 ctrl->edu_count + 1,
1545 ctrl->oob, ctrl->sas,
1546 ctrl->sector_size_1k);
1547 } else {
1548 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1549 ctrl->edu_ext_addr);
1550 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1551 ctrl->oob += write_oob_to_regs(ctrl,
1552 ctrl->edu_count,
1553 ctrl->oob, ctrl->sas,
1554 ctrl->sector_size_1k);
1555 }
1556 }
1557
1558 mb(); /* flush previous writes */
1559 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
1560 edu_readl(ctrl, EDU_CMD);
1561
1562 return IRQ_HANDLED;
1563 }
1564
1565 complete(&ctrl->edu_done);
1566
1567 return IRQ_HANDLED;
1568 }
1569
brcmnand_ctlrdy_irq(int irq,void * data)1570 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1571 {
1572 struct brcmnand_controller *ctrl = data;
1573
1574 /* Discard all NAND_CTLRDY interrupts during DMA */
1575 if (ctrl->dma_pending)
1576 return IRQ_HANDLED;
1577
1578 /* check if you need to piggy back on the ctrlrdy irq */
1579 if (ctrl->edu_pending) {
1580 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0))
1581 /* Discard interrupts while using dedicated edu irq */
1582 return IRQ_HANDLED;
1583
1584 /* no registered edu irq, call handler */
1585 return brcmnand_edu_irq(irq, data);
1586 }
1587
1588 complete(&ctrl->done);
1589 return IRQ_HANDLED;
1590 }
1591
1592 /* Handle SoC-specific interrupt hardware */
brcmnand_irq(int irq,void * data)1593 static irqreturn_t brcmnand_irq(int irq, void *data)
1594 {
1595 struct brcmnand_controller *ctrl = data;
1596
1597 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1598 return brcmnand_ctlrdy_irq(irq, data);
1599
1600 return IRQ_NONE;
1601 }
1602
brcmnand_dma_irq(int irq,void * data)1603 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1604 {
1605 struct brcmnand_controller *ctrl = data;
1606
1607 complete(&ctrl->dma_done);
1608
1609 return IRQ_HANDLED;
1610 }
1611
brcmnand_send_cmd(struct brcmnand_host * host,int cmd)1612 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1613 {
1614 struct brcmnand_controller *ctrl = host->ctrl;
1615 int ret;
1616 u64 cmd_addr;
1617
1618 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1619
1620 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr);
1621
1622 /*
1623 * If we came here through _panic_write and there is a pending
1624 * command, try to wait for it. If it times out, rather than
1625 * hitting BUG_ON, just return so we don't crash while crashing.
1626 */
1627 if (oops_in_progress) {
1628 if (ctrl->cmd_pending &&
1629 bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0))
1630 return;
1631 } else
1632 BUG_ON(ctrl->cmd_pending != 0);
1633 ctrl->cmd_pending = cmd;
1634
1635 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1636 WARN_ON(ret);
1637
1638 mb(); /* flush previous writes */
1639 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1640 cmd << brcmnand_cmd_shift(ctrl));
1641 }
1642
brcmstb_nand_wait_for_completion(struct nand_chip * chip)1643 static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip)
1644 {
1645 struct brcmnand_host *host = nand_get_controller_data(chip);
1646 struct brcmnand_controller *ctrl = host->ctrl;
1647 struct mtd_info *mtd = nand_to_mtd(chip);
1648 bool err = false;
1649 int sts;
1650
1651 if (mtd->oops_panic_write || ctrl->irq < 0) {
1652 /* switch to interrupt polling and PIO mode */
1653 disable_ctrl_irqs(ctrl);
1654 sts = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY,
1655 NAND_CTRL_RDY, 0);
1656 err = sts < 0;
1657 } else {
1658 unsigned long timeo = msecs_to_jiffies(
1659 NAND_POLL_STATUS_TIMEOUT_MS);
1660 /* wait for completion interrupt */
1661 sts = wait_for_completion_timeout(&ctrl->done, timeo);
1662 err = !sts;
1663 }
1664
1665 return err;
1666 }
1667
brcmnand_waitfunc(struct nand_chip * chip)1668 static int brcmnand_waitfunc(struct nand_chip *chip)
1669 {
1670 struct brcmnand_host *host = nand_get_controller_data(chip);
1671 struct brcmnand_controller *ctrl = host->ctrl;
1672 bool err = false;
1673
1674 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1675 if (ctrl->cmd_pending)
1676 err = brcmstb_nand_wait_for_completion(chip);
1677
1678 ctrl->cmd_pending = 0;
1679 if (err) {
1680 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1681 >> brcmnand_cmd_shift(ctrl);
1682
1683 dev_err_ratelimited(ctrl->dev,
1684 "timeout waiting for command %#02x\n", cmd);
1685 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1686 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1687 return -ETIMEDOUT;
1688 }
1689 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1690 INTFC_FLASH_STATUS;
1691 }
1692
brcmnand_status(struct brcmnand_host * host)1693 static u8 brcmnand_status(struct brcmnand_host *host)
1694 {
1695 struct nand_chip *chip = &host->chip;
1696 struct mtd_info *mtd = nand_to_mtd(chip);
1697
1698 brcmnand_set_cmd_addr(mtd, 0);
1699 brcmnand_send_cmd(host, CMD_STATUS_READ);
1700
1701 return brcmnand_waitfunc(chip);
1702 }
1703
brcmnand_reset(struct brcmnand_host * host)1704 static u8 brcmnand_reset(struct brcmnand_host *host)
1705 {
1706 struct nand_chip *chip = &host->chip;
1707
1708 brcmnand_send_cmd(host, CMD_FLASH_RESET);
1709
1710 return brcmnand_waitfunc(chip);
1711 }
1712
1713 enum {
1714 LLOP_RE = BIT(16),
1715 LLOP_WE = BIT(17),
1716 LLOP_ALE = BIT(18),
1717 LLOP_CLE = BIT(19),
1718 LLOP_RETURN_IDLE = BIT(31),
1719
1720 LLOP_DATA_MASK = GENMASK(15, 0),
1721 };
1722
brcmnand_low_level_op(struct brcmnand_host * host,enum brcmnand_llop_type type,u32 data,bool last_op)1723 static int brcmnand_low_level_op(struct brcmnand_host *host,
1724 enum brcmnand_llop_type type, u32 data,
1725 bool last_op)
1726 {
1727 struct nand_chip *chip = &host->chip;
1728 struct brcmnand_controller *ctrl = host->ctrl;
1729 u32 tmp;
1730
1731 tmp = data & LLOP_DATA_MASK;
1732 switch (type) {
1733 case LL_OP_CMD:
1734 tmp |= LLOP_WE | LLOP_CLE;
1735 break;
1736 case LL_OP_ADDR:
1737 /* WE | ALE */
1738 tmp |= LLOP_WE | LLOP_ALE;
1739 break;
1740 case LL_OP_WR:
1741 /* WE */
1742 tmp |= LLOP_WE;
1743 break;
1744 case LL_OP_RD:
1745 /* RE */
1746 tmp |= LLOP_RE;
1747 break;
1748 }
1749 if (last_op)
1750 /* RETURN_IDLE */
1751 tmp |= LLOP_RETURN_IDLE;
1752
1753 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1754
1755 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1756 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1757
1758 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1759 return brcmnand_waitfunc(chip);
1760 }
1761
1762 /*
1763 * Kick EDU engine
1764 */
brcmnand_edu_trans(struct brcmnand_host * host,u64 addr,u32 * buf,u8 * oob,u32 len,u8 cmd)1765 static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1766 u8 *oob, u32 len, u8 cmd)
1767 {
1768 struct brcmnand_controller *ctrl = host->ctrl;
1769 struct brcmnand_cfg *cfg = &host->hwcfg;
1770 unsigned long timeo = msecs_to_jiffies(200);
1771 int ret = 0;
1772 int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
1773 u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE);
1774 unsigned int trans = len >> FC_SHIFT;
1775 dma_addr_t pa;
1776
1777 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ?
1778 "read" : "write"), buf, oob);
1779
1780 pa = dma_map_single(ctrl->dev, buf, len, dir);
1781 if (dma_mapping_error(ctrl->dev, pa)) {
1782 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n");
1783 return -ENOMEM;
1784 }
1785
1786 ctrl->edu_pending = true;
1787 ctrl->edu_dram_addr = pa;
1788 ctrl->edu_ext_addr = addr;
1789 ctrl->edu_cmd = edu_cmd;
1790 ctrl->edu_count = trans;
1791 ctrl->sas = cfg->spare_area_size;
1792 ctrl->oob = oob;
1793
1794 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
1795 edu_readl(ctrl, EDU_DRAM_ADDR);
1796 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
1797 edu_readl(ctrl, EDU_EXT_ADDR);
1798 edu_writel(ctrl, EDU_LENGTH, FC_BYTES);
1799 edu_readl(ctrl, EDU_LENGTH);
1800
1801 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) {
1802 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1803 ctrl->edu_ext_addr);
1804 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1805 ctrl->oob += write_oob_to_regs(ctrl,
1806 1,
1807 ctrl->oob, ctrl->sas,
1808 ctrl->sector_size_1k);
1809 }
1810
1811 /* Start edu engine */
1812 mb(); /* flush previous writes */
1813 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
1814 edu_readl(ctrl, EDU_CMD);
1815
1816 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) {
1817 dev_err(ctrl->dev,
1818 "timeout waiting for EDU; status %#x, error status %#x\n",
1819 edu_readl(ctrl, EDU_STATUS),
1820 edu_readl(ctrl, EDU_ERR_STATUS));
1821 }
1822
1823 dma_unmap_single(ctrl->dev, pa, len, dir);
1824
1825 /* read last subpage oob */
1826 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) {
1827 ctrl->oob += read_oob_from_regs(ctrl,
1828 1,
1829 ctrl->oob, ctrl->sas,
1830 ctrl->sector_size_1k);
1831 }
1832
1833 /* for program page check NAND status */
1834 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1835 INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) &&
1836 edu_cmd == EDU_CMD_WRITE) {
1837 dev_info(ctrl->dev, "program failed at %llx\n",
1838 (unsigned long long)addr);
1839 ret = -EIO;
1840 }
1841
1842 /* Make sure the EDU status is clean */
1843 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE)
1844 dev_warn(ctrl->dev, "EDU still active: %#x\n",
1845 edu_readl(ctrl, EDU_STATUS));
1846
1847 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) {
1848 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n",
1849 (unsigned long long)addr);
1850 ret = -EIO;
1851 }
1852
1853 ctrl->edu_pending = false;
1854 brcmnand_edu_init(ctrl);
1855 edu_writel(ctrl, EDU_STOP, 0); /* force stop */
1856 edu_readl(ctrl, EDU_STOP);
1857
1858 if (!ret && edu_cmd == EDU_CMD_READ) {
1859 u64 err_addr = 0;
1860
1861 /*
1862 * check for ECC errors here, subpage ECC errors are
1863 * retained in ECC error address register
1864 */
1865 err_addr = brcmnand_get_uncorrecc_addr(ctrl);
1866 if (!err_addr) {
1867 err_addr = brcmnand_get_correcc_addr(ctrl);
1868 if (err_addr)
1869 ret = -EUCLEAN;
1870 } else
1871 ret = -EBADMSG;
1872 }
1873
1874 return ret;
1875 }
1876
1877 /*
1878 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1879 * following ahead of time:
1880 * - Is this descriptor the beginning or end of a linked list?
1881 * - What is the (DMA) address of the next descriptor in the linked list?
1882 */
brcmnand_fill_dma_desc(struct brcmnand_host * host,struct brcm_nand_dma_desc * desc,u64 addr,dma_addr_t buf,u32 len,u8 dma_cmd,bool begin,bool end,dma_addr_t next_desc)1883 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1884 struct brcm_nand_dma_desc *desc, u64 addr,
1885 dma_addr_t buf, u32 len, u8 dma_cmd,
1886 bool begin, bool end,
1887 dma_addr_t next_desc)
1888 {
1889 memset(desc, 0, sizeof(*desc));
1890 /* Descriptors are written in native byte order (wordwise) */
1891 desc->next_desc = lower_32_bits(next_desc);
1892 desc->next_desc_ext = upper_32_bits(next_desc);
1893 desc->cmd_irq = (dma_cmd << 24) |
1894 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1895 (!!begin) | ((!!end) << 1); /* head, tail */
1896 #ifdef CONFIG_CPU_BIG_ENDIAN
1897 desc->cmd_irq |= 0x01 << 12;
1898 #endif
1899 desc->dram_addr = lower_32_bits(buf);
1900 desc->dram_addr_ext = upper_32_bits(buf);
1901 desc->tfr_len = len;
1902 desc->total_len = len;
1903 desc->flash_addr = lower_32_bits(addr);
1904 desc->flash_addr_ext = upper_32_bits(addr);
1905 desc->cs = host->cs;
1906 desc->status_valid = 0x01;
1907 return 0;
1908 }
1909
1910 /*
1911 * Kick the FLASH_DMA engine, with a given DMA descriptor
1912 */
brcmnand_dma_run(struct brcmnand_host * host,dma_addr_t desc)1913 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1914 {
1915 struct brcmnand_controller *ctrl = host->ctrl;
1916 unsigned long timeo = msecs_to_jiffies(100);
1917
1918 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1919 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1920 if (ctrl->nand_version > 0x0602) {
1921 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT,
1922 upper_32_bits(desc));
1923 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1924 }
1925
1926 /* Start FLASH_DMA engine */
1927 ctrl->dma_pending = true;
1928 mb(); /* flush previous writes */
1929 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1930
1931 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1932 dev_err(ctrl->dev,
1933 "timeout waiting for DMA; status %#x, error status %#x\n",
1934 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1935 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1936 }
1937 ctrl->dma_pending = false;
1938 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1939 }
1940
brcmnand_dma_trans(struct brcmnand_host * host,u64 addr,u32 * buf,u8 * oob,u32 len,u8 dma_cmd)1941 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1942 u8 *oob, u32 len, u8 dma_cmd)
1943 {
1944 struct brcmnand_controller *ctrl = host->ctrl;
1945 dma_addr_t buf_pa;
1946 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1947
1948 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1949 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1950 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1951 return -ENOMEM;
1952 }
1953
1954 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1955 dma_cmd, true, true, 0);
1956
1957 brcmnand_dma_run(host, ctrl->dma_pa);
1958
1959 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1960
1961 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1962 return -EBADMSG;
1963 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1964 return -EUCLEAN;
1965
1966 return 0;
1967 }
1968
1969 /*
1970 * Assumes proper CS is already set
1971 */
brcmnand_read_by_pio(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob,u64 * err_addr)1972 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1973 u64 addr, unsigned int trans, u32 *buf,
1974 u8 *oob, u64 *err_addr)
1975 {
1976 struct brcmnand_host *host = nand_get_controller_data(chip);
1977 struct brcmnand_controller *ctrl = host->ctrl;
1978 int i, j, ret = 0;
1979
1980 brcmnand_clear_ecc_addr(ctrl);
1981
1982 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1983 brcmnand_set_cmd_addr(mtd, addr);
1984 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1985 brcmnand_send_cmd(host, CMD_PAGE_READ);
1986 brcmnand_waitfunc(chip);
1987
1988 if (likely(buf)) {
1989 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1990
1991 for (j = 0; j < FC_WORDS; j++, buf++)
1992 *buf = brcmnand_read_fc(ctrl, j);
1993
1994 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1995 }
1996
1997 if (oob)
1998 oob += read_oob_from_regs(ctrl, i, oob,
1999 mtd->oobsize / trans,
2000 host->hwcfg.sector_size_1k);
2001
2002 if (ret != -EBADMSG) {
2003 *err_addr = brcmnand_get_uncorrecc_addr(ctrl);
2004
2005 if (*err_addr)
2006 ret = -EBADMSG;
2007 }
2008
2009 if (!ret) {
2010 *err_addr = brcmnand_get_correcc_addr(ctrl);
2011
2012 if (*err_addr)
2013 ret = -EUCLEAN;
2014 }
2015 }
2016
2017 return ret;
2018 }
2019
2020 /*
2021 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
2022 * error
2023 *
2024 * Because the HW ECC signals an ECC error if an erase paged has even a single
2025 * bitflip, we must check each ECC error to see if it is actually an erased
2026 * page with bitflips, not a truly corrupted page.
2027 *
2028 * On a real error, return a negative error code (-EBADMSG for ECC error), and
2029 * buf will contain raw data.
2030 * Otherwise, buf gets filled with 0xffs and return the maximum number of
2031 * bitflips-per-ECC-sector to the caller.
2032 *
2033 */
brcmstb_nand_verify_erased_page(struct mtd_info * mtd,struct nand_chip * chip,void * buf,u64 addr)2034 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
2035 struct nand_chip *chip, void *buf, u64 addr)
2036 {
2037 struct mtd_oob_region ecc;
2038 int i;
2039 int bitflips = 0;
2040 int page = addr >> chip->page_shift;
2041 int ret;
2042 void *ecc_bytes;
2043 void *ecc_chunk;
2044
2045 if (!buf)
2046 buf = nand_get_data_buf(chip);
2047
2048 /* read without ecc for verification */
2049 ret = chip->ecc.read_page_raw(chip, buf, true, page);
2050 if (ret)
2051 return ret;
2052
2053 for (i = 0; i < chip->ecc.steps; i++) {
2054 ecc_chunk = buf + chip->ecc.size * i;
2055
2056 mtd_ooblayout_ecc(mtd, i, &ecc);
2057 ecc_bytes = chip->oob_poi + ecc.offset;
2058
2059 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
2060 ecc_bytes, ecc.length,
2061 NULL, 0,
2062 chip->ecc.strength);
2063 if (ret < 0)
2064 return ret;
2065
2066 bitflips = max(bitflips, ret);
2067 }
2068
2069 return bitflips;
2070 }
2071
brcmnand_read(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob)2072 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
2073 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
2074 {
2075 struct brcmnand_host *host = nand_get_controller_data(chip);
2076 struct brcmnand_controller *ctrl = host->ctrl;
2077 u64 err_addr = 0;
2078 int err;
2079 bool retry = true;
2080 bool edu_err = false;
2081
2082 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
2083
2084 try_dmaread:
2085 brcmnand_clear_ecc_addr(ctrl);
2086
2087 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) &&
2088 flash_dma_buf_ok(buf)) {
2089 err = ctrl->dma_trans(host, addr, buf, oob,
2090 trans * FC_BYTES,
2091 CMD_PAGE_READ);
2092
2093 if (err) {
2094 if (mtd_is_bitflip_or_eccerr(err))
2095 err_addr = addr;
2096 else
2097 return -EIO;
2098 }
2099
2100 if (has_edu(ctrl) && err_addr)
2101 edu_err = true;
2102
2103 } else {
2104 if (oob)
2105 memset(oob, 0x99, mtd->oobsize);
2106
2107 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
2108 oob, &err_addr);
2109 }
2110
2111 if (mtd_is_eccerr(err)) {
2112 /*
2113 * On controller version and 7.0, 7.1 , DMA read after a
2114 * prior PIO read that reported uncorrectable error,
2115 * the DMA engine captures this error following DMA read
2116 * cleared only on subsequent DMA read, so just retry once
2117 * to clear a possible false error reported for current DMA
2118 * read
2119 */
2120 if ((ctrl->nand_version == 0x0700) ||
2121 (ctrl->nand_version == 0x0701)) {
2122 if (retry) {
2123 retry = false;
2124 goto try_dmaread;
2125 }
2126 }
2127
2128 /*
2129 * Controller version 7.2 has hw encoder to detect erased page
2130 * bitflips, apply sw verification for older controllers only
2131 */
2132 if (ctrl->nand_version < 0x0702) {
2133 err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
2134 addr);
2135 /* erased page bitflips corrected */
2136 if (err >= 0)
2137 return err;
2138 }
2139
2140 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
2141 (unsigned long long)err_addr);
2142 mtd->ecc_stats.failed++;
2143 /* NAND layer expects zero on ECC errors */
2144 return 0;
2145 }
2146
2147 if (mtd_is_bitflip(err)) {
2148 unsigned int corrected = brcmnand_count_corrected(ctrl);
2149
2150 /* in case of EDU correctable error we read again using PIO */
2151 if (edu_err)
2152 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
2153 oob, &err_addr);
2154
2155 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
2156 (unsigned long long)err_addr);
2157 mtd->ecc_stats.corrected += corrected;
2158 /* Always exceed the software-imposed threshold */
2159 return max(mtd->bitflip_threshold, corrected);
2160 }
2161
2162 return 0;
2163 }
2164
brcmnand_read_page(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2165 static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf,
2166 int oob_required, int page)
2167 {
2168 struct mtd_info *mtd = nand_to_mtd(chip);
2169 struct brcmnand_host *host = nand_get_controller_data(chip);
2170 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
2171 u64 addr = (u64)page << chip->page_shift;
2172
2173 host->last_addr = addr;
2174
2175 return brcmnand_read(mtd, chip, host->last_addr,
2176 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
2177 }
2178
brcmnand_read_page_raw(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2179 static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
2180 int oob_required, int page)
2181 {
2182 struct brcmnand_host *host = nand_get_controller_data(chip);
2183 struct mtd_info *mtd = nand_to_mtd(chip);
2184 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
2185 int ret;
2186 u64 addr = (u64)page << chip->page_shift;
2187
2188 host->last_addr = addr;
2189
2190 brcmnand_set_ecc_enabled(host, 0);
2191 ret = brcmnand_read(mtd, chip, host->last_addr,
2192 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
2193 brcmnand_set_ecc_enabled(host, 1);
2194 return ret;
2195 }
2196
brcmnand_read_oob(struct nand_chip * chip,int page)2197 static int brcmnand_read_oob(struct nand_chip *chip, int page)
2198 {
2199 struct mtd_info *mtd = nand_to_mtd(chip);
2200
2201 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
2202 mtd->writesize >> FC_SHIFT,
2203 NULL, (u8 *)chip->oob_poi);
2204 }
2205
brcmnand_read_oob_raw(struct nand_chip * chip,int page)2206 static int brcmnand_read_oob_raw(struct nand_chip *chip, int page)
2207 {
2208 struct mtd_info *mtd = nand_to_mtd(chip);
2209 struct brcmnand_host *host = nand_get_controller_data(chip);
2210
2211 brcmnand_set_ecc_enabled(host, 0);
2212 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
2213 mtd->writesize >> FC_SHIFT,
2214 NULL, (u8 *)chip->oob_poi);
2215 brcmnand_set_ecc_enabled(host, 1);
2216 return 0;
2217 }
2218
brcmnand_write(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,const u32 * buf,u8 * oob)2219 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
2220 u64 addr, const u32 *buf, u8 *oob)
2221 {
2222 struct brcmnand_host *host = nand_get_controller_data(chip);
2223 struct brcmnand_controller *ctrl = host->ctrl;
2224 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
2225 int status, ret = 0;
2226
2227 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
2228
2229 if (unlikely((unsigned long)buf & 0x03)) {
2230 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
2231 buf = (u32 *)((unsigned long)buf & ~0x03);
2232 }
2233
2234 brcmnand_wp(mtd, 0);
2235
2236 for (i = 0; i < ctrl->max_oob; i += 4)
2237 oob_reg_write(ctrl, i, 0xffffffff);
2238
2239 if (mtd->oops_panic_write)
2240 /* switch to interrupt polling and PIO mode */
2241 disable_ctrl_irqs(ctrl);
2242
2243 if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) {
2244 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize,
2245 CMD_PROGRAM_PAGE))
2246
2247 ret = -EIO;
2248
2249 goto out;
2250 }
2251
2252 for (i = 0; i < trans; i++, addr += FC_BYTES) {
2253 /* full address MUST be set before populating FC */
2254 brcmnand_set_cmd_addr(mtd, addr);
2255
2256 if (buf) {
2257 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
2258
2259 for (j = 0; j < FC_WORDS; j++, buf++)
2260 brcmnand_write_fc(ctrl, j, *buf);
2261
2262 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
2263 } else if (oob) {
2264 for (j = 0; j < FC_WORDS; j++)
2265 brcmnand_write_fc(ctrl, j, 0xffffffff);
2266 }
2267
2268 if (oob) {
2269 oob += write_oob_to_regs(ctrl, i, oob,
2270 mtd->oobsize / trans,
2271 host->hwcfg.sector_size_1k);
2272 }
2273
2274 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
2275 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
2276 status = brcmnand_waitfunc(chip);
2277
2278 if (status & NAND_STATUS_FAIL) {
2279 dev_info(ctrl->dev, "program failed at %llx\n",
2280 (unsigned long long)addr);
2281 ret = -EIO;
2282 goto out;
2283 }
2284 }
2285 out:
2286 brcmnand_wp(mtd, 1);
2287 return ret;
2288 }
2289
brcmnand_write_page(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2290 static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf,
2291 int oob_required, int page)
2292 {
2293 struct mtd_info *mtd = nand_to_mtd(chip);
2294 struct brcmnand_host *host = nand_get_controller_data(chip);
2295 void *oob = oob_required ? chip->oob_poi : NULL;
2296 u64 addr = (u64)page << chip->page_shift;
2297
2298 host->last_addr = addr;
2299
2300 return brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
2301 }
2302
brcmnand_write_page_raw(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2303 static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
2304 int oob_required, int page)
2305 {
2306 struct mtd_info *mtd = nand_to_mtd(chip);
2307 struct brcmnand_host *host = nand_get_controller_data(chip);
2308 void *oob = oob_required ? chip->oob_poi : NULL;
2309 u64 addr = (u64)page << chip->page_shift;
2310 int ret = 0;
2311
2312 host->last_addr = addr;
2313 brcmnand_set_ecc_enabled(host, 0);
2314 ret = brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
2315 brcmnand_set_ecc_enabled(host, 1);
2316
2317 return ret;
2318 }
2319
brcmnand_write_oob(struct nand_chip * chip,int page)2320 static int brcmnand_write_oob(struct nand_chip *chip, int page)
2321 {
2322 return brcmnand_write(nand_to_mtd(chip), chip,
2323 (u64)page << chip->page_shift, NULL,
2324 chip->oob_poi);
2325 }
2326
brcmnand_write_oob_raw(struct nand_chip * chip,int page)2327 static int brcmnand_write_oob_raw(struct nand_chip *chip, int page)
2328 {
2329 struct mtd_info *mtd = nand_to_mtd(chip);
2330 struct brcmnand_host *host = nand_get_controller_data(chip);
2331 int ret;
2332
2333 brcmnand_set_ecc_enabled(host, 0);
2334 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
2335 (u8 *)chip->oob_poi);
2336 brcmnand_set_ecc_enabled(host, 1);
2337
2338 return ret;
2339 }
2340
brcmnand_exec_instr(struct brcmnand_host * host,int i,const struct nand_operation * op)2341 static int brcmnand_exec_instr(struct brcmnand_host *host, int i,
2342 const struct nand_operation *op)
2343 {
2344 const struct nand_op_instr *instr = &op->instrs[i];
2345 struct brcmnand_controller *ctrl = host->ctrl;
2346 const u8 *out;
2347 bool last_op;
2348 int ret = 0;
2349 u8 *in;
2350
2351 /*
2352 * The controller needs to be aware of the last command in the operation
2353 * (WAITRDY excepted).
2354 */
2355 last_op = ((i == (op->ninstrs - 1)) && (instr->type != NAND_OP_WAITRDY_INSTR)) ||
2356 ((i == (op->ninstrs - 2)) && (op->instrs[i+1].type == NAND_OP_WAITRDY_INSTR));
2357
2358 switch (instr->type) {
2359 case NAND_OP_CMD_INSTR:
2360 brcmnand_low_level_op(host, LL_OP_CMD, instr->ctx.cmd.opcode, last_op);
2361 break;
2362
2363 case NAND_OP_ADDR_INSTR:
2364 for (i = 0; i < instr->ctx.addr.naddrs; i++)
2365 brcmnand_low_level_op(host, LL_OP_ADDR, instr->ctx.addr.addrs[i],
2366 last_op && (i == (instr->ctx.addr.naddrs - 1)));
2367 break;
2368
2369 case NAND_OP_DATA_IN_INSTR:
2370 in = instr->ctx.data.buf.in;
2371 for (i = 0; i < instr->ctx.data.len; i++) {
2372 brcmnand_low_level_op(host, LL_OP_RD, 0,
2373 last_op && (i == (instr->ctx.data.len - 1)));
2374 in[i] = brcmnand_read_reg(host->ctrl, BRCMNAND_LL_RDATA);
2375 }
2376 break;
2377
2378 case NAND_OP_DATA_OUT_INSTR:
2379 out = instr->ctx.data.buf.out;
2380 for (i = 0; i < instr->ctx.data.len; i++)
2381 brcmnand_low_level_op(host, LL_OP_WR, out[i],
2382 last_op && (i == (instr->ctx.data.len - 1)));
2383 break;
2384
2385 case NAND_OP_WAITRDY_INSTR:
2386 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
2387 break;
2388
2389 default:
2390 dev_err(ctrl->dev, "unsupported instruction type: %d\n",
2391 instr->type);
2392 ret = -EINVAL;
2393 break;
2394 }
2395
2396 return ret;
2397 }
2398
brcmnand_op_is_status(const struct nand_operation * op)2399 static int brcmnand_op_is_status(const struct nand_operation *op)
2400 {
2401 if ((op->ninstrs == 2) &&
2402 (op->instrs[0].type == NAND_OP_CMD_INSTR) &&
2403 (op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS) &&
2404 (op->instrs[1].type == NAND_OP_DATA_IN_INSTR))
2405 return 1;
2406
2407 return 0;
2408 }
2409
brcmnand_op_is_reset(const struct nand_operation * op)2410 static int brcmnand_op_is_reset(const struct nand_operation *op)
2411 {
2412 if ((op->ninstrs == 2) &&
2413 (op->instrs[0].type == NAND_OP_CMD_INSTR) &&
2414 (op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET) &&
2415 (op->instrs[1].type == NAND_OP_WAITRDY_INSTR))
2416 return 1;
2417
2418 return 0;
2419 }
2420
brcmnand_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)2421 static int brcmnand_exec_op(struct nand_chip *chip,
2422 const struct nand_operation *op,
2423 bool check_only)
2424 {
2425 struct brcmnand_host *host = nand_get_controller_data(chip);
2426 struct mtd_info *mtd = nand_to_mtd(chip);
2427 u8 *status;
2428 unsigned int i;
2429 int ret = 0;
2430
2431 if (check_only)
2432 return 0;
2433
2434 if (brcmnand_op_is_status(op)) {
2435 status = op->instrs[1].ctx.data.buf.in;
2436 *status = brcmnand_status(host);
2437
2438 return 0;
2439 }
2440 else if (brcmnand_op_is_reset(op)) {
2441 ret = brcmnand_reset(host);
2442 if (ret < 0)
2443 return ret;
2444
2445 brcmnand_wp(mtd, 1);
2446
2447 return 0;
2448 }
2449
2450 if (op->deassert_wp)
2451 brcmnand_wp(mtd, 0);
2452
2453 for (i = 0; i < op->ninstrs; i++) {
2454 ret = brcmnand_exec_instr(host, i, op);
2455 if (ret)
2456 break;
2457 }
2458
2459 if (op->deassert_wp)
2460 brcmnand_wp(mtd, 1);
2461
2462 return ret;
2463 }
2464
2465 /***********************************************************************
2466 * Per-CS setup (1 NAND device)
2467 ***********************************************************************/
2468
brcmnand_set_cfg(struct brcmnand_host * host,struct brcmnand_cfg * cfg)2469 static int brcmnand_set_cfg(struct brcmnand_host *host,
2470 struct brcmnand_cfg *cfg)
2471 {
2472 struct brcmnand_controller *ctrl = host->ctrl;
2473 struct nand_chip *chip = &host->chip;
2474 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2475 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2476 BRCMNAND_CS_CFG_EXT);
2477 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2478 BRCMNAND_CS_ACC_CONTROL);
2479 u8 block_size = 0, page_size = 0, device_size = 0;
2480 u32 tmp;
2481
2482 if (ctrl->block_sizes) {
2483 int i, found;
2484
2485 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
2486 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
2487 block_size = i;
2488 found = 1;
2489 }
2490 if (!found) {
2491 dev_warn(ctrl->dev, "invalid block size %u\n",
2492 cfg->block_size);
2493 return -EINVAL;
2494 }
2495 } else {
2496 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
2497 }
2498
2499 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
2500 cfg->block_size > ctrl->max_block_size)) {
2501 dev_warn(ctrl->dev, "invalid block size %u\n",
2502 cfg->block_size);
2503 block_size = 0;
2504 }
2505
2506 if (ctrl->page_sizes) {
2507 int i, found;
2508
2509 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
2510 if (ctrl->page_sizes[i] == cfg->page_size) {
2511 page_size = i;
2512 found = 1;
2513 }
2514 if (!found) {
2515 dev_warn(ctrl->dev, "invalid page size %u\n",
2516 cfg->page_size);
2517 return -EINVAL;
2518 }
2519 } else {
2520 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
2521 }
2522
2523 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
2524 cfg->page_size > ctrl->max_page_size)) {
2525 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
2526 return -EINVAL;
2527 }
2528
2529 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
2530 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
2531 (unsigned long long)cfg->device_size);
2532 return -EINVAL;
2533 }
2534 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
2535
2536 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
2537 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
2538 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
2539 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
2540 (device_size << CFG_DEVICE_SIZE_SHIFT);
2541 if (cfg_offs == cfg_ext_offs) {
2542 tmp |= (page_size << ctrl->page_size_shift) |
2543 (block_size << CFG_BLK_SIZE_SHIFT);
2544 nand_writereg(ctrl, cfg_offs, tmp);
2545 } else {
2546 nand_writereg(ctrl, cfg_offs, tmp);
2547 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
2548 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
2549 nand_writereg(ctrl, cfg_ext_offs, tmp);
2550 }
2551
2552 tmp = nand_readreg(ctrl, acc_control_offs);
2553 tmp &= ~brcmnand_ecc_level_mask(ctrl);
2554 tmp &= ~brcmnand_spare_area_mask(ctrl);
2555 if (ctrl->nand_version >= 0x0302) {
2556 tmp |= cfg->ecc_level << ctrl->ecc_level_shift;
2557 tmp |= cfg->spare_area_size;
2558 }
2559 nand_writereg(ctrl, acc_control_offs, tmp);
2560
2561 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
2562
2563 /* threshold = ceil(BCH-level * 0.75) */
2564 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2565
2566 return 0;
2567 }
2568
brcmnand_print_cfg(struct brcmnand_host * host,char * buf,struct brcmnand_cfg * cfg)2569 static void brcmnand_print_cfg(struct brcmnand_host *host,
2570 char *buf, struct brcmnand_cfg *cfg)
2571 {
2572 buf += sprintf(buf,
2573 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2574 (unsigned long long)cfg->device_size >> 20,
2575 cfg->block_size >> 10,
2576 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2577 cfg->page_size >= 1024 ? "KiB" : "B",
2578 cfg->spare_area_size, cfg->device_width);
2579
2580 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2581 if (is_hamming_ecc(host->ctrl, cfg))
2582 sprintf(buf, ", Hamming ECC");
2583 else if (cfg->sector_size_1k)
2584 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2585 else
2586 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2587 }
2588
2589 /*
2590 * Minimum number of bytes to address a page. Calculated as:
2591 * roundup(log2(size / page-size) / 8)
2592 *
2593 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2594 * OK because many other things will break if 'size' is irregular...
2595 */
get_blk_adr_bytes(u64 size,u32 writesize)2596 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2597 {
2598 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2599 }
2600
brcmnand_setup_dev(struct brcmnand_host * host)2601 static int brcmnand_setup_dev(struct brcmnand_host *host)
2602 {
2603 struct mtd_info *mtd = nand_to_mtd(&host->chip);
2604 struct nand_chip *chip = &host->chip;
2605 const struct nand_ecc_props *requirements =
2606 nanddev_get_ecc_requirements(&chip->base);
2607 struct nand_memory_organization *memorg =
2608 nanddev_get_memorg(&chip->base);
2609 struct brcmnand_controller *ctrl = host->ctrl;
2610 struct brcmnand_cfg *cfg = &host->hwcfg;
2611 char msg[128];
2612 u32 offs, tmp, oob_sector;
2613 int ret;
2614
2615 memset(cfg, 0, sizeof(*cfg));
2616
2617 ret = of_property_read_u32(nand_get_flash_node(chip),
2618 "brcm,nand-oob-sector-size",
2619 &oob_sector);
2620 if (ret) {
2621 /* Use detected size */
2622 cfg->spare_area_size = mtd->oobsize /
2623 (mtd->writesize >> FC_SHIFT);
2624 } else {
2625 cfg->spare_area_size = oob_sector;
2626 }
2627 if (cfg->spare_area_size > ctrl->max_oob)
2628 cfg->spare_area_size = ctrl->max_oob;
2629 /*
2630 * Set mtd and memorg oobsize to be consistent with controller's
2631 * spare_area_size, as the rest is inaccessible.
2632 */
2633 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2634 memorg->oobsize = mtd->oobsize;
2635
2636 cfg->device_size = mtd->size;
2637 cfg->block_size = mtd->erasesize;
2638 cfg->page_size = mtd->writesize;
2639 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2640 cfg->col_adr_bytes = 2;
2641 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2642
2643 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
2644 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2645 chip->ecc.engine_type);
2646 return -EINVAL;
2647 }
2648
2649 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
2650 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2651 /* Default to Hamming for 1-bit ECC, if unspecified */
2652 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2653 else
2654 /* Otherwise, BCH */
2655 chip->ecc.algo = NAND_ECC_ALGO_BCH;
2656 }
2657
2658 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&
2659 (chip->ecc.strength != 1 || chip->ecc.size != 512)) {
2660 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2661 chip->ecc.strength, chip->ecc.size);
2662 return -EINVAL;
2663 }
2664
2665 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2666 (!chip->ecc.size || !chip->ecc.strength)) {
2667 if (requirements->step_size && requirements->strength) {
2668 /* use detected ECC parameters */
2669 chip->ecc.size = requirements->step_size;
2670 chip->ecc.strength = requirements->strength;
2671 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n",
2672 chip->ecc.size, chip->ecc.strength);
2673 }
2674 }
2675
2676 switch (chip->ecc.size) {
2677 case 512:
2678 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
2679 cfg->ecc_level = 15;
2680 else
2681 cfg->ecc_level = chip->ecc.strength;
2682 cfg->sector_size_1k = 0;
2683 break;
2684 case 1024:
2685 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2686 dev_err(ctrl->dev, "1KB sectors not supported\n");
2687 return -EINVAL;
2688 }
2689 if (chip->ecc.strength & 0x1) {
2690 dev_err(ctrl->dev,
2691 "odd ECC not supported with 1KB sectors\n");
2692 return -EINVAL;
2693 }
2694
2695 cfg->ecc_level = chip->ecc.strength >> 1;
2696 cfg->sector_size_1k = 1;
2697 break;
2698 default:
2699 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2700 chip->ecc.size);
2701 return -EINVAL;
2702 }
2703
2704 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2705 if (mtd->writesize > 512)
2706 cfg->ful_adr_bytes += cfg->col_adr_bytes;
2707 else
2708 cfg->ful_adr_bytes += 1;
2709
2710 ret = brcmnand_set_cfg(host, cfg);
2711 if (ret)
2712 return ret;
2713
2714 brcmnand_set_ecc_enabled(host, 1);
2715
2716 brcmnand_print_cfg(host, msg, cfg);
2717 dev_info(ctrl->dev, "detected %s\n", msg);
2718
2719 /* Configure ACC_CONTROL */
2720 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2721 tmp = nand_readreg(ctrl, offs);
2722 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2723 tmp &= ~ACC_CONTROL_RD_ERASED;
2724
2725 /* We need to turn on Read from erased paged protected by ECC */
2726 if (ctrl->nand_version >= 0x0702)
2727 tmp |= ACC_CONTROL_RD_ERASED;
2728 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2729 if (ctrl->features & BRCMNAND_HAS_PREFETCH)
2730 tmp &= ~ACC_CONTROL_PREFETCH;
2731
2732 nand_writereg(ctrl, offs, tmp);
2733
2734 return 0;
2735 }
2736
brcmnand_attach_chip(struct nand_chip * chip)2737 static int brcmnand_attach_chip(struct nand_chip *chip)
2738 {
2739 struct mtd_info *mtd = nand_to_mtd(chip);
2740 struct brcmnand_host *host = nand_get_controller_data(chip);
2741 int ret;
2742
2743 chip->options |= NAND_NO_SUBPAGE_WRITE;
2744 /*
2745 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2746 * to/from, and have nand_base pass us a bounce buffer instead, as
2747 * needed.
2748 */
2749 chip->options |= NAND_USES_DMA;
2750
2751 if (chip->bbt_options & NAND_BBT_USE_FLASH)
2752 chip->bbt_options |= NAND_BBT_NO_OOB;
2753
2754 if (brcmnand_setup_dev(host))
2755 return -ENXIO;
2756
2757 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2758
2759 /* only use our internal HW threshold */
2760 mtd->bitflip_threshold = 1;
2761
2762 ret = brcmstb_choose_ecc_layout(host);
2763
2764 /* If OOB is written with ECC enabled it will cause ECC errors */
2765 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) {
2766 chip->ecc.write_oob = brcmnand_write_oob_raw;
2767 chip->ecc.read_oob = brcmnand_read_oob_raw;
2768 }
2769
2770 return ret;
2771 }
2772
2773 static const struct nand_controller_ops brcmnand_controller_ops = {
2774 .attach_chip = brcmnand_attach_chip,
2775 .exec_op = brcmnand_exec_op,
2776 };
2777
brcmnand_init_cs(struct brcmnand_host * host,const char * const * part_probe_types)2778 static int brcmnand_init_cs(struct brcmnand_host *host,
2779 const char * const *part_probe_types)
2780 {
2781 struct brcmnand_controller *ctrl = host->ctrl;
2782 struct device *dev = ctrl->dev;
2783 struct mtd_info *mtd;
2784 struct nand_chip *chip;
2785 int ret;
2786 u16 cfg_offs;
2787
2788 mtd = nand_to_mtd(&host->chip);
2789 chip = &host->chip;
2790
2791 nand_set_controller_data(chip, host);
2792 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
2793 host->cs);
2794 if (!mtd->name)
2795 return -ENOMEM;
2796
2797 mtd->owner = THIS_MODULE;
2798 mtd->dev.parent = dev;
2799
2800 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2801 chip->ecc.read_page = brcmnand_read_page;
2802 chip->ecc.write_page = brcmnand_write_page;
2803 chip->ecc.read_page_raw = brcmnand_read_page_raw;
2804 chip->ecc.write_page_raw = brcmnand_write_page_raw;
2805 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2806 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2807 chip->ecc.read_oob = brcmnand_read_oob;
2808 chip->ecc.write_oob = brcmnand_write_oob;
2809
2810 chip->controller = &ctrl->controller;
2811 ctrl->controller.controller_wp = 1;
2812
2813 /*
2814 * The bootloader might have configured 16bit mode but
2815 * NAND READID command only works in 8bit mode. We force
2816 * 8bit mode here to ensure that NAND READID commands works.
2817 */
2818 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2819 nand_writereg(ctrl, cfg_offs,
2820 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
2821
2822 ret = nand_scan(chip, 1);
2823 if (ret)
2824 return ret;
2825
2826 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
2827 if (ret)
2828 nand_cleanup(chip);
2829
2830 return ret;
2831 }
2832
brcmnand_save_restore_cs_config(struct brcmnand_host * host,int restore)2833 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2834 int restore)
2835 {
2836 struct brcmnand_controller *ctrl = host->ctrl;
2837 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2838 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2839 BRCMNAND_CS_CFG_EXT);
2840 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2841 BRCMNAND_CS_ACC_CONTROL);
2842 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2843 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2844
2845 if (restore) {
2846 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2847 if (cfg_offs != cfg_ext_offs)
2848 nand_writereg(ctrl, cfg_ext_offs,
2849 host->hwcfg.config_ext);
2850 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2851 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2852 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2853 } else {
2854 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2855 if (cfg_offs != cfg_ext_offs)
2856 host->hwcfg.config_ext =
2857 nand_readreg(ctrl, cfg_ext_offs);
2858 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2859 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2860 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2861 }
2862 }
2863
brcmnand_suspend(struct device * dev)2864 static int brcmnand_suspend(struct device *dev)
2865 {
2866 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2867 struct brcmnand_host *host;
2868
2869 list_for_each_entry(host, &ctrl->host_list, node)
2870 brcmnand_save_restore_cs_config(host, 0);
2871
2872 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2873 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2874 ctrl->corr_stat_threshold =
2875 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2876
2877 if (has_flash_dma(ctrl))
2878 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2879 else if (has_edu(ctrl))
2880 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
2881
2882 return 0;
2883 }
2884
brcmnand_resume(struct device * dev)2885 static int brcmnand_resume(struct device *dev)
2886 {
2887 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2888 struct brcmnand_host *host;
2889
2890 if (has_flash_dma(ctrl)) {
2891 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2892 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2893 }
2894
2895 if (has_edu(ctrl)) {
2896 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
2897 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config);
2898 edu_readl(ctrl, EDU_CONFIG);
2899 brcmnand_edu_init(ctrl);
2900 }
2901
2902 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2903 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2904 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2905 ctrl->corr_stat_threshold);
2906 if (ctrl->soc) {
2907 /* Clear/re-enable interrupt */
2908 ctrl->soc->ctlrdy_ack(ctrl->soc);
2909 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2910 }
2911
2912 list_for_each_entry(host, &ctrl->host_list, node) {
2913 struct nand_chip *chip = &host->chip;
2914
2915 brcmnand_save_restore_cs_config(host, 1);
2916
2917 /* Reset the chip, required by some chips after power-up */
2918 nand_reset_op(chip);
2919 }
2920
2921 return 0;
2922 }
2923
2924 const struct dev_pm_ops brcmnand_pm_ops = {
2925 .suspend = brcmnand_suspend,
2926 .resume = brcmnand_resume,
2927 };
2928 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2929
2930 static const struct of_device_id __maybe_unused brcmnand_of_match[] = {
2931 { .compatible = "brcm,brcmnand-v2.1" },
2932 { .compatible = "brcm,brcmnand-v2.2" },
2933 { .compatible = "brcm,brcmnand-v4.0" },
2934 { .compatible = "brcm,brcmnand-v5.0" },
2935 { .compatible = "brcm,brcmnand-v6.0" },
2936 { .compatible = "brcm,brcmnand-v6.1" },
2937 { .compatible = "brcm,brcmnand-v6.2" },
2938 { .compatible = "brcm,brcmnand-v7.0" },
2939 { .compatible = "brcm,brcmnand-v7.1" },
2940 { .compatible = "brcm,brcmnand-v7.2" },
2941 { .compatible = "brcm,brcmnand-v7.3" },
2942 {},
2943 };
2944 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2945
2946 /***********************************************************************
2947 * Platform driver setup (per controller)
2948 ***********************************************************************/
brcmnand_edu_setup(struct platform_device * pdev)2949 static int brcmnand_edu_setup(struct platform_device *pdev)
2950 {
2951 struct device *dev = &pdev->dev;
2952 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2953 struct resource *res;
2954 int ret;
2955
2956 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu");
2957 if (res) {
2958 ctrl->edu_base = devm_ioremap_resource(dev, res);
2959 if (IS_ERR(ctrl->edu_base))
2960 return PTR_ERR(ctrl->edu_base);
2961
2962 ctrl->edu_offsets = edu_regs;
2963
2964 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND |
2965 EDU_CONFIG_SWAP_CFG);
2966 edu_readl(ctrl, EDU_CONFIG);
2967
2968 /* initialize edu */
2969 brcmnand_edu_init(ctrl);
2970
2971 ctrl->edu_irq = platform_get_irq_optional(pdev, 1);
2972 if (ctrl->edu_irq < 0) {
2973 dev_warn(dev,
2974 "FLASH EDU enabled, using ctlrdy irq\n");
2975 } else {
2976 ret = devm_request_irq(dev, ctrl->edu_irq,
2977 brcmnand_edu_irq, 0,
2978 "brcmnand-edu", ctrl);
2979 if (ret < 0) {
2980 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n",
2981 ctrl->edu_irq, ret);
2982 return ret;
2983 }
2984
2985 dev_info(dev, "FLASH EDU enabled using irq %u\n",
2986 ctrl->edu_irq);
2987 }
2988 }
2989
2990 return 0;
2991 }
2992
brcmnand_probe(struct platform_device * pdev,struct brcmnand_soc * soc)2993 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2994 {
2995 struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev);
2996 struct device *dev = &pdev->dev;
2997 struct device_node *dn = dev->of_node, *child;
2998 struct brcmnand_controller *ctrl;
2999 struct brcmnand_host *host;
3000 struct resource *res;
3001 int ret;
3002
3003 if (dn && !of_match_node(brcmnand_of_match, dn))
3004 return -ENODEV;
3005
3006 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
3007 if (!ctrl)
3008 return -ENOMEM;
3009
3010 dev_set_drvdata(dev, ctrl);
3011 ctrl->dev = dev;
3012 ctrl->soc = soc;
3013
3014 /* Enable the static key if the soc provides I/O operations indicating
3015 * that a non-memory mapped IO access path must be used
3016 */
3017 if (brcmnand_soc_has_ops(ctrl->soc))
3018 static_branch_enable(&brcmnand_soc_has_ops_key);
3019
3020 init_completion(&ctrl->done);
3021 init_completion(&ctrl->dma_done);
3022 init_completion(&ctrl->edu_done);
3023 nand_controller_init(&ctrl->controller);
3024 ctrl->controller.ops = &brcmnand_controller_ops;
3025 INIT_LIST_HEAD(&ctrl->host_list);
3026
3027 /* NAND register range */
3028 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3029 ctrl->nand_base = devm_ioremap_resource(dev, res);
3030 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc))
3031 return PTR_ERR(ctrl->nand_base);
3032
3033 /* Enable clock before using NAND registers */
3034 ctrl->clk = devm_clk_get(dev, "nand");
3035 if (!IS_ERR(ctrl->clk)) {
3036 ret = clk_prepare_enable(ctrl->clk);
3037 if (ret)
3038 return ret;
3039 } else {
3040 ret = PTR_ERR(ctrl->clk);
3041 if (ret == -EPROBE_DEFER)
3042 return ret;
3043
3044 ctrl->clk = NULL;
3045 }
3046
3047 /* Initialize NAND revision */
3048 ret = brcmnand_revision_init(ctrl);
3049 if (ret)
3050 goto err;
3051
3052 /*
3053 * Most chips have this cache at a fixed offset within 'nand' block.
3054 * Some must specify this region separately.
3055 */
3056 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
3057 if (res) {
3058 ctrl->nand_fc = devm_ioremap_resource(dev, res);
3059 if (IS_ERR(ctrl->nand_fc)) {
3060 ret = PTR_ERR(ctrl->nand_fc);
3061 goto err;
3062 }
3063 } else {
3064 ctrl->nand_fc = ctrl->nand_base +
3065 ctrl->reg_offsets[BRCMNAND_FC_BASE];
3066 }
3067
3068 /* FLASH_DMA */
3069 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
3070 if (res) {
3071 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
3072 if (IS_ERR(ctrl->flash_dma_base)) {
3073 ret = PTR_ERR(ctrl->flash_dma_base);
3074 goto err;
3075 }
3076
3077 /* initialize the dma version */
3078 brcmnand_flash_dma_revision_init(ctrl);
3079
3080 ret = -EIO;
3081 if (ctrl->nand_version >= 0x0700)
3082 ret = dma_set_mask_and_coherent(&pdev->dev,
3083 DMA_BIT_MASK(40));
3084 if (ret)
3085 ret = dma_set_mask_and_coherent(&pdev->dev,
3086 DMA_BIT_MASK(32));
3087 if (ret)
3088 goto err;
3089
3090 /* linked-list and stop on error */
3091 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK);
3092 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
3093
3094 /* Allocate descriptor(s) */
3095 ctrl->dma_desc = dmam_alloc_coherent(dev,
3096 sizeof(*ctrl->dma_desc),
3097 &ctrl->dma_pa, GFP_KERNEL);
3098 if (!ctrl->dma_desc) {
3099 ret = -ENOMEM;
3100 goto err;
3101 }
3102
3103 ctrl->dma_irq = platform_get_irq(pdev, 1);
3104 if ((int)ctrl->dma_irq < 0) {
3105 dev_err(dev, "missing FLASH_DMA IRQ\n");
3106 ret = -ENODEV;
3107 goto err;
3108 }
3109
3110 ret = devm_request_irq(dev, ctrl->dma_irq,
3111 brcmnand_dma_irq, 0, DRV_NAME,
3112 ctrl);
3113 if (ret < 0) {
3114 dev_err(dev, "can't allocate IRQ %d: error %d\n",
3115 ctrl->dma_irq, ret);
3116 goto err;
3117 }
3118
3119 dev_info(dev, "enabling FLASH_DMA\n");
3120 /* set flash dma transfer function to call */
3121 ctrl->dma_trans = brcmnand_dma_trans;
3122 } else {
3123 ret = brcmnand_edu_setup(pdev);
3124 if (ret < 0)
3125 goto err;
3126
3127 if (has_edu(ctrl))
3128 /* set edu transfer function to call */
3129 ctrl->dma_trans = brcmnand_edu_trans;
3130 }
3131
3132 /* Disable automatic device ID config, direct addressing */
3133 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
3134 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
3135 /* Disable XOR addressing */
3136 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
3137
3138 if (ctrl->features & BRCMNAND_HAS_WP) {
3139 /* Permanently disable write protection */
3140 if (wp_on == 2)
3141 brcmnand_set_wp(ctrl, false);
3142 } else {
3143 wp_on = 0;
3144 }
3145
3146 /* IRQ */
3147 ctrl->irq = platform_get_irq_optional(pdev, 0);
3148 if (ctrl->irq > 0) {
3149 /*
3150 * Some SoCs integrate this controller (e.g., its interrupt bits) in
3151 * interesting ways
3152 */
3153 if (soc) {
3154 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
3155 DRV_NAME, ctrl);
3156
3157 /* Enable interrupt */
3158 ctrl->soc->ctlrdy_ack(ctrl->soc);
3159 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
3160 } else {
3161 /* Use standard interrupt infrastructure */
3162 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
3163 DRV_NAME, ctrl);
3164 }
3165 if (ret < 0) {
3166 dev_err(dev, "can't allocate IRQ %d: error %d\n",
3167 ctrl->irq, ret);
3168 goto err;
3169 }
3170 }
3171
3172 for_each_available_child_of_node(dn, child) {
3173 if (of_device_is_compatible(child, "brcm,nandcs")) {
3174
3175 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
3176 if (!host) {
3177 of_node_put(child);
3178 ret = -ENOMEM;
3179 goto err;
3180 }
3181 host->pdev = pdev;
3182 host->ctrl = ctrl;
3183
3184 ret = of_property_read_u32(child, "reg", &host->cs);
3185 if (ret) {
3186 dev_err(dev, "can't get chip-select\n");
3187 devm_kfree(dev, host);
3188 continue;
3189 }
3190
3191 nand_set_flash_node(&host->chip, child);
3192
3193 ret = brcmnand_init_cs(host, NULL);
3194 if (ret) {
3195 if (ret == -EPROBE_DEFER) {
3196 of_node_put(child);
3197 goto err;
3198 }
3199 devm_kfree(dev, host);
3200 continue; /* Try all chip-selects */
3201 }
3202
3203 list_add_tail(&host->node, &ctrl->host_list);
3204 }
3205 }
3206
3207 if (!list_empty(&ctrl->host_list))
3208 return 0;
3209
3210 if (!pd) {
3211 ret = -ENODEV;
3212 goto err;
3213 }
3214
3215 /* If we got there we must have been probing via platform data */
3216 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
3217 if (!host) {
3218 ret = -ENOMEM;
3219 goto err;
3220 }
3221 host->pdev = pdev;
3222 host->ctrl = ctrl;
3223 host->cs = pd->chip_select;
3224 host->chip.ecc.size = pd->ecc_stepsize;
3225 host->chip.ecc.strength = pd->ecc_strength;
3226
3227 ret = brcmnand_init_cs(host, pd->part_probe_types);
3228 if (ret)
3229 goto err;
3230
3231 list_add_tail(&host->node, &ctrl->host_list);
3232
3233 /* No chip-selects could initialize properly */
3234 if (list_empty(&ctrl->host_list)) {
3235 ret = -ENODEV;
3236 goto err;
3237 }
3238
3239 return 0;
3240
3241 err:
3242 clk_disable_unprepare(ctrl->clk);
3243 return ret;
3244
3245 }
3246 EXPORT_SYMBOL_GPL(brcmnand_probe);
3247
brcmnand_remove(struct platform_device * pdev)3248 void brcmnand_remove(struct platform_device *pdev)
3249 {
3250 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
3251 struct brcmnand_host *host;
3252 struct nand_chip *chip;
3253 int ret;
3254
3255 list_for_each_entry(host, &ctrl->host_list, node) {
3256 chip = &host->chip;
3257 ret = mtd_device_unregister(nand_to_mtd(chip));
3258 WARN_ON(ret);
3259 nand_cleanup(chip);
3260 }
3261
3262 clk_disable_unprepare(ctrl->clk);
3263
3264 dev_set_drvdata(&pdev->dev, NULL);
3265 }
3266 EXPORT_SYMBOL_GPL(brcmnand_remove);
3267
3268 MODULE_LICENSE("GPL v2");
3269 MODULE_AUTHOR("Kevin Cernekee");
3270 MODULE_AUTHOR("Brian Norris");
3271 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
3272 MODULE_ALIAS("platform:brcmnand");
3273