1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/export.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13
14 #include <soc/tegra/common.h>
15 #include <soc/tegra/fuse.h>
16
17 #include "fuse.h"
18
19 #define FUSE_SKU_INFO 0x10
20
21 #define ERD_ERR_CONFIG 0x120c
22 #define ERD_MASK_INBAND_ERR 0x1
23
24 #define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
25 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
26 (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
27 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
28 (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
29
30 static void __iomem *apbmisc_base;
31 static bool long_ram_code;
32 static u32 strapping;
33 static u32 chipid;
34
tegra_read_chipid(void)35 u32 tegra_read_chipid(void)
36 {
37 WARN(!chipid, "Tegra APB MISC not yet available\n");
38
39 return chipid;
40 }
41
tegra_get_chip_id(void)42 u8 tegra_get_chip_id(void)
43 {
44 return (tegra_read_chipid() >> 8) & 0xff;
45 }
46
tegra_get_major_rev(void)47 u8 tegra_get_major_rev(void)
48 {
49 return (tegra_read_chipid() >> 4) & 0xf;
50 }
51
tegra_get_minor_rev(void)52 u8 tegra_get_minor_rev(void)
53 {
54 return (tegra_read_chipid() >> 16) & 0xf;
55 }
56
tegra_get_platform(void)57 u8 tegra_get_platform(void)
58 {
59 return (tegra_read_chipid() >> 20) & 0xf;
60 }
61
tegra_is_silicon(void)62 bool tegra_is_silicon(void)
63 {
64 switch (tegra_get_chip_id()) {
65 case TEGRA194:
66 case TEGRA234:
67 case TEGRA241:
68 case TEGRA264:
69 if (tegra_get_platform() == 0)
70 return true;
71
72 return false;
73 }
74
75 /*
76 * Chips prior to Tegra194 have a different way of determining whether
77 * they are silicon or not. Since we never supported simulation on the
78 * older Tegra chips, don't bother extracting the information and just
79 * report that we're running on silicon.
80 */
81 return true;
82 }
83
tegra_read_straps(void)84 u32 tegra_read_straps(void)
85 {
86 WARN(!chipid, "Tegra ABP MISC not yet available\n");
87
88 return strapping;
89 }
90
tegra_read_ram_code(void)91 u32 tegra_read_ram_code(void)
92 {
93 u32 straps = tegra_read_straps();
94
95 if (long_ram_code)
96 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
97 else
98 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
99
100 return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
101 }
102 EXPORT_SYMBOL_GPL(tegra_read_ram_code);
103
104 /*
105 * The function sets ERD(Error Response Disable) bit.
106 * This allows to mask inband errors and always send an
107 * OKAY response from CBB to the master which caused error.
108 */
tegra194_miscreg_mask_serror(void)109 int tegra194_miscreg_mask_serror(void)
110 {
111 if (!apbmisc_base)
112 return -EPROBE_DEFER;
113
114 if (!of_machine_is_compatible("nvidia,tegra194")) {
115 WARN(1, "Only supported for Tegra194 devices!\n");
116 return -EOPNOTSUPP;
117 }
118
119 writel_relaxed(ERD_MASK_INBAND_ERR,
120 apbmisc_base + ERD_ERR_CONFIG);
121
122 return 0;
123 }
124 EXPORT_SYMBOL(tegra194_miscreg_mask_serror);
125
126 static const struct of_device_id apbmisc_match[] __initconst = {
127 { .compatible = "nvidia,tegra20-apbmisc", },
128 { .compatible = "nvidia,tegra186-misc", },
129 { .compatible = "nvidia,tegra194-misc", },
130 { .compatible = "nvidia,tegra234-misc", },
131 { .compatible = "nvidia,tegra264-misc", },
132 {},
133 };
134
tegra_init_revision(void)135 void __init tegra_init_revision(void)
136 {
137 u8 chip_id, minor_rev;
138
139 chip_id = tegra_get_chip_id();
140 minor_rev = tegra_get_minor_rev();
141
142 switch (minor_rev) {
143 case 1:
144 tegra_sku_info.revision = TEGRA_REVISION_A01;
145 break;
146 case 2:
147 tegra_sku_info.revision = TEGRA_REVISION_A02;
148 break;
149 case 3:
150 if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
151 tegra_fuse_read_spare(19)))
152 tegra_sku_info.revision = TEGRA_REVISION_A03p;
153 else
154 tegra_sku_info.revision = TEGRA_REVISION_A03;
155 break;
156 case 4:
157 tegra_sku_info.revision = TEGRA_REVISION_A04;
158 break;
159 default:
160 tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
161 }
162
163 tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
164 tegra_sku_info.platform = tegra_get_platform();
165 }
166
tegra_init_apbmisc_resources(struct resource * apbmisc,struct resource * straps)167 static void tegra_init_apbmisc_resources(struct resource *apbmisc,
168 struct resource *straps)
169 {
170 void __iomem *strapping_base;
171
172 apbmisc_base = ioremap(apbmisc->start, resource_size(apbmisc));
173 if (apbmisc_base)
174 chipid = readl_relaxed(apbmisc_base + 4);
175 else
176 pr_err("failed to map APBMISC registers\n");
177
178 strapping_base = ioremap(straps->start, resource_size(straps));
179 if (strapping_base) {
180 strapping = readl_relaxed(strapping_base);
181 iounmap(strapping_base);
182 } else {
183 pr_err("failed to map strapping options registers\n");
184 }
185 }
186
187 /**
188 * tegra_init_apbmisc - Initializes Tegra APBMISC and Strapping registers.
189 *
190 * This is called during early init as some of the old 32-bit ARM code needs
191 * information from the APBMISC registers very early during boot.
192 */
tegra_init_apbmisc(void)193 void __init tegra_init_apbmisc(void)
194 {
195 struct resource apbmisc, straps;
196 struct device_node *np;
197
198 np = of_find_matching_node(NULL, apbmisc_match);
199 if (!np) {
200 /*
201 * Fall back to legacy initialization for 32-bit ARM only. All
202 * 64-bit ARM device tree files for Tegra are required to have
203 * an APBMISC node.
204 *
205 * This is for backwards-compatibility with old device trees
206 * that didn't contain an APBMISC node.
207 */
208 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
209 /* APBMISC registers (chip revision, ...) */
210 apbmisc.start = 0x70000800;
211 apbmisc.end = 0x70000863;
212 apbmisc.flags = IORESOURCE_MEM;
213
214 /* strapping options */
215 if (of_machine_is_compatible("nvidia,tegra124")) {
216 straps.start = 0x7000e864;
217 straps.end = 0x7000e867;
218 } else {
219 straps.start = 0x70000008;
220 straps.end = 0x7000000b;
221 }
222
223 straps.flags = IORESOURCE_MEM;
224
225 pr_warn("Using APBMISC region %pR\n", &apbmisc);
226 pr_warn("Using strapping options registers %pR\n",
227 &straps);
228 } else {
229 /*
230 * At this point we're not running on Tegra, so play
231 * nice with multi-platform kernels.
232 */
233 return;
234 }
235 } else {
236 /*
237 * Extract information from the device tree if we've found a
238 * matching node.
239 */
240 if (of_address_to_resource(np, 0, &apbmisc) < 0) {
241 pr_err("failed to get APBMISC registers\n");
242 goto put;
243 }
244
245 if (of_address_to_resource(np, 1, &straps) < 0) {
246 pr_err("failed to get strapping options registers\n");
247 goto put;
248 }
249 }
250
251 tegra_init_apbmisc_resources(&apbmisc, &straps);
252 long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
253
254 put:
255 of_node_put(np);
256 }
257
258 #ifdef CONFIG_ACPI
259 static const struct acpi_device_id apbmisc_acpi_match[] = {
260 { "NVDA2010" },
261 { /* sentinel */ }
262 };
263
tegra_acpi_init_apbmisc(void)264 void tegra_acpi_init_apbmisc(void)
265 {
266 struct resource *resources[2] = { NULL };
267 struct resource_entry *rentry;
268 struct acpi_device *adev = NULL;
269 struct list_head resource_list;
270 int rcount = 0;
271 int ret;
272
273 adev = acpi_dev_get_first_match_dev(apbmisc_acpi_match[0].id, NULL, -1);
274 if (!adev)
275 return;
276
277 INIT_LIST_HEAD(&resource_list);
278
279 ret = acpi_dev_get_memory_resources(adev, &resource_list);
280 if (ret < 0) {
281 pr_err("failed to get APBMISC memory resources");
282 goto out_put_acpi_dev;
283 }
284
285 /*
286 * Get required memory resources.
287 *
288 * resources[0]: apbmisc.
289 * resources[1]: straps.
290 */
291 resource_list_for_each_entry(rentry, &resource_list) {
292 if (rcount >= ARRAY_SIZE(resources))
293 break;
294
295 resources[rcount++] = rentry->res;
296 }
297
298 if (!resources[0]) {
299 pr_err("failed to get APBMISC registers\n");
300 goto out_free_resource_list;
301 }
302
303 if (!resources[1]) {
304 pr_err("failed to get strapping options registers\n");
305 goto out_free_resource_list;
306 }
307
308 tegra_init_apbmisc_resources(resources[0], resources[1]);
309
310 out_free_resource_list:
311 acpi_dev_free_resource_list(&resource_list);
312
313 out_put_acpi_dev:
314 acpi_dev_put(adev);
315 }
316 #else
tegra_acpi_init_apbmisc(void)317 void tegra_acpi_init_apbmisc(void)
318 {
319 }
320 #endif
321