1 /*
2 * Copyright (C) 2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 *
7 * Copyright (C) 2010, NVIDIA Corporation
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/of.h>
25
26 #include <asm/hardware/gic.h>
27
28 #include <mach/iomap.h>
29
30 #include "board.h"
31
32 #define ICTLR_CPU_IEP_VFIQ 0x08
33 #define ICTLR_CPU_IEP_FIR 0x14
34 #define ICTLR_CPU_IEP_FIR_SET 0x18
35 #define ICTLR_CPU_IEP_FIR_CLR 0x1c
36
37 #define ICTLR_CPU_IER 0x20
38 #define ICTLR_CPU_IER_SET 0x24
39 #define ICTLR_CPU_IER_CLR 0x28
40 #define ICTLR_CPU_IEP_CLASS 0x2C
41
42 #define ICTLR_COP_IER 0x30
43 #define ICTLR_COP_IER_SET 0x34
44 #define ICTLR_COP_IER_CLR 0x38
45 #define ICTLR_COP_IEP_CLASS 0x3c
46
47 #define NUM_ICTLRS 4
48 #define FIRST_LEGACY_IRQ 32
49
50 static void __iomem *ictlr_reg_base[] = {
51 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
52 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
53 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
54 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
55 };
56
tegra_irq_write_mask(unsigned int irq,unsigned long reg)57 static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
58 {
59 void __iomem *base;
60 u32 mask;
61
62 BUG_ON(irq < FIRST_LEGACY_IRQ ||
63 irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
64
65 base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
66 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
67
68 __raw_writel(mask, base + reg);
69 }
70
tegra_mask(struct irq_data * d)71 static void tegra_mask(struct irq_data *d)
72 {
73 if (d->irq < FIRST_LEGACY_IRQ)
74 return;
75
76 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
77 }
78
tegra_unmask(struct irq_data * d)79 static void tegra_unmask(struct irq_data *d)
80 {
81 if (d->irq < FIRST_LEGACY_IRQ)
82 return;
83
84 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
85 }
86
tegra_ack(struct irq_data * d)87 static void tegra_ack(struct irq_data *d)
88 {
89 if (d->irq < FIRST_LEGACY_IRQ)
90 return;
91
92 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
93 }
94
tegra_eoi(struct irq_data * d)95 static void tegra_eoi(struct irq_data *d)
96 {
97 if (d->irq < FIRST_LEGACY_IRQ)
98 return;
99
100 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
101 }
102
tegra_retrigger(struct irq_data * d)103 static int tegra_retrigger(struct irq_data *d)
104 {
105 if (d->irq < FIRST_LEGACY_IRQ)
106 return 0;
107
108 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
109
110 return 1;
111 }
112
tegra_init_irq(void)113 void __init tegra_init_irq(void)
114 {
115 int i;
116
117 for (i = 0; i < NUM_ICTLRS; i++) {
118 void __iomem *ictlr = ictlr_reg_base[i];
119 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
120 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
121 }
122
123 gic_arch_extn.irq_ack = tegra_ack;
124 gic_arch_extn.irq_eoi = tegra_eoi;
125 gic_arch_extn.irq_mask = tegra_mask;
126 gic_arch_extn.irq_unmask = tegra_unmask;
127 gic_arch_extn.irq_retrigger = tegra_retrigger;
128
129 /*
130 * Check if there is a devicetree present, since the GIC will be
131 * initialized elsewhere under DT.
132 */
133 if (!of_have_populated_dt())
134 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
135 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
136 }
137