1 // SPDX-License-Identifier: GPL-2.0-only 2 // SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. 3 // All rights reserved. 4 // 5 // tegra210_i2s.c - Tegra210 I2S driver 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/of_graph.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <sound/core.h> 16 #include <sound/pcm_params.h> 17 #include <sound/simple_card_utils.h> 18 #include <sound/soc.h> 19 #include "tegra210_i2s.h" 20 #include "tegra_cif.h" 21 22 static const struct reg_default tegra210_i2s_reg_defaults[] = { 23 { TEGRA210_I2S_RX_INT_MASK, 0x00000003 }, 24 { TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 }, 25 { TEGRA210_I2S_TX_INT_MASK, 0x00000003 }, 26 { TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 }, 27 { TEGRA210_I2S_CG, 0x1 }, 28 { TEGRA210_I2S_TIMING, 0x0000001f }, 29 { TEGRA210_I2S_ENABLE, 0x1 }, 30 /* 31 * Below update does not have any effect on Tegra186 and Tegra194. 32 * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update 33 * is required to select i2s4b for it to be functional for I2S 34 * operation. 35 */ 36 { TEGRA210_I2S_CYA, 0x1 }, 37 }; 38 39 static const struct reg_default tegra264_i2s_reg_defaults[] = { 40 { TEGRA210_I2S_RX_INT_MASK, 0x00000003 }, 41 { TEGRA210_I2S_RX_CIF_CTRL, 0x00003f00 }, 42 { TEGRA264_I2S_TX_INT_MASK, 0x00000003 }, 43 { TEGRA264_I2S_TX_CIF_CTRL, 0x00003f00 }, 44 { TEGRA264_I2S_CG, 0x1 }, 45 { TEGRA264_I2S_TIMING, 0x0000001f }, 46 { TEGRA264_I2S_ENABLE, 0x1 }, 47 { TEGRA264_I2S_RX_FIFO_WR_ACCESS_MODE, 0x1 }, 48 { TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE, 0x1 }, 49 }; 50 51 static void tegra210_i2s_set_slot_ctrl(struct tegra210_i2s *i2s, 52 unsigned int total_slots, 53 unsigned int tx_slot_mask, 54 unsigned int rx_slot_mask) 55 { 56 regmap_write(i2s->regmap, TEGRA210_I2S_SLOT_CTRL + i2s->soc_data->i2s_ctrl_offset, 57 total_slots - 1); 58 regmap_write(i2s->regmap, TEGRA210_I2S_TX_SLOT_CTRL + i2s->soc_data->tx_offset, 59 tx_slot_mask); 60 regmap_write(i2s->regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask); 61 } 62 63 static int tegra210_i2s_set_clock_rate(struct device *dev, 64 unsigned int clock_rate) 65 { 66 struct tegra210_i2s *i2s = dev_get_drvdata(dev); 67 unsigned int val; 68 int err; 69 70 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val); 71 72 /* No need to set rates if I2S is being operated in slave */ 73 if (!(val & I2S_CTRL_MASTER_EN)) 74 return 0; 75 76 err = clk_set_rate(i2s->clk_i2s, clock_rate); 77 if (err) { 78 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", 79 clock_rate, err); 80 return err; 81 } 82 83 if (!IS_ERR(i2s->clk_sync_input)) { 84 /* 85 * Other I/O modules in AHUB can use i2s bclk as reference 86 * clock. Below sets sync input clock rate as per bclk, 87 * which can be used as input to other I/O modules. 88 */ 89 err = clk_set_rate(i2s->clk_sync_input, clock_rate); 90 if (err) { 91 dev_err(dev, 92 "can't set I2S sync input rate %u, err = %d\n", 93 clock_rate, err); 94 return err; 95 } 96 } 97 98 return 0; 99 } 100 101 static int tegra210_i2s_sw_reset(struct snd_soc_component *compnt, 102 int stream) 103 { 104 struct device *dev = compnt->dev; 105 struct tegra210_i2s *i2s = dev_get_drvdata(dev); 106 unsigned int reset_mask = I2S_SOFT_RESET_MASK; 107 unsigned int reset_en = I2S_SOFT_RESET_EN; 108 unsigned int reset_reg, cif_reg, stream_reg; 109 unsigned int cif_ctrl, stream_ctrl, i2s_ctrl, val; 110 int err; 111 112 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 113 reset_reg = TEGRA210_I2S_RX_SOFT_RESET; 114 cif_reg = TEGRA210_I2S_RX_CIF_CTRL; 115 stream_reg = TEGRA210_I2S_RX_CTRL; 116 } else { 117 reset_reg = TEGRA210_I2S_TX_SOFT_RESET + i2s->soc_data->tx_offset; 118 cif_reg = TEGRA210_I2S_TX_CIF_CTRL + i2s->soc_data->tx_offset; 119 stream_reg = TEGRA210_I2S_TX_CTRL + i2s->soc_data->tx_offset; 120 } 121 122 /* Store CIF and I2S control values */ 123 regmap_read(i2s->regmap, cif_reg, &cif_ctrl); 124 regmap_read(i2s->regmap, stream_reg, &stream_ctrl); 125 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &i2s_ctrl); 126 127 /* Reset to make sure the previous transactions are clean */ 128 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en); 129 130 err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val, 131 !(val & reset_mask & reset_en), 132 10, 10000); 133 if (err) { 134 dev_err(dev, "timeout: failed to reset I2S for %s\n", 135 snd_pcm_direction_name(stream)); 136 return err; 137 } 138 139 /* Restore CIF and I2S control values */ 140 regmap_write(i2s->regmap, cif_reg, cif_ctrl); 141 regmap_write(i2s->regmap, stream_reg, stream_ctrl); 142 regmap_write(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, i2s_ctrl); 143 144 return 0; 145 } 146 147 static int tegra210_i2s_init(struct snd_soc_dapm_widget *w, 148 struct snd_kcontrol *kcontrol, int event) 149 { 150 struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm); 151 struct device *dev = compnt->dev; 152 struct tegra210_i2s *i2s = dev_get_drvdata(dev); 153 unsigned int val, status_reg; 154 int stream; 155 int err; 156 157 if (w->reg == TEGRA210_I2S_RX_ENABLE) { 158 stream = SNDRV_PCM_STREAM_PLAYBACK; 159 status_reg = TEGRA210_I2S_RX_STATUS; 160 } else if (w->reg == (TEGRA210_I2S_TX_ENABLE + i2s->soc_data->tx_offset)) { 161 stream = SNDRV_PCM_STREAM_CAPTURE; 162 status_reg = TEGRA210_I2S_TX_STATUS + i2s->soc_data->tx_offset; 163 } else { 164 dev_err(dev, "invalid I2S direction register 0x%x\n", w->reg); 165 return -EINVAL; 166 } 167 168 /* Ensure I2S is in disabled state before new session */ 169 err = regmap_read_poll_timeout(i2s->regmap, status_reg, val, 170 !(val & I2S_EN_MASK & I2S_EN), 171 10, 10000); 172 if (err) { 173 dev_err(dev, "timeout: previous I2S %s is still active\n", 174 snd_pcm_direction_name(stream)); 175 return err; 176 } 177 178 return tegra210_i2s_sw_reset(compnt, stream); 179 } 180 181 static int tegra210_i2s_runtime_suspend(struct device *dev) 182 { 183 struct tegra210_i2s *i2s = dev_get_drvdata(dev); 184 185 regcache_cache_only(i2s->regmap, true); 186 regcache_mark_dirty(i2s->regmap); 187 188 clk_disable_unprepare(i2s->clk_i2s); 189 190 return 0; 191 } 192 193 static int tegra210_i2s_runtime_resume(struct device *dev) 194 { 195 struct tegra210_i2s *i2s = dev_get_drvdata(dev); 196 int err; 197 198 err = clk_prepare_enable(i2s->clk_i2s); 199 if (err) { 200 dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err); 201 return err; 202 } 203 204 regcache_cache_only(i2s->regmap, false); 205 regcache_sync(i2s->regmap); 206 207 return 0; 208 } 209 210 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s, 211 unsigned int data_offset) 212 { 213 /* Capture path */ 214 regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL + i2s->soc_data->tx_offset, 215 I2S_CTRL_DATA_OFFSET_MASK, 216 data_offset << I2S_DATA_SHIFT); 217 218 /* Playback path */ 219 regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL, 220 I2S_CTRL_DATA_OFFSET_MASK, 221 data_offset << I2S_DATA_SHIFT); 222 } 223 224 static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai, 225 unsigned int fmt) 226 { 227 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); 228 unsigned int mask, val; 229 230 mask = I2S_CTRL_MASTER_EN_MASK; 231 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 232 case SND_SOC_DAIFMT_BC_FC: 233 val = 0; 234 break; 235 case SND_SOC_DAIFMT_BP_FP: 236 val = I2S_CTRL_MASTER_EN; 237 break; 238 default: 239 dev_err(dai->dev, "invalid clock provider format 0x%x\n", fmt); 240 return -EINVAL; 241 } 242 243 mask |= I2S_CTRL_FRAME_FMT_MASK | I2S_CTRL_LRCK_POL_MASK; 244 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 245 case SND_SOC_DAIFMT_DSP_A: 246 val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE; 247 val |= I2S_CTRL_LRCK_POL_HIGH; 248 tegra210_i2s_set_data_offset(i2s, 1); 249 break; 250 case SND_SOC_DAIFMT_DSP_B: 251 val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE; 252 val |= I2S_CTRL_LRCK_POL_HIGH; 253 tegra210_i2s_set_data_offset(i2s, 0); 254 break; 255 /* I2S mode has data offset of 1 */ 256 case SND_SOC_DAIFMT_I2S: 257 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE; 258 val |= I2S_CTRL_LRCK_POL_LOW; 259 tegra210_i2s_set_data_offset(i2s, 1); 260 break; 261 /* 262 * For RJ mode data offset is dependent on the sample size 263 * and the bclk ratio, and so is set when hw_params is called. 264 */ 265 case SND_SOC_DAIFMT_RIGHT_J: 266 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE; 267 val |= I2S_CTRL_LRCK_POL_HIGH; 268 break; 269 case SND_SOC_DAIFMT_LEFT_J: 270 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE; 271 val |= I2S_CTRL_LRCK_POL_HIGH; 272 tegra210_i2s_set_data_offset(i2s, 0); 273 break; 274 default: 275 dev_err(dai->dev, "invalid I2S frame format 0x%x\n", fmt); 276 return -EINVAL; 277 } 278 279 mask |= I2S_CTRL_EDGE_CTRL_MASK; 280 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 281 case SND_SOC_DAIFMT_NB_NF: 282 val |= I2S_CTRL_EDGE_CTRL_POS_EDGE; 283 break; 284 case SND_SOC_DAIFMT_NB_IF: 285 val |= I2S_CTRL_EDGE_CTRL_POS_EDGE; 286 val ^= I2S_CTRL_LRCK_POL_MASK; 287 break; 288 case SND_SOC_DAIFMT_IB_NF: 289 val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE; 290 break; 291 case SND_SOC_DAIFMT_IB_IF: 292 val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE; 293 val ^= I2S_CTRL_LRCK_POL_MASK; 294 break; 295 default: 296 dev_err(dai->dev, "invalid I2S clock inversion 0x%x\n", fmt); 297 return -EINVAL; 298 } 299 300 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, 301 mask, val); 302 303 i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 304 305 return 0; 306 } 307 308 static int tegra210_i2s_set_tdm_slot(struct snd_soc_dai *dai, 309 unsigned int tx_mask, unsigned int rx_mask, 310 int slots, int slot_width) 311 { 312 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); 313 314 /* Copy the required tx and rx mask */ 315 i2s->tx_mask = (tx_mask > i2s->soc_data->slot_mask) ? 316 i2s->soc_data->slot_mask : tx_mask; 317 i2s->rx_mask = (rx_mask > i2s->soc_data->slot_mask) ? 318 i2s->soc_data->slot_mask : rx_mask; 319 320 return 0; 321 } 322 323 static int tegra210_i2s_get_loopback(struct snd_kcontrol *kcontrol, 324 struct snd_ctl_elem_value *ucontrol) 325 { 326 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 327 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 328 329 ucontrol->value.integer.value[0] = i2s->loopback; 330 331 return 0; 332 } 333 334 static int tegra210_i2s_put_loopback(struct snd_kcontrol *kcontrol, 335 struct snd_ctl_elem_value *ucontrol) 336 { 337 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 338 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 339 int value = ucontrol->value.integer.value[0]; 340 341 if (value == i2s->loopback) 342 return 0; 343 344 i2s->loopback = value; 345 346 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, 347 I2S_CTRL_LPBK_MASK, i2s->loopback << I2S_CTRL_LPBK_SHIFT); 348 349 return 1; 350 } 351 352 static int tegra210_i2s_get_fsync_width(struct snd_kcontrol *kcontrol, 353 struct snd_ctl_elem_value *ucontrol) 354 { 355 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 356 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 357 358 ucontrol->value.integer.value[0] = i2s->fsync_width; 359 360 return 0; 361 } 362 363 static int tegra210_i2s_put_fsync_width(struct snd_kcontrol *kcontrol, 364 struct snd_ctl_elem_value *ucontrol) 365 { 366 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 367 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 368 int value = ucontrol->value.integer.value[0]; 369 370 if (value == i2s->fsync_width) 371 return 0; 372 373 i2s->fsync_width = value; 374 375 /* 376 * Frame sync width is used only for FSYNC modes and not 377 * applicable for LRCK modes. Reset value for this field is "0", 378 * which means the width is one bit clock wide. 379 * The width requirement may depend on the codec and in such 380 * cases mixer control is used to update custom values. A value 381 * of "N" here means, width is "N + 1" bit clock wide. 382 */ 383 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, 384 i2s->soc_data->fsync_width_mask, 385 i2s->fsync_width << i2s->soc_data->fsync_width_shift); 386 387 return 1; 388 } 389 390 static int tegra210_i2s_cget_stereo_to_mono(struct snd_kcontrol *kcontrol, 391 struct snd_ctl_elem_value *ucontrol) 392 { 393 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 394 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 395 396 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH]; 397 398 return 0; 399 } 400 401 static int tegra210_i2s_cput_stereo_to_mono(struct snd_kcontrol *kcontrol, 402 struct snd_ctl_elem_value *ucontrol) 403 { 404 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 405 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 406 unsigned int value = ucontrol->value.enumerated.item[0]; 407 408 if (value == i2s->stereo_to_mono[I2S_TX_PATH]) 409 return 0; 410 411 i2s->stereo_to_mono[I2S_TX_PATH] = value; 412 413 return 1; 414 } 415 416 static int tegra210_i2s_cget_mono_to_stereo(struct snd_kcontrol *kcontrol, 417 struct snd_ctl_elem_value *ucontrol) 418 { 419 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 420 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 421 422 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH]; 423 424 return 0; 425 } 426 427 static int tegra210_i2s_cput_mono_to_stereo(struct snd_kcontrol *kcontrol, 428 struct snd_ctl_elem_value *ucontrol) 429 { 430 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 431 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 432 unsigned int value = ucontrol->value.enumerated.item[0]; 433 434 if (value == i2s->mono_to_stereo[I2S_TX_PATH]) 435 return 0; 436 437 i2s->mono_to_stereo[I2S_TX_PATH] = value; 438 439 return 1; 440 } 441 442 static int tegra210_i2s_pget_stereo_to_mono(struct snd_kcontrol *kcontrol, 443 struct snd_ctl_elem_value *ucontrol) 444 { 445 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 446 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 447 448 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH]; 449 450 return 0; 451 } 452 453 static int tegra210_i2s_pput_stereo_to_mono(struct snd_kcontrol *kcontrol, 454 struct snd_ctl_elem_value *ucontrol) 455 { 456 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 457 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 458 unsigned int value = ucontrol->value.enumerated.item[0]; 459 460 if (value == i2s->stereo_to_mono[I2S_RX_PATH]) 461 return 0; 462 463 i2s->stereo_to_mono[I2S_RX_PATH] = value; 464 465 return 1; 466 } 467 468 static int tegra210_i2s_pget_mono_to_stereo(struct snd_kcontrol *kcontrol, 469 struct snd_ctl_elem_value *ucontrol) 470 { 471 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 472 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 473 474 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH]; 475 476 return 0; 477 } 478 479 static int tegra210_i2s_pput_mono_to_stereo(struct snd_kcontrol *kcontrol, 480 struct snd_ctl_elem_value *ucontrol) 481 { 482 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 483 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 484 unsigned int value = ucontrol->value.enumerated.item[0]; 485 486 if (value == i2s->mono_to_stereo[I2S_RX_PATH]) 487 return 0; 488 489 i2s->mono_to_stereo[I2S_RX_PATH] = value; 490 491 return 1; 492 } 493 494 static int tegra210_i2s_pget_fifo_th(struct snd_kcontrol *kcontrol, 495 struct snd_ctl_elem_value *ucontrol) 496 { 497 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 498 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 499 500 ucontrol->value.integer.value[0] = i2s->rx_fifo_th; 501 502 return 0; 503 } 504 505 static int tegra210_i2s_pput_fifo_th(struct snd_kcontrol *kcontrol, 506 struct snd_ctl_elem_value *ucontrol) 507 { 508 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 509 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 510 int value = ucontrol->value.integer.value[0]; 511 512 if (value == i2s->rx_fifo_th) 513 return 0; 514 515 i2s->rx_fifo_th = value; 516 517 return 1; 518 } 519 520 static int tegra210_i2s_get_bclk_ratio(struct snd_kcontrol *kcontrol, 521 struct snd_ctl_elem_value *ucontrol) 522 { 523 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 524 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 525 526 ucontrol->value.integer.value[0] = i2s->bclk_ratio; 527 528 return 0; 529 } 530 531 static int tegra210_i2s_put_bclk_ratio(struct snd_kcontrol *kcontrol, 532 struct snd_ctl_elem_value *ucontrol) 533 { 534 struct snd_soc_component *compnt = snd_kcontrol_chip(kcontrol); 535 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); 536 int value = ucontrol->value.integer.value[0]; 537 538 if (value == i2s->bclk_ratio) 539 return 0; 540 541 i2s->bclk_ratio = value; 542 543 return 1; 544 } 545 546 static int tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, 547 unsigned int ratio) 548 { 549 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); 550 551 i2s->bclk_ratio = ratio; 552 553 return 0; 554 } 555 556 static int tegra210_i2s_set_timing_params(struct device *dev, 557 unsigned int sample_size, 558 unsigned int srate, 559 unsigned int channels) 560 { 561 struct tegra210_i2s *i2s = dev_get_drvdata(dev); 562 unsigned int val, bit_count, bclk_rate, num_bclk = sample_size; 563 int err; 564 565 if (i2s->bclk_ratio) 566 num_bclk *= i2s->bclk_ratio; 567 568 if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) 569 tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size); 570 571 /* I2S bit clock rate */ 572 bclk_rate = srate * channels * num_bclk; 573 574 err = tegra210_i2s_set_clock_rate(dev, bclk_rate); 575 if (err) { 576 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", 577 bclk_rate, err); 578 return err; 579 } 580 581 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val); 582 583 /* 584 * For LRCK mode, channel bit count depends on number of bit clocks 585 * on the left channel, where as for FSYNC mode bit count depends on 586 * the number of bit clocks in both left and right channels for DSP 587 * mode or the number of bit clocks in one TDM frame. 588 * 589 */ 590 switch (val & I2S_CTRL_FRAME_FMT_MASK) { 591 case I2S_CTRL_FRAME_FMT_LRCK_MODE: 592 bit_count = (bclk_rate / (srate * 2)) - 1; 593 break; 594 case I2S_CTRL_FRAME_FMT_FSYNC_MODE: 595 bit_count = (bclk_rate / srate) - 1; 596 597 tegra210_i2s_set_slot_ctrl(i2s, channels, 598 i2s->tx_mask, i2s->rx_mask); 599 break; 600 default: 601 dev_err(dev, "invalid I2S frame format\n"); 602 return -EINVAL; 603 } 604 605 if (bit_count > I2S_TIMING_CH_BIT_CNT_MASK) { 606 dev_err(dev, "invalid I2S channel bit count %u\n", bit_count); 607 return -EINVAL; 608 } 609 610 regmap_write(i2s->regmap, TEGRA210_I2S_TIMING + i2s->soc_data->i2s_ctrl_offset, 611 bit_count << I2S_TIMING_CH_BIT_CNT_SHIFT); 612 613 return 0; 614 } 615 616 static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream, 617 struct snd_pcm_hw_params *params, 618 struct snd_soc_dai *dai) 619 { 620 struct device *dev = dai->dev; 621 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); 622 unsigned int sample_size, channels, srate, val, reg, path; 623 struct tegra_cif_conf cif_conf; 624 snd_pcm_format_t sample_format; 625 626 memset(&cif_conf, 0, sizeof(struct tegra_cif_conf)); 627 628 channels = params_channels(params); 629 if (channels < 1) { 630 dev_err(dev, "invalid I2S %d channel configuration\n", 631 channels); 632 return -EINVAL; 633 } 634 635 cif_conf.audio_ch = channels; 636 cif_conf.client_ch = channels; 637 if (i2s->client_channels) 638 cif_conf.client_ch = i2s->client_channels; 639 640 /* AHUB CIF Audio bits configs */ 641 switch (params_format(params)) { 642 case SNDRV_PCM_FORMAT_S8: 643 cif_conf.audio_bits = TEGRA_ACIF_BITS_8; 644 break; 645 case SNDRV_PCM_FORMAT_S16_LE: 646 cif_conf.audio_bits = TEGRA_ACIF_BITS_16; 647 break; 648 case SNDRV_PCM_FORMAT_S24_LE: 649 case SNDRV_PCM_FORMAT_S32_LE: 650 cif_conf.audio_bits = TEGRA_ACIF_BITS_32; 651 break; 652 default: 653 dev_err(dev, "unsupported params audio bit format!\n"); 654 return -EOPNOTSUPP; 655 } 656 657 sample_format = params_format(params); 658 if (i2s->client_sample_format >= 0) 659 sample_format = (snd_pcm_format_t)i2s->client_sample_format; 660 661 /* 662 * Format of the I2S for sending/receiving the audio 663 * to/from external device. 664 */ 665 switch (sample_format) { 666 case SNDRV_PCM_FORMAT_S8: 667 val = I2S_BITS_8; 668 sample_size = 8; 669 cif_conf.client_bits = TEGRA_ACIF_BITS_8; 670 break; 671 case SNDRV_PCM_FORMAT_S16_LE: 672 val = I2S_BITS_16; 673 sample_size = 16; 674 cif_conf.client_bits = TEGRA_ACIF_BITS_16; 675 break; 676 case SNDRV_PCM_FORMAT_S24_LE: 677 val = I2S_BITS_24; 678 sample_size = 32; 679 cif_conf.client_bits = TEGRA_ACIF_BITS_24; 680 break; 681 case SNDRV_PCM_FORMAT_S32_LE: 682 val = I2S_BITS_32; 683 sample_size = 32; 684 cif_conf.client_bits = TEGRA_ACIF_BITS_32; 685 break; 686 default: 687 dev_err(dev, "unsupported client bit format!\n"); 688 return -EOPNOTSUPP; 689 } 690 691 /* Program sample size */ 692 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, 693 I2S_CTRL_BIT_SIZE_MASK, val); 694 695 srate = params_rate(params); 696 697 /* For playback I2S RX-CIF and for capture TX-CIF is used */ 698 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 699 path = I2S_RX_PATH; 700 else 701 path = I2S_TX_PATH; 702 703 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 704 unsigned int max_th; 705 706 /* FIFO threshold in terms of frames */ 707 max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1; 708 709 if (i2s->rx_fifo_th > max_th) 710 i2s->rx_fifo_th = max_th; 711 712 cif_conf.threshold = i2s->rx_fifo_th; 713 714 reg = TEGRA210_I2S_RX_CIF_CTRL; 715 } else { 716 reg = TEGRA210_I2S_TX_CIF_CTRL + i2s->soc_data->tx_offset; 717 } 718 719 cif_conf.mono_conv = i2s->mono_to_stereo[path]; 720 cif_conf.stereo_conv = i2s->stereo_to_mono[path]; 721 722 if (i2s->soc_data->max_ch == TEGRA264_I2S_MAX_CHANNEL) 723 tegra264_set_cif(i2s->regmap, reg, &cif_conf); 724 else 725 tegra_set_cif(i2s->regmap, reg, &cif_conf); 726 727 return tegra210_i2s_set_timing_params(dev, sample_size, srate, 728 cif_conf.client_ch); 729 } 730 731 static const struct snd_soc_dai_ops tegra210_i2s_dai_ops = { 732 .set_fmt = tegra210_i2s_set_fmt, 733 .hw_params = tegra210_i2s_hw_params, 734 .set_bclk_ratio = tegra210_i2s_set_dai_bclk_ratio, 735 .set_tdm_slot = tegra210_i2s_set_tdm_slot, 736 }; 737 738 static struct snd_soc_dai_driver tegra210_i2s_dais[] = { 739 { 740 .name = "I2S-CIF", 741 .playback = { 742 .stream_name = "CIF-Playback", 743 .channels_min = 1, 744 .channels_max = 16, 745 .rates = SNDRV_PCM_RATE_8000_192000, 746 .formats = SNDRV_PCM_FMTBIT_S8 | 747 SNDRV_PCM_FMTBIT_S16_LE | 748 SNDRV_PCM_FMTBIT_S24_LE | 749 SNDRV_PCM_FMTBIT_S32_LE, 750 }, 751 .capture = { 752 .stream_name = "CIF-Capture", 753 .channels_min = 1, 754 .channels_max = 16, 755 .rates = SNDRV_PCM_RATE_8000_192000, 756 .formats = SNDRV_PCM_FMTBIT_S8 | 757 SNDRV_PCM_FMTBIT_S16_LE | 758 SNDRV_PCM_FMTBIT_S24_LE | 759 SNDRV_PCM_FMTBIT_S32_LE, 760 }, 761 }, 762 { 763 .name = "I2S-DAP", 764 .playback = { 765 .stream_name = "DAP-Playback", 766 .channels_min = 1, 767 .channels_max = 16, 768 .rates = SNDRV_PCM_RATE_8000_192000, 769 .formats = SNDRV_PCM_FMTBIT_S8 | 770 SNDRV_PCM_FMTBIT_S16_LE | 771 SNDRV_PCM_FMTBIT_S24_LE | 772 SNDRV_PCM_FMTBIT_S32_LE, 773 }, 774 .capture = { 775 .stream_name = "DAP-Capture", 776 .channels_min = 1, 777 .channels_max = 16, 778 .rates = SNDRV_PCM_RATE_8000_192000, 779 .formats = SNDRV_PCM_FMTBIT_S8 | 780 SNDRV_PCM_FMTBIT_S16_LE | 781 SNDRV_PCM_FMTBIT_S24_LE | 782 SNDRV_PCM_FMTBIT_S32_LE, 783 }, 784 .ops = &tegra210_i2s_dai_ops, 785 .symmetric_rate = 1, 786 }, 787 }; 788 789 static const char * const tegra210_i2s_stereo_conv_text[] = { 790 "CH0", "CH1", "AVG", 791 }; 792 793 static const char * const tegra210_i2s_mono_conv_text[] = { 794 "Zero", "Copy", 795 }; 796 797 static const struct soc_enum tegra210_i2s_mono_conv_enum = 798 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_mono_conv_text), 799 tegra210_i2s_mono_conv_text); 800 801 static const struct soc_enum tegra210_i2s_stereo_conv_enum = 802 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_stereo_conv_text), 803 tegra210_i2s_stereo_conv_text); 804 805 static const struct snd_kcontrol_new tegra210_i2s_controls[] = { 806 SOC_SINGLE_EXT("Loopback", 0, 0, 1, 0, tegra210_i2s_get_loopback, 807 tegra210_i2s_put_loopback), 808 SOC_SINGLE_EXT("FSYNC Width", 0, 0, 255, 0, 809 tegra210_i2s_get_fsync_width, 810 tegra210_i2s_put_fsync_width), 811 SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum, 812 tegra210_i2s_cget_stereo_to_mono, 813 tegra210_i2s_cput_stereo_to_mono), 814 SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum, 815 tegra210_i2s_cget_mono_to_stereo, 816 tegra210_i2s_cput_mono_to_stereo), 817 SOC_ENUM_EXT("Playback Stereo To Mono", tegra210_i2s_stereo_conv_enum, 818 tegra210_i2s_pget_mono_to_stereo, 819 tegra210_i2s_pput_mono_to_stereo), 820 SOC_ENUM_EXT("Playback Mono To Stereo", tegra210_i2s_mono_conv_enum, 821 tegra210_i2s_pget_stereo_to_mono, 822 tegra210_i2s_pput_stereo_to_mono), 823 SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1, 824 0, tegra210_i2s_pget_fifo_th, tegra210_i2s_pput_fifo_th), 825 SOC_SINGLE_EXT("BCLK Ratio", 0, 0, INT_MAX, 0, 826 tegra210_i2s_get_bclk_ratio, 827 tegra210_i2s_put_bclk_ratio), 828 }; 829 830 #define TEGRA_I2S_WIDGETS(tx_enable_reg) \ 831 SND_SOC_DAPM_AIF_IN_E("RX", NULL, 0, TEGRA210_I2S_RX_ENABLE, \ 832 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU), \ 833 SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, tx_enable_reg, \ 834 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU), \ 835 SND_SOC_DAPM_MIC("MIC", NULL), \ 836 SND_SOC_DAPM_SPK("SPK", NULL), 837 838 static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = { 839 TEGRA_I2S_WIDGETS(TEGRA210_I2S_TX_ENABLE) 840 }; 841 842 static const struct snd_soc_dapm_widget tegra264_i2s_widgets[] = { 843 TEGRA_I2S_WIDGETS(TEGRA264_I2S_TX_ENABLE) 844 }; 845 846 static const struct snd_soc_dapm_route tegra210_i2s_routes[] = { 847 /* Playback route from XBAR */ 848 { "XBAR-Playback", NULL, "XBAR-TX" }, 849 { "CIF-Playback", NULL, "XBAR-Playback" }, 850 { "RX", NULL, "CIF-Playback" }, 851 { "DAP-Playback", NULL, "RX" }, 852 { "SPK", NULL, "DAP-Playback" }, 853 /* Capture route to XBAR */ 854 { "XBAR-RX", NULL, "XBAR-Capture" }, 855 { "XBAR-Capture", NULL, "CIF-Capture" }, 856 { "CIF-Capture", NULL, "TX" }, 857 { "TX", NULL, "DAP-Capture" }, 858 { "DAP-Capture", NULL, "MIC" }, 859 }; 860 861 static const struct snd_soc_component_driver tegra210_i2s_cmpnt = { 862 .dapm_widgets = tegra210_i2s_widgets, 863 .num_dapm_widgets = ARRAY_SIZE(tegra210_i2s_widgets), 864 .dapm_routes = tegra210_i2s_routes, 865 .num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes), 866 .controls = tegra210_i2s_controls, 867 .num_controls = ARRAY_SIZE(tegra210_i2s_controls), 868 }; 869 870 static const struct snd_soc_component_driver tegra264_i2s_cmpnt = { 871 .dapm_widgets = tegra264_i2s_widgets, 872 .num_dapm_widgets = ARRAY_SIZE(tegra264_i2s_widgets), 873 .dapm_routes = tegra210_i2s_routes, 874 .num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes), 875 .controls = tegra210_i2s_controls, 876 .num_controls = ARRAY_SIZE(tegra210_i2s_controls), 877 }; 878 879 static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg) 880 { 881 switch (reg) { 882 case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET: 883 case TEGRA210_I2S_RX_INT_MASK ... TEGRA210_I2S_RX_CLK_TRIM: 884 case TEGRA210_I2S_TX_ENABLE ... TEGRA210_I2S_TX_SOFT_RESET: 885 case TEGRA210_I2S_TX_INT_MASK ... TEGRA210_I2S_TX_CLK_TRIM: 886 case TEGRA210_I2S_ENABLE ... TEGRA210_I2S_CG: 887 case TEGRA210_I2S_CTRL ... TEGRA210_I2S_CYA: 888 return true; 889 default: 890 return false; 891 } 892 } 893 894 static bool tegra210_i2s_rd_reg(struct device *dev, unsigned int reg) 895 { 896 if (tegra210_i2s_wr_reg(dev, reg)) 897 return true; 898 899 switch (reg) { 900 case TEGRA210_I2S_RX_STATUS: 901 case TEGRA210_I2S_RX_INT_STATUS: 902 case TEGRA210_I2S_RX_CIF_FIFO_STATUS: 903 case TEGRA210_I2S_TX_STATUS: 904 case TEGRA210_I2S_TX_INT_STATUS: 905 case TEGRA210_I2S_TX_CIF_FIFO_STATUS: 906 case TEGRA210_I2S_STATUS: 907 case TEGRA210_I2S_INT_STATUS: 908 return true; 909 default: 910 return false; 911 } 912 } 913 914 static bool tegra210_i2s_volatile_reg(struct device *dev, unsigned int reg) 915 { 916 switch (reg) { 917 case TEGRA210_I2S_RX_STATUS: 918 case TEGRA210_I2S_RX_INT_STATUS: 919 case TEGRA210_I2S_RX_CIF_FIFO_STATUS: 920 case TEGRA210_I2S_TX_STATUS: 921 case TEGRA210_I2S_TX_INT_STATUS: 922 case TEGRA210_I2S_TX_CIF_FIFO_STATUS: 923 case TEGRA210_I2S_STATUS: 924 case TEGRA210_I2S_INT_STATUS: 925 case TEGRA210_I2S_RX_SOFT_RESET: 926 case TEGRA210_I2S_TX_SOFT_RESET: 927 return true; 928 default: 929 return false; 930 } 931 } 932 933 static bool tegra264_i2s_wr_reg(struct device *dev, unsigned int reg) 934 { 935 switch (reg) { 936 case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET: 937 case TEGRA210_I2S_RX_INT_MASK ... TEGRA264_I2S_RX_CYA: 938 case TEGRA264_I2S_TX_ENABLE ... TEGRA264_I2S_TX_SOFT_RESET: 939 case TEGRA264_I2S_TX_INT_MASK ... TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE: 940 case TEGRA264_I2S_TX_FIFO_THRESHOLD ... TEGRA264_I2S_TX_CYA: 941 case TEGRA264_I2S_ENABLE ... TEGRA264_I2S_CG: 942 case TEGRA264_I2S_INT_SET ... TEGRA264_I2S_INT_MASK: 943 case TEGRA264_I2S_CTRL ... TEGRA264_I2S_CYA: 944 return true; 945 default: 946 return false; 947 }; 948 } 949 950 static bool tegra264_i2s_rd_reg(struct device *dev, unsigned int reg) 951 { 952 if (tegra264_i2s_wr_reg(dev, reg)) 953 return true; 954 955 switch (reg) { 956 case TEGRA210_I2S_RX_STATUS: 957 case TEGRA210_I2S_RX_INT_STATUS: 958 case TEGRA264_I2S_RX_CIF_FIFO_STATUS: 959 case TEGRA264_I2S_TX_STATUS: 960 case TEGRA264_I2S_TX_INT_STATUS: 961 case TEGRA264_I2S_TX_FIFO_RD_DATA: 962 case TEGRA264_I2S_TX_CIF_FIFO_STATUS: 963 case TEGRA264_I2S_STATUS: 964 case TEGRA264_I2S_INT_STATUS: 965 case TEGRA264_I2S_PIO_MODE_ENABLE: 966 case TEGRA264_I2S_PAD_MACRO_STATUS: 967 return true; 968 default: 969 return false; 970 }; 971 } 972 973 static bool tegra264_i2s_volatile_reg(struct device *dev, unsigned int reg) 974 { 975 switch (reg) { 976 case TEGRA210_I2S_RX_SOFT_RESET: 977 case TEGRA210_I2S_RX_STATUS: 978 case TEGRA210_I2S_RX_INT_STATUS: 979 case TEGRA264_I2S_RX_CIF_FIFO_STATUS: 980 case TEGRA264_I2S_TX_STATUS: 981 case TEGRA264_I2S_TX_INT_STATUS: 982 case TEGRA264_I2S_TX_FIFO_RD_DATA: 983 case TEGRA264_I2S_TX_CIF_FIFO_STATUS: 984 case TEGRA264_I2S_STATUS: 985 case TEGRA264_I2S_INT_STATUS: 986 case TEGRA264_I2S_TX_SOFT_RESET: 987 case TEGRA264_I2S_PAD_MACRO_STATUS: 988 return true; 989 default: 990 return false; 991 }; 992 } 993 994 static const struct regmap_config tegra210_regmap_conf = { 995 .reg_bits = 32, 996 .reg_stride = 4, 997 .val_bits = 32, 998 .max_register = TEGRA210_I2S_CYA, 999 .writeable_reg = tegra210_i2s_wr_reg, 1000 .readable_reg = tegra210_i2s_rd_reg, 1001 .volatile_reg = tegra210_i2s_volatile_reg, 1002 .reg_defaults = tegra210_i2s_reg_defaults, 1003 .num_reg_defaults = ARRAY_SIZE(tegra210_i2s_reg_defaults), 1004 .reg_default_cb = regmap_default_zero_cb, 1005 .cache_type = REGCACHE_FLAT, 1006 }; 1007 1008 /* 1009 * The AHUB HW modules are interconnected with CIF which are capable of 1010 * supporting Channel and Sample bit format conversion. This needs different 1011 * CIF Audio and client configuration. As one of the config comes from 1012 * params_channels() or params_format(), the extra configuration is passed from 1013 * CIF Port of DT I2S node which can help to perform this conversion. 1014 * 1015 * 4ch audio = 4ch client = 2ch 2ch 1016 * -----> ADMAIF -----------> CIF -------------> I2S ----> 1017 */ 1018 static void tegra210_parse_client_convert(struct device *dev) 1019 { 1020 struct tegra210_i2s *i2s = dev_get_drvdata(dev); 1021 struct device_node *ports, *ep; 1022 struct simple_util_data data = {}; 1023 int cif_port = 0; 1024 1025 ports = of_get_child_by_name(dev->of_node, "ports"); 1026 if (ports) { 1027 ep = of_graph_get_endpoint_by_regs(ports, cif_port, -1); 1028 if (ep) { 1029 simple_util_parse_convert(ep, NULL, &data); 1030 of_node_put(ep); 1031 } 1032 of_node_put(ports); 1033 } 1034 1035 if (data.convert_channels) 1036 i2s->client_channels = data.convert_channels; 1037 1038 if (data.convert_sample_format) 1039 i2s->client_sample_format = simple_util_get_sample_fmt(&data); 1040 } 1041 1042 static const struct regmap_config tegra264_regmap_conf = { 1043 .reg_bits = 32, 1044 .reg_stride = 4, 1045 .val_bits = 32, 1046 .max_register = TEGRA264_I2S_PAD_MACRO_STATUS, 1047 .writeable_reg = tegra264_i2s_wr_reg, 1048 .readable_reg = tegra264_i2s_rd_reg, 1049 .volatile_reg = tegra264_i2s_volatile_reg, 1050 .reg_defaults = tegra264_i2s_reg_defaults, 1051 .num_reg_defaults = ARRAY_SIZE(tegra264_i2s_reg_defaults), 1052 .reg_default_cb = regmap_default_zero_cb, 1053 .cache_type = REGCACHE_FLAT, 1054 }; 1055 1056 static int tegra210_i2s_probe(struct platform_device *pdev) 1057 { 1058 struct device *dev = &pdev->dev; 1059 struct tegra210_i2s *i2s; 1060 void __iomem *regs; 1061 int err, id; 1062 1063 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); 1064 if (!i2s) 1065 return -ENOMEM; 1066 1067 i2s->soc_data = of_device_get_match_data(&pdev->dev); 1068 i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD; 1069 i2s->tx_mask = i2s->soc_data->slot_mask; 1070 i2s->rx_mask = i2s->soc_data->slot_mask; 1071 i2s->loopback = false; 1072 i2s->client_sample_format = -EINVAL; 1073 1074 dev_set_drvdata(dev, i2s); 1075 1076 i2s->clk_i2s = devm_clk_get(dev, "i2s"); 1077 if (IS_ERR(i2s->clk_i2s)) 1078 return dev_err_probe(dev, PTR_ERR(i2s->clk_i2s), 1079 "can't retrieve I2S bit clock\n"); 1080 1081 /* 1082 * Not an error, as this clock is needed only when some other I/O 1083 * requires input clock from current I2S instance, which is 1084 * configurable from DT. 1085 */ 1086 i2s->clk_sync_input = devm_clk_get(dev, "sync_input"); 1087 if (IS_ERR(i2s->clk_sync_input)) 1088 dev_dbg(dev, "can't retrieve I2S sync input clock\n"); 1089 1090 regs = devm_platform_ioremap_resource(pdev, 0); 1091 if (IS_ERR(regs)) 1092 return PTR_ERR(regs); 1093 1094 i2s->regmap = devm_regmap_init_mmio(dev, regs, 1095 i2s->soc_data->regmap_conf); 1096 if (IS_ERR(i2s->regmap)) 1097 return dev_err_probe(dev, PTR_ERR(i2s->regmap), 1098 "regmap init failed\n"); 1099 1100 tegra210_parse_client_convert(dev); 1101 1102 regcache_cache_only(i2s->regmap, true); 1103 1104 /* Update the dais max channel as per soc */ 1105 for (id = 0; id < ARRAY_SIZE(tegra210_i2s_dais); id++) { 1106 tegra210_i2s_dais[id].playback.channels_max = i2s->soc_data->max_ch; 1107 tegra210_i2s_dais[id].capture.channels_max = i2s->soc_data->max_ch; 1108 } 1109 1110 err = devm_snd_soc_register_component(dev, i2s->soc_data->i2s_cmpnt, 1111 tegra210_i2s_dais, 1112 ARRAY_SIZE(tegra210_i2s_dais)); 1113 if (err) 1114 return dev_err_probe(dev, err, 1115 "can't register I2S component\n"); 1116 1117 pm_runtime_enable(dev); 1118 1119 return 0; 1120 } 1121 1122 static void tegra210_i2s_remove(struct platform_device *pdev) 1123 { 1124 pm_runtime_disable(&pdev->dev); 1125 } 1126 1127 static const struct dev_pm_ops tegra210_i2s_pm_ops = { 1128 RUNTIME_PM_OPS(tegra210_i2s_runtime_suspend, 1129 tegra210_i2s_runtime_resume, NULL) 1130 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1131 }; 1132 1133 static const struct tegra_i2s_soc_data soc_data_tegra210 = { 1134 .regmap_conf = &tegra210_regmap_conf, 1135 .i2s_cmpnt = &tegra210_i2s_cmpnt, 1136 .max_ch = TEGRA210_I2S_MAX_CHANNEL, 1137 .tx_offset = TEGRA210_I2S_TX_OFFSET, 1138 .i2s_ctrl_offset = TEGRA210_I2S_CTRL_OFFSET, 1139 .fsync_width_mask = I2S_CTRL_FSYNC_WIDTH_MASK, 1140 .fsync_width_shift = I2S_FSYNC_WIDTH_SHIFT, 1141 .slot_mask = DEFAULT_I2S_SLOT_MASK, 1142 }; 1143 1144 static const struct tegra_i2s_soc_data soc_data_tegra264 = { 1145 .regmap_conf = &tegra264_regmap_conf, 1146 .i2s_cmpnt = &tegra264_i2s_cmpnt, 1147 .max_ch = TEGRA264_I2S_MAX_CHANNEL, 1148 .tx_offset = TEGRA264_I2S_TX_OFFSET, 1149 .i2s_ctrl_offset = TEGRA264_I2S_CTRL_OFFSET, 1150 .fsync_width_mask = TEGRA264_I2S_CTRL_FSYNC_WIDTH_MASK, 1151 .fsync_width_shift = TEGRA264_I2S_FSYNC_WIDTH_SHIFT, 1152 .slot_mask = TEGRA264_DEFAULT_I2S_SLOT_MASK, 1153 }; 1154 1155 static const struct of_device_id tegra210_i2s_of_match[] = { 1156 { .compatible = "nvidia,tegra210-i2s", .data = &soc_data_tegra210 }, 1157 { .compatible = "nvidia,tegra264-i2s", .data = &soc_data_tegra264 }, 1158 {}, 1159 }; 1160 MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match); 1161 1162 static struct platform_driver tegra210_i2s_driver = { 1163 .driver = { 1164 .name = "tegra210-i2s", 1165 .of_match_table = tegra210_i2s_of_match, 1166 .pm = pm_ptr(&tegra210_i2s_pm_ops), 1167 }, 1168 .probe = tegra210_i2s_probe, 1169 .remove = tegra210_i2s_remove, 1170 }; 1171 module_platform_driver(tegra210_i2s_driver) 1172 1173 MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>"); 1174 MODULE_DESCRIPTION("Tegra210 ASoC I2S driver"); 1175 MODULE_LICENSE("GPL v2"); 1176