1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Thunderbolt driver - NHI driver
4 *
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
7 *
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
10 */
11
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/iommu.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/property.h>
22 #include <linux/string_choices.h>
23 #include <linux/string_helpers.h>
24
25 #include "nhi.h"
26 #include "nhi_regs.h"
27 #include "tb.h"
28
29 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
30
31 #define RING_FIRST_USABLE_HOPID 1
32 /*
33 * Used with QUIRK_E2E to specify an unused HopID the Rx credits are
34 * transferred.
35 */
36 #define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID
37 /*
38 * Minimal number of vectors when we use MSI-X. Two for control channel
39 * Rx/Tx and the rest four are for cross domain DMA paths.
40 */
41 #define MSIX_MIN_VECS 6
42 #define MSIX_MAX_VECS 16
43
44 #define NHI_MAILBOX_TIMEOUT 500 /* ms */
45
46 /* Host interface quirks */
47 #define QUIRK_AUTO_CLEAR_INT BIT(0)
48 #define QUIRK_E2E BIT(1)
49
50 static bool host_reset = true;
51 module_param(host_reset, bool, 0444);
52 MODULE_PARM_DESC(host_reset, "reset USB4 host router (default: true)");
53
ring_interrupt_index(const struct tb_ring * ring)54 static int ring_interrupt_index(const struct tb_ring *ring)
55 {
56 int bit = ring->hop;
57 if (!ring->is_tx)
58 bit += ring->nhi->hop_count;
59 return bit;
60 }
61
nhi_mask_interrupt(struct tb_nhi * nhi,int mask,int ring)62 static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring)
63 {
64 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) {
65 u32 val;
66
67 val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
68 iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
69 } else {
70 iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring);
71 }
72 }
73
nhi_clear_interrupt(struct tb_nhi * nhi,int ring)74 static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring)
75 {
76 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT)
77 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + ring);
78 else
79 iowrite32(~0, nhi->iobase + REG_RING_INT_CLEAR + ring);
80 }
81
82 /*
83 * ring_interrupt_active() - activate/deactivate interrupts for a single ring
84 *
85 * ring->nhi->lock must be held.
86 */
ring_interrupt_active(struct tb_ring * ring,bool active)87 static void ring_interrupt_active(struct tb_ring *ring, bool active)
88 {
89 int index = ring_interrupt_index(ring) / 32 * 4;
90 int reg = REG_RING_INTERRUPT_BASE + index;
91 int interrupt_bit = ring_interrupt_index(ring) & 31;
92 int mask = 1 << interrupt_bit;
93 u32 old, new;
94
95 if (ring->irq > 0) {
96 u32 step, shift, ivr, misc;
97 void __iomem *ivr_base;
98 int auto_clear_bit;
99 int index;
100
101 if (ring->is_tx)
102 index = ring->hop;
103 else
104 index = ring->hop + ring->nhi->hop_count;
105
106 /*
107 * Intel routers support a bit that isn't part of
108 * the USB4 spec to ask the hardware to clear
109 * interrupt status bits automatically since
110 * we already know which interrupt was triggered.
111 *
112 * Other routers explicitly disable auto-clear
113 * to prevent conditions that may occur where two
114 * MSIX interrupts are simultaneously active and
115 * reading the register clears both of them.
116 */
117 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
118 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
119 auto_clear_bit = REG_DMA_MISC_INT_AUTO_CLEAR;
120 else
121 auto_clear_bit = REG_DMA_MISC_DISABLE_AUTO_CLEAR;
122 if (!(misc & auto_clear_bit))
123 iowrite32(misc | auto_clear_bit,
124 ring->nhi->iobase + REG_DMA_MISC);
125
126 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
127 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
128 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
129 ivr = ioread32(ivr_base + step);
130 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
131 if (active)
132 ivr |= ring->vector << shift;
133 iowrite32(ivr, ivr_base + step);
134 }
135
136 old = ioread32(ring->nhi->iobase + reg);
137 if (active)
138 new = old | mask;
139 else
140 new = old & ~mask;
141
142 dev_dbg(&ring->nhi->pdev->dev,
143 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
144 active ? "enabling" : "disabling", reg, interrupt_bit, old, new);
145
146 if (new == old)
147 dev_WARN(&ring->nhi->pdev->dev,
148 "interrupt for %s %d is already %s\n",
149 RING_TYPE(ring), ring->hop,
150 str_enabled_disabled(active));
151
152 if (active)
153 iowrite32(new, ring->nhi->iobase + reg);
154 else
155 nhi_mask_interrupt(ring->nhi, mask, index);
156 }
157
158 /*
159 * nhi_disable_interrupts() - disable interrupts for all rings
160 *
161 * Use only during init and shutdown.
162 */
nhi_disable_interrupts(struct tb_nhi * nhi)163 static void nhi_disable_interrupts(struct tb_nhi *nhi)
164 {
165 int i = 0;
166 /* disable interrupts */
167 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
168 nhi_mask_interrupt(nhi, ~0, 4 * i);
169
170 /* clear interrupt status bits */
171 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
172 nhi_clear_interrupt(nhi, 4 * i);
173 }
174
175 /* ring helper methods */
176
ring_desc_base(struct tb_ring * ring)177 static void __iomem *ring_desc_base(struct tb_ring *ring)
178 {
179 void __iomem *io = ring->nhi->iobase;
180 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
181 io += ring->hop * 16;
182 return io;
183 }
184
ring_options_base(struct tb_ring * ring)185 static void __iomem *ring_options_base(struct tb_ring *ring)
186 {
187 void __iomem *io = ring->nhi->iobase;
188 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
189 io += ring->hop * 32;
190 return io;
191 }
192
ring_iowrite_cons(struct tb_ring * ring,u16 cons)193 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
194 {
195 /*
196 * The other 16-bits in the register is read-only and writes to it
197 * are ignored by the hardware so we can save one ioread32() by
198 * filling the read-only bits with zeroes.
199 */
200 iowrite32(cons, ring_desc_base(ring) + 8);
201 }
202
ring_iowrite_prod(struct tb_ring * ring,u16 prod)203 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
204 {
205 /* See ring_iowrite_cons() above for explanation */
206 iowrite32(prod << 16, ring_desc_base(ring) + 8);
207 }
208
ring_iowrite32desc(struct tb_ring * ring,u32 value,u32 offset)209 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
210 {
211 iowrite32(value, ring_desc_base(ring) + offset);
212 }
213
ring_iowrite64desc(struct tb_ring * ring,u64 value,u32 offset)214 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
215 {
216 iowrite32(value, ring_desc_base(ring) + offset);
217 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
218 }
219
ring_iowrite32options(struct tb_ring * ring,u32 value,u32 offset)220 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
221 {
222 iowrite32(value, ring_options_base(ring) + offset);
223 }
224
ring_full(struct tb_ring * ring)225 static bool ring_full(struct tb_ring *ring)
226 {
227 return ((ring->head + 1) % ring->size) == ring->tail;
228 }
229
ring_empty(struct tb_ring * ring)230 static bool ring_empty(struct tb_ring *ring)
231 {
232 return ring->head == ring->tail;
233 }
234
235 /*
236 * ring_write_descriptors() - post frames from ring->queue to the controller
237 *
238 * ring->lock is held.
239 */
ring_write_descriptors(struct tb_ring * ring)240 static void ring_write_descriptors(struct tb_ring *ring)
241 {
242 struct ring_frame *frame, *n;
243 struct ring_desc *descriptor;
244 list_for_each_entry_safe(frame, n, &ring->queue, list) {
245 if (ring_full(ring))
246 break;
247 list_move_tail(&frame->list, &ring->in_flight);
248 descriptor = &ring->descriptors[ring->head];
249 descriptor->phys = frame->buffer_phy;
250 descriptor->time = 0;
251 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
252 if (ring->is_tx) {
253 descriptor->length = frame->size;
254 descriptor->eof = frame->eof;
255 descriptor->sof = frame->sof;
256 }
257 ring->head = (ring->head + 1) % ring->size;
258 if (ring->is_tx)
259 ring_iowrite_prod(ring, ring->head);
260 else
261 ring_iowrite_cons(ring, ring->head);
262 }
263 }
264
265 /*
266 * ring_work() - progress completed frames
267 *
268 * If the ring is shutting down then all frames are marked as canceled and
269 * their callbacks are invoked.
270 *
271 * Otherwise we collect all completed frame from the ring buffer, write new
272 * frame to the ring buffer and invoke the callbacks for the completed frames.
273 */
ring_work(struct work_struct * work)274 static void ring_work(struct work_struct *work)
275 {
276 struct tb_ring *ring = container_of(work, typeof(*ring), work);
277 struct ring_frame *frame;
278 bool canceled = false;
279 unsigned long flags;
280 LIST_HEAD(done);
281
282 spin_lock_irqsave(&ring->lock, flags);
283
284 if (!ring->running) {
285 /* Move all frames to done and mark them as canceled. */
286 list_splice_tail_init(&ring->in_flight, &done);
287 list_splice_tail_init(&ring->queue, &done);
288 canceled = true;
289 goto invoke_callback;
290 }
291
292 while (!ring_empty(ring)) {
293 if (!(ring->descriptors[ring->tail].flags
294 & RING_DESC_COMPLETED))
295 break;
296 frame = list_first_entry(&ring->in_flight, typeof(*frame),
297 list);
298 list_move_tail(&frame->list, &done);
299 if (!ring->is_tx) {
300 frame->size = ring->descriptors[ring->tail].length;
301 frame->eof = ring->descriptors[ring->tail].eof;
302 frame->sof = ring->descriptors[ring->tail].sof;
303 frame->flags = ring->descriptors[ring->tail].flags;
304 }
305 ring->tail = (ring->tail + 1) % ring->size;
306 }
307 ring_write_descriptors(ring);
308
309 invoke_callback:
310 /* allow callbacks to schedule new work */
311 spin_unlock_irqrestore(&ring->lock, flags);
312 while (!list_empty(&done)) {
313 frame = list_first_entry(&done, typeof(*frame), list);
314 /*
315 * The callback may reenqueue or delete frame.
316 * Do not hold on to it.
317 */
318 list_del_init(&frame->list);
319 if (frame->callback)
320 frame->callback(ring, frame, canceled);
321 }
322 }
323
__tb_ring_enqueue(struct tb_ring * ring,struct ring_frame * frame)324 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
325 {
326 unsigned long flags;
327 int ret = 0;
328
329 spin_lock_irqsave(&ring->lock, flags);
330 if (ring->running) {
331 list_add_tail(&frame->list, &ring->queue);
332 ring_write_descriptors(ring);
333 } else {
334 ret = -ESHUTDOWN;
335 }
336 spin_unlock_irqrestore(&ring->lock, flags);
337 return ret;
338 }
339 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
340
341 /**
342 * tb_ring_poll() - Poll one completed frame from the ring
343 * @ring: Ring to poll
344 *
345 * This function can be called when @start_poll callback of the @ring
346 * has been called. It will read one completed frame from the ring and
347 * return it to the caller.
348 *
349 * Return: Pointer to &struct ring_frame, %NULL if there is no more
350 * completed frames.
351 */
tb_ring_poll(struct tb_ring * ring)352 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
353 {
354 struct ring_frame *frame = NULL;
355 unsigned long flags;
356
357 spin_lock_irqsave(&ring->lock, flags);
358 if (!ring->running)
359 goto unlock;
360 if (ring_empty(ring))
361 goto unlock;
362
363 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
364 frame = list_first_entry(&ring->in_flight, typeof(*frame),
365 list);
366 list_del_init(&frame->list);
367
368 if (!ring->is_tx) {
369 frame->size = ring->descriptors[ring->tail].length;
370 frame->eof = ring->descriptors[ring->tail].eof;
371 frame->sof = ring->descriptors[ring->tail].sof;
372 frame->flags = ring->descriptors[ring->tail].flags;
373 }
374
375 ring->tail = (ring->tail + 1) % ring->size;
376 }
377
378 unlock:
379 spin_unlock_irqrestore(&ring->lock, flags);
380 return frame;
381 }
382 EXPORT_SYMBOL_GPL(tb_ring_poll);
383
__ring_interrupt_mask(struct tb_ring * ring,bool mask)384 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
385 {
386 int idx = ring_interrupt_index(ring);
387 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
388 int bit = idx % 32;
389 u32 val;
390
391 val = ioread32(ring->nhi->iobase + reg);
392 if (mask)
393 val &= ~BIT(bit);
394 else
395 val |= BIT(bit);
396 iowrite32(val, ring->nhi->iobase + reg);
397 }
398
399 /* Both @nhi->lock and @ring->lock should be held */
__ring_interrupt(struct tb_ring * ring)400 static void __ring_interrupt(struct tb_ring *ring)
401 {
402 if (!ring->running)
403 return;
404
405 if (ring->start_poll) {
406 __ring_interrupt_mask(ring, true);
407 ring->start_poll(ring->poll_data);
408 } else {
409 schedule_work(&ring->work);
410 }
411 }
412
413 /**
414 * tb_ring_poll_complete() - Re-start interrupt for the ring
415 * @ring: Ring to re-start the interrupt
416 *
417 * This will re-start (unmask) the ring interrupt once the user is done
418 * with polling.
419 */
tb_ring_poll_complete(struct tb_ring * ring)420 void tb_ring_poll_complete(struct tb_ring *ring)
421 {
422 unsigned long flags;
423
424 spin_lock_irqsave(&ring->nhi->lock, flags);
425 spin_lock(&ring->lock);
426 if (ring->start_poll)
427 __ring_interrupt_mask(ring, false);
428 spin_unlock(&ring->lock);
429 spin_unlock_irqrestore(&ring->nhi->lock, flags);
430 }
431 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
432
ring_clear_msix(const struct tb_ring * ring)433 static void ring_clear_msix(const struct tb_ring *ring)
434 {
435 int bit;
436
437 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
438 return;
439
440 bit = ring_interrupt_index(ring) & 31;
441 if (ring->is_tx)
442 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR);
443 else
444 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR +
445 4 * (ring->nhi->hop_count / 32));
446 }
447
ring_msix(int irq,void * data)448 static irqreturn_t ring_msix(int irq, void *data)
449 {
450 struct tb_ring *ring = data;
451
452 spin_lock(&ring->nhi->lock);
453 ring_clear_msix(ring);
454 spin_lock(&ring->lock);
455 __ring_interrupt(ring);
456 spin_unlock(&ring->lock);
457 spin_unlock(&ring->nhi->lock);
458
459 return IRQ_HANDLED;
460 }
461
ring_request_msix(struct tb_ring * ring,bool no_suspend)462 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
463 {
464 struct tb_nhi *nhi = ring->nhi;
465 unsigned long irqflags;
466 int ret;
467
468 if (!nhi->pdev->msix_enabled)
469 return 0;
470
471 ret = ida_alloc_max(&nhi->msix_ida, MSIX_MAX_VECS - 1, GFP_KERNEL);
472 if (ret < 0)
473 return ret;
474
475 ring->vector = ret;
476
477 ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
478 if (ret < 0)
479 goto err_ida_remove;
480
481 ring->irq = ret;
482
483 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
484 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
485 if (ret)
486 goto err_ida_remove;
487
488 return 0;
489
490 err_ida_remove:
491 ida_free(&nhi->msix_ida, ring->vector);
492
493 return ret;
494 }
495
ring_release_msix(struct tb_ring * ring)496 static void ring_release_msix(struct tb_ring *ring)
497 {
498 if (ring->irq <= 0)
499 return;
500
501 free_irq(ring->irq, ring);
502 ida_free(&ring->nhi->msix_ida, ring->vector);
503 ring->vector = 0;
504 ring->irq = 0;
505 }
506
nhi_alloc_hop(struct tb_nhi * nhi,struct tb_ring * ring)507 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
508 {
509 unsigned int start_hop = RING_FIRST_USABLE_HOPID;
510 int ret = 0;
511
512 if (nhi->quirks & QUIRK_E2E) {
513 start_hop = RING_FIRST_USABLE_HOPID + 1;
514 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) {
515 dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n",
516 ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID);
517 ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID;
518 }
519 }
520
521 spin_lock_irq(&nhi->lock);
522
523 if (ring->hop < 0) {
524 unsigned int i;
525
526 /*
527 * Automatically allocate HopID from the non-reserved
528 * range 1 .. hop_count - 1.
529 */
530 for (i = start_hop; i < nhi->hop_count; i++) {
531 if (ring->is_tx) {
532 if (!nhi->tx_rings[i]) {
533 ring->hop = i;
534 break;
535 }
536 } else {
537 if (!nhi->rx_rings[i]) {
538 ring->hop = i;
539 break;
540 }
541 }
542 }
543 }
544
545 if (ring->hop > 0 && ring->hop < start_hop) {
546 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
547 ret = -EINVAL;
548 goto err_unlock;
549 }
550 if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
551 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
552 ret = -EINVAL;
553 goto err_unlock;
554 }
555 if (ring->is_tx && nhi->tx_rings[ring->hop]) {
556 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
557 ring->hop);
558 ret = -EBUSY;
559 goto err_unlock;
560 }
561 if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
562 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
563 ring->hop);
564 ret = -EBUSY;
565 goto err_unlock;
566 }
567
568 if (ring->is_tx)
569 nhi->tx_rings[ring->hop] = ring;
570 else
571 nhi->rx_rings[ring->hop] = ring;
572
573 err_unlock:
574 spin_unlock_irq(&nhi->lock);
575
576 return ret;
577 }
578
tb_ring_alloc(struct tb_nhi * nhi,u32 hop,int size,bool transmit,unsigned int flags,int e2e_tx_hop,u16 sof_mask,u16 eof_mask,void (* start_poll)(void *),void * poll_data)579 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
580 bool transmit, unsigned int flags,
581 int e2e_tx_hop, u16 sof_mask, u16 eof_mask,
582 void (*start_poll)(void *),
583 void *poll_data)
584 {
585 struct tb_ring *ring = NULL;
586
587 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
588 transmit ? "TX" : "RX", hop, size);
589
590 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
591 if (!ring)
592 return NULL;
593
594 spin_lock_init(&ring->lock);
595 INIT_LIST_HEAD(&ring->queue);
596 INIT_LIST_HEAD(&ring->in_flight);
597 INIT_WORK(&ring->work, ring_work);
598
599 ring->nhi = nhi;
600 ring->hop = hop;
601 ring->is_tx = transmit;
602 ring->size = size;
603 ring->flags = flags;
604 ring->e2e_tx_hop = e2e_tx_hop;
605 ring->sof_mask = sof_mask;
606 ring->eof_mask = eof_mask;
607 ring->head = 0;
608 ring->tail = 0;
609 ring->running = false;
610 ring->start_poll = start_poll;
611 ring->poll_data = poll_data;
612
613 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
614 size * sizeof(*ring->descriptors),
615 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
616 if (!ring->descriptors)
617 goto err_free_ring;
618
619 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
620 goto err_free_descs;
621
622 if (nhi_alloc_hop(nhi, ring))
623 goto err_release_msix;
624
625 return ring;
626
627 err_release_msix:
628 ring_release_msix(ring);
629 err_free_descs:
630 dma_free_coherent(&ring->nhi->pdev->dev,
631 ring->size * sizeof(*ring->descriptors),
632 ring->descriptors, ring->descriptors_dma);
633 err_free_ring:
634 kfree(ring);
635
636 return NULL;
637 }
638
639 /**
640 * tb_ring_alloc_tx() - Allocate DMA ring for transmit
641 * @nhi: Pointer to the NHI the ring is to be allocated
642 * @hop: HopID (ring) to allocate
643 * @size: Number of entries in the ring
644 * @flags: Flags for the ring
645 *
646 * Return: Pointer to &struct tb_ring, %NULL otherwise.
647 */
tb_ring_alloc_tx(struct tb_nhi * nhi,int hop,int size,unsigned int flags)648 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
649 unsigned int flags)
650 {
651 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL);
652 }
653 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
654
655 /**
656 * tb_ring_alloc_rx() - Allocate DMA ring for receive
657 * @nhi: Pointer to the NHI the ring is to be allocated
658 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
659 * @size: Number of entries in the ring
660 * @flags: Flags for the ring
661 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags
662 * @sof_mask: Mask of PDF values that start a frame
663 * @eof_mask: Mask of PDF values that end a frame
664 * @start_poll: If not %NULL the ring will call this function when an
665 * interrupt is triggered and masked, instead of callback
666 * in each Rx frame.
667 * @poll_data: Optional data passed to @start_poll
668 *
669 * Return: Pointer to &struct tb_ring, %NULL otherwise.
670 */
tb_ring_alloc_rx(struct tb_nhi * nhi,int hop,int size,unsigned int flags,int e2e_tx_hop,u16 sof_mask,u16 eof_mask,void (* start_poll)(void *),void * poll_data)671 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
672 unsigned int flags, int e2e_tx_hop,
673 u16 sof_mask, u16 eof_mask,
674 void (*start_poll)(void *), void *poll_data)
675 {
676 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask,
677 start_poll, poll_data);
678 }
679 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
680
681 /**
682 * tb_ring_start() - enable a ring
683 * @ring: Ring to start
684 *
685 * Must not be invoked in parallel with tb_ring_stop().
686 */
tb_ring_start(struct tb_ring * ring)687 void tb_ring_start(struct tb_ring *ring)
688 {
689 u16 frame_size;
690 u32 flags;
691
692 spin_lock_irq(&ring->nhi->lock);
693 spin_lock(&ring->lock);
694 if (ring->nhi->going_away)
695 goto err;
696 if (ring->running) {
697 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
698 goto err;
699 }
700 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
701 RING_TYPE(ring), ring->hop);
702
703 if (ring->flags & RING_FLAG_FRAME) {
704 /* Means 4096 */
705 frame_size = 0;
706 flags = RING_FLAG_ENABLE;
707 } else {
708 frame_size = TB_FRAME_SIZE;
709 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
710 }
711
712 ring_iowrite64desc(ring, ring->descriptors_dma, 0);
713 if (ring->is_tx) {
714 ring_iowrite32desc(ring, ring->size, 12);
715 ring_iowrite32options(ring, 0, 4); /* time releated ? */
716 ring_iowrite32options(ring, flags, 0);
717 } else {
718 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
719
720 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
721 ring_iowrite32options(ring, sof_eof_mask, 4);
722 ring_iowrite32options(ring, flags, 0);
723 }
724
725 /*
726 * Now that the ring valid bit is set we can configure E2E if
727 * enabled for the ring.
728 */
729 if (ring->flags & RING_FLAG_E2E) {
730 if (!ring->is_tx) {
731 u32 hop;
732
733 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT;
734 hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
735 flags |= hop;
736
737 dev_dbg(&ring->nhi->pdev->dev,
738 "enabling E2E for %s %d with TX HopID %d\n",
739 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop);
740 } else {
741 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n",
742 RING_TYPE(ring), ring->hop);
743 }
744
745 flags |= RING_FLAG_E2E_FLOW_CONTROL;
746 ring_iowrite32options(ring, flags, 0);
747 }
748
749 ring_interrupt_active(ring, true);
750 ring->running = true;
751 err:
752 spin_unlock(&ring->lock);
753 spin_unlock_irq(&ring->nhi->lock);
754 }
755 EXPORT_SYMBOL_GPL(tb_ring_start);
756
757 /**
758 * tb_ring_stop() - shutdown a ring
759 * @ring: Ring to stop
760 *
761 * Must not be invoked from a callback.
762 *
763 * This method will disable the ring. Further calls to
764 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
765 * called.
766 *
767 * All enqueued frames will be canceled and their callbacks will be executed
768 * with frame->canceled set to true (on the callback thread). This method
769 * returns only after all callback invocations have finished.
770 */
tb_ring_stop(struct tb_ring * ring)771 void tb_ring_stop(struct tb_ring *ring)
772 {
773 spin_lock_irq(&ring->nhi->lock);
774 spin_lock(&ring->lock);
775 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
776 RING_TYPE(ring), ring->hop);
777 if (ring->nhi->going_away)
778 goto err;
779 if (!ring->running) {
780 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
781 RING_TYPE(ring), ring->hop);
782 goto err;
783 }
784 ring_interrupt_active(ring, false);
785
786 ring_iowrite32options(ring, 0, 0);
787 ring_iowrite64desc(ring, 0, 0);
788 ring_iowrite32desc(ring, 0, 8);
789 ring_iowrite32desc(ring, 0, 12);
790 ring->head = 0;
791 ring->tail = 0;
792 ring->running = false;
793
794 err:
795 spin_unlock(&ring->lock);
796 spin_unlock_irq(&ring->nhi->lock);
797
798 /*
799 * schedule ring->work to invoke callbacks on all remaining frames.
800 */
801 schedule_work(&ring->work);
802 flush_work(&ring->work);
803 }
804 EXPORT_SYMBOL_GPL(tb_ring_stop);
805
806 /*
807 * tb_ring_free() - free ring
808 *
809 * When this method returns all invocations of ring->callback will have
810 * finished.
811 *
812 * Ring must be stopped.
813 *
814 * Must NOT be called from ring_frame->callback!
815 */
tb_ring_free(struct tb_ring * ring)816 void tb_ring_free(struct tb_ring *ring)
817 {
818 spin_lock_irq(&ring->nhi->lock);
819 /*
820 * Dissociate the ring from the NHI. This also ensures that
821 * nhi_interrupt_work cannot reschedule ring->work.
822 */
823 if (ring->is_tx)
824 ring->nhi->tx_rings[ring->hop] = NULL;
825 else
826 ring->nhi->rx_rings[ring->hop] = NULL;
827
828 if (ring->running) {
829 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
830 RING_TYPE(ring), ring->hop);
831 }
832 spin_unlock_irq(&ring->nhi->lock);
833
834 ring_release_msix(ring);
835
836 dma_free_coherent(&ring->nhi->pdev->dev,
837 ring->size * sizeof(*ring->descriptors),
838 ring->descriptors, ring->descriptors_dma);
839
840 ring->descriptors = NULL;
841 ring->descriptors_dma = 0;
842
843
844 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
845 ring->hop);
846
847 /*
848 * ring->work can no longer be scheduled (it is scheduled only
849 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
850 * to finish before freeing the ring.
851 */
852 flush_work(&ring->work);
853 kfree(ring);
854 }
855 EXPORT_SYMBOL_GPL(tb_ring_free);
856
857 /**
858 * nhi_mailbox_cmd() - Send a command through NHI mailbox
859 * @nhi: Pointer to the NHI structure
860 * @cmd: Command to send
861 * @data: Data to be send with the command
862 *
863 * Sends mailbox command to the firmware running on NHI.
864 *
865 * Return: %0 on success, negative errno otherwise.
866 */
nhi_mailbox_cmd(struct tb_nhi * nhi,enum nhi_mailbox_cmd cmd,u32 data)867 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
868 {
869 ktime_t timeout;
870 u32 val;
871
872 iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
873
874 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
875 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
876 val |= REG_INMAIL_OP_REQUEST | cmd;
877 iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
878
879 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
880 do {
881 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
882 if (!(val & REG_INMAIL_OP_REQUEST))
883 break;
884 usleep_range(10, 20);
885 } while (ktime_before(ktime_get(), timeout));
886
887 if (val & REG_INMAIL_OP_REQUEST)
888 return -ETIMEDOUT;
889 if (val & REG_INMAIL_ERROR)
890 return -EIO;
891
892 return 0;
893 }
894
895 /**
896 * nhi_mailbox_mode() - Return current firmware operation mode
897 * @nhi: Pointer to the NHI structure
898 *
899 * The function reads current firmware operation mode using NHI mailbox
900 * registers and returns it to the caller.
901 *
902 * Return: &enum nhi_fw_mode.
903 */
nhi_mailbox_mode(struct tb_nhi * nhi)904 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
905 {
906 u32 val;
907
908 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
909 val &= REG_OUTMAIL_CMD_OPMODE_MASK;
910 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
911
912 return (enum nhi_fw_mode)val;
913 }
914
nhi_interrupt_work(struct work_struct * work)915 static void nhi_interrupt_work(struct work_struct *work)
916 {
917 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
918 int value = 0; /* Suppress uninitialized usage warning. */
919 int bit;
920 int hop = -1;
921 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
922 struct tb_ring *ring;
923
924 spin_lock_irq(&nhi->lock);
925
926 /*
927 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
928 * (TX, RX, RX overflow). We iterate over the bits and read a new
929 * dwords as required. The registers are cleared on read.
930 */
931 for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
932 if (bit % 32 == 0)
933 value = ioread32(nhi->iobase
934 + REG_RING_NOTIFY_BASE
935 + 4 * (bit / 32));
936 if (++hop == nhi->hop_count) {
937 hop = 0;
938 type++;
939 }
940 if ((value & (1 << (bit % 32))) == 0)
941 continue;
942 if (type == 2) {
943 dev_warn(&nhi->pdev->dev,
944 "RX overflow for ring %d\n",
945 hop);
946 continue;
947 }
948 if (type == 0)
949 ring = nhi->tx_rings[hop];
950 else
951 ring = nhi->rx_rings[hop];
952 if (ring == NULL) {
953 dev_warn(&nhi->pdev->dev,
954 "got interrupt for inactive %s ring %d\n",
955 type ? "RX" : "TX",
956 hop);
957 continue;
958 }
959
960 spin_lock(&ring->lock);
961 __ring_interrupt(ring);
962 spin_unlock(&ring->lock);
963 }
964 spin_unlock_irq(&nhi->lock);
965 }
966
nhi_msi(int irq,void * data)967 static irqreturn_t nhi_msi(int irq, void *data)
968 {
969 struct tb_nhi *nhi = data;
970 schedule_work(&nhi->interrupt_work);
971 return IRQ_HANDLED;
972 }
973
__nhi_suspend_noirq(struct device * dev,bool wakeup)974 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
975 {
976 struct pci_dev *pdev = to_pci_dev(dev);
977 struct tb *tb = pci_get_drvdata(pdev);
978 struct tb_nhi *nhi = tb->nhi;
979 int ret;
980
981 ret = tb_domain_suspend_noirq(tb);
982 if (ret)
983 return ret;
984
985 if (nhi->ops && nhi->ops->suspend_noirq) {
986 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
987 if (ret)
988 return ret;
989 }
990
991 return 0;
992 }
993
nhi_suspend_noirq(struct device * dev)994 static int nhi_suspend_noirq(struct device *dev)
995 {
996 return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
997 }
998
nhi_freeze_noirq(struct device * dev)999 static int nhi_freeze_noirq(struct device *dev)
1000 {
1001 struct pci_dev *pdev = to_pci_dev(dev);
1002 struct tb *tb = pci_get_drvdata(pdev);
1003
1004 return tb_domain_freeze_noirq(tb);
1005 }
1006
nhi_thaw_noirq(struct device * dev)1007 static int nhi_thaw_noirq(struct device *dev)
1008 {
1009 struct pci_dev *pdev = to_pci_dev(dev);
1010 struct tb *tb = pci_get_drvdata(pdev);
1011
1012 return tb_domain_thaw_noirq(tb);
1013 }
1014
nhi_wake_supported(struct pci_dev * pdev)1015 static bool nhi_wake_supported(struct pci_dev *pdev)
1016 {
1017 u8 val;
1018
1019 /*
1020 * If power rails are sustainable for wakeup from S4 this
1021 * property is set by the BIOS.
1022 */
1023 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
1024 return !!val;
1025
1026 return true;
1027 }
1028
nhi_poweroff_noirq(struct device * dev)1029 static int nhi_poweroff_noirq(struct device *dev)
1030 {
1031 struct pci_dev *pdev = to_pci_dev(dev);
1032 bool wakeup;
1033
1034 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
1035 return __nhi_suspend_noirq(dev, wakeup);
1036 }
1037
nhi_enable_int_throttling(struct tb_nhi * nhi)1038 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
1039 {
1040 /* Throttling is specified in 256ns increments */
1041 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
1042 unsigned int i;
1043
1044 /*
1045 * Configure interrupt throttling for all vectors even if we
1046 * only use few.
1047 */
1048 for (i = 0; i < MSIX_MAX_VECS; i++) {
1049 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
1050 iowrite32(throttle, nhi->iobase + reg);
1051 }
1052 }
1053
nhi_resume_noirq(struct device * dev)1054 static int nhi_resume_noirq(struct device *dev)
1055 {
1056 struct pci_dev *pdev = to_pci_dev(dev);
1057 struct tb *tb = pci_get_drvdata(pdev);
1058 struct tb_nhi *nhi = tb->nhi;
1059 int ret;
1060
1061 /*
1062 * Check that the device is still there. It may be that the user
1063 * unplugged last device which causes the host controller to go
1064 * away on PCs.
1065 */
1066 if (!pci_device_is_present(pdev)) {
1067 nhi->going_away = true;
1068 } else {
1069 if (nhi->ops && nhi->ops->resume_noirq) {
1070 ret = nhi->ops->resume_noirq(nhi);
1071 if (ret)
1072 return ret;
1073 }
1074 nhi_enable_int_throttling(tb->nhi);
1075 }
1076
1077 return tb_domain_resume_noirq(tb);
1078 }
1079
nhi_suspend(struct device * dev)1080 static int nhi_suspend(struct device *dev)
1081 {
1082 struct pci_dev *pdev = to_pci_dev(dev);
1083 struct tb *tb = pci_get_drvdata(pdev);
1084
1085 return tb_domain_suspend(tb);
1086 }
1087
nhi_complete(struct device * dev)1088 static void nhi_complete(struct device *dev)
1089 {
1090 struct pci_dev *pdev = to_pci_dev(dev);
1091 struct tb *tb = pci_get_drvdata(pdev);
1092
1093 /*
1094 * If we were runtime suspended when system suspend started,
1095 * schedule runtime resume now. It should bring the domain back
1096 * to functional state.
1097 */
1098 if (pm_runtime_suspended(&pdev->dev))
1099 pm_runtime_resume(&pdev->dev);
1100 else
1101 tb_domain_complete(tb);
1102 }
1103
nhi_runtime_suspend(struct device * dev)1104 static int nhi_runtime_suspend(struct device *dev)
1105 {
1106 struct pci_dev *pdev = to_pci_dev(dev);
1107 struct tb *tb = pci_get_drvdata(pdev);
1108 struct tb_nhi *nhi = tb->nhi;
1109 int ret;
1110
1111 ret = tb_domain_runtime_suspend(tb);
1112 if (ret)
1113 return ret;
1114
1115 if (nhi->ops && nhi->ops->runtime_suspend) {
1116 ret = nhi->ops->runtime_suspend(tb->nhi);
1117 if (ret)
1118 return ret;
1119 }
1120 return 0;
1121 }
1122
nhi_runtime_resume(struct device * dev)1123 static int nhi_runtime_resume(struct device *dev)
1124 {
1125 struct pci_dev *pdev = to_pci_dev(dev);
1126 struct tb *tb = pci_get_drvdata(pdev);
1127 struct tb_nhi *nhi = tb->nhi;
1128 int ret;
1129
1130 if (nhi->ops && nhi->ops->runtime_resume) {
1131 ret = nhi->ops->runtime_resume(nhi);
1132 if (ret)
1133 return ret;
1134 }
1135
1136 nhi_enable_int_throttling(nhi);
1137 return tb_domain_runtime_resume(tb);
1138 }
1139
nhi_shutdown(struct tb_nhi * nhi)1140 static void nhi_shutdown(struct tb_nhi *nhi)
1141 {
1142 int i;
1143
1144 dev_dbg(&nhi->pdev->dev, "shutdown\n");
1145
1146 for (i = 0; i < nhi->hop_count; i++) {
1147 if (nhi->tx_rings[i])
1148 dev_WARN(&nhi->pdev->dev,
1149 "TX ring %d is still active\n", i);
1150 if (nhi->rx_rings[i])
1151 dev_WARN(&nhi->pdev->dev,
1152 "RX ring %d is still active\n", i);
1153 }
1154 nhi_disable_interrupts(nhi);
1155 /*
1156 * We have to release the irq before calling flush_work. Otherwise an
1157 * already executing IRQ handler could call schedule_work again.
1158 */
1159 if (!nhi->pdev->msix_enabled) {
1160 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1161 flush_work(&nhi->interrupt_work);
1162 }
1163 ida_destroy(&nhi->msix_ida);
1164
1165 if (nhi->ops && nhi->ops->shutdown)
1166 nhi->ops->shutdown(nhi);
1167 }
1168
nhi_check_quirks(struct tb_nhi * nhi)1169 static void nhi_check_quirks(struct tb_nhi *nhi)
1170 {
1171 if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) {
1172 /*
1173 * Intel hardware supports auto clear of the interrupt
1174 * status register right after interrupt is being
1175 * issued.
1176 */
1177 nhi->quirks |= QUIRK_AUTO_CLEAR_INT;
1178
1179 switch (nhi->pdev->device) {
1180 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI:
1181 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI:
1182 /*
1183 * Falcon Ridge controller needs the end-to-end
1184 * flow control workaround to avoid losing Rx
1185 * packets when RING_FLAG_E2E is set.
1186 */
1187 nhi->quirks |= QUIRK_E2E;
1188 break;
1189 }
1190 }
1191 }
1192
nhi_check_iommu_pdev(struct pci_dev * pdev,void * data)1193 static int nhi_check_iommu_pdev(struct pci_dev *pdev, void *data)
1194 {
1195 if (!pdev->external_facing ||
1196 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION))
1197 return 0;
1198 *(bool *)data = true;
1199 return 1; /* Stop walking */
1200 }
1201
nhi_check_iommu(struct tb_nhi * nhi)1202 static void nhi_check_iommu(struct tb_nhi *nhi)
1203 {
1204 struct pci_bus *bus = nhi->pdev->bus;
1205 bool port_ok = false;
1206
1207 /*
1208 * Ideally what we'd do here is grab every PCI device that
1209 * represents a tunnelling adapter for this NHI and check their
1210 * status directly, but unfortunately USB4 seems to make it
1211 * obnoxiously difficult to reliably make any correlation.
1212 *
1213 * So for now we'll have to bodge it... Hoping that the system
1214 * is at least sane enough that an adapter is in the same PCI
1215 * segment as its NHI, if we can find *something* on that segment
1216 * which meets the requirements for Kernel DMA Protection, we'll
1217 * take that to imply that firmware is aware and has (hopefully)
1218 * done the right thing in general. We need to know that the PCI
1219 * layer has seen the ExternalFacingPort property which will then
1220 * inform the IOMMU layer to enforce the complete "untrusted DMA"
1221 * flow, but also that the IOMMU driver itself can be trusted not
1222 * to have been subverted by a pre-boot DMA attack.
1223 */
1224 while (bus->parent)
1225 bus = bus->parent;
1226
1227 pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok);
1228
1229 nhi->iommu_dma_protection = port_ok;
1230 dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n",
1231 str_enabled_disabled(port_ok));
1232 }
1233
nhi_reset(struct tb_nhi * nhi)1234 static void nhi_reset(struct tb_nhi *nhi)
1235 {
1236 ktime_t timeout;
1237 u32 val;
1238
1239 val = ioread32(nhi->iobase + REG_CAPS);
1240 /* Reset only v2 and later routers */
1241 if (FIELD_GET(REG_CAPS_VERSION_MASK, val) < REG_CAPS_VERSION_2)
1242 return;
1243
1244 if (!host_reset) {
1245 dev_dbg(&nhi->pdev->dev, "skipping host router reset\n");
1246 return;
1247 }
1248
1249 iowrite32(REG_RESET_HRR, nhi->iobase + REG_RESET);
1250 msleep(100);
1251
1252 timeout = ktime_add_ms(ktime_get(), 500);
1253 do {
1254 val = ioread32(nhi->iobase + REG_RESET);
1255 if (!(val & REG_RESET_HRR)) {
1256 dev_warn(&nhi->pdev->dev, "host router reset successful\n");
1257 return;
1258 }
1259 usleep_range(10, 20);
1260 } while (ktime_before(ktime_get(), timeout));
1261
1262 dev_warn(&nhi->pdev->dev, "timeout resetting host router\n");
1263 }
1264
nhi_init_msi(struct tb_nhi * nhi)1265 static int nhi_init_msi(struct tb_nhi *nhi)
1266 {
1267 struct pci_dev *pdev = nhi->pdev;
1268 struct device *dev = &pdev->dev;
1269 int res, irq, nvec;
1270
1271 /* In case someone left them on. */
1272 nhi_disable_interrupts(nhi);
1273
1274 nhi_enable_int_throttling(nhi);
1275
1276 ida_init(&nhi->msix_ida);
1277
1278 /*
1279 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1280 * get all MSI-X vectors and if we succeed, each ring will have
1281 * one MSI-X. If for some reason that does not work out, we
1282 * fallback to a single MSI.
1283 */
1284 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1285 PCI_IRQ_MSIX);
1286 if (nvec < 0) {
1287 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1288 if (nvec < 0)
1289 return nvec;
1290
1291 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1292
1293 irq = pci_irq_vector(nhi->pdev, 0);
1294 if (irq < 0)
1295 return irq;
1296
1297 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1298 IRQF_NO_SUSPEND, "thunderbolt", nhi);
1299 if (res)
1300 return dev_err_probe(dev, res, "request_irq failed, aborting\n");
1301 }
1302
1303 return 0;
1304 }
1305
nhi_imr_valid(struct pci_dev * pdev)1306 static bool nhi_imr_valid(struct pci_dev *pdev)
1307 {
1308 u8 val;
1309
1310 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1311 return !!val;
1312
1313 return true;
1314 }
1315
nhi_select_cm(struct tb_nhi * nhi)1316 static struct tb *nhi_select_cm(struct tb_nhi *nhi)
1317 {
1318 struct tb *tb;
1319
1320 /*
1321 * USB4 case is simple. If we got control of any of the
1322 * capabilities, we use software CM.
1323 */
1324 if (tb_acpi_is_native())
1325 return tb_probe(nhi);
1326
1327 /*
1328 * Either firmware based CM is running (we did not get control
1329 * from the firmware) or this is pre-USB4 PC so try first
1330 * firmware CM and then fallback to software CM.
1331 */
1332 tb = icm_probe(nhi);
1333 if (!tb)
1334 tb = tb_probe(nhi);
1335
1336 return tb;
1337 }
1338
nhi_probe(struct pci_dev * pdev,const struct pci_device_id * id)1339 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1340 {
1341 struct device *dev = &pdev->dev;
1342 struct tb_nhi *nhi;
1343 struct tb *tb;
1344 int res;
1345
1346 if (!nhi_imr_valid(pdev))
1347 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n");
1348
1349 res = pcim_enable_device(pdev);
1350 if (res)
1351 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n");
1352
1353 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1354 if (!nhi)
1355 return -ENOMEM;
1356
1357 nhi->pdev = pdev;
1358 nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1359
1360 nhi->iobase = pcim_iomap_region(pdev, 0, "thunderbolt");
1361 res = PTR_ERR_OR_ZERO(nhi->iobase);
1362 if (res)
1363 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n");
1364
1365 nhi->hop_count = ioread32(nhi->iobase + REG_CAPS) & 0x3ff;
1366 dev_dbg(dev, "total paths: %d\n", nhi->hop_count);
1367
1368 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1369 sizeof(*nhi->tx_rings), GFP_KERNEL);
1370 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1371 sizeof(*nhi->rx_rings), GFP_KERNEL);
1372 if (!nhi->tx_rings || !nhi->rx_rings)
1373 return -ENOMEM;
1374
1375 nhi_check_quirks(nhi);
1376 nhi_check_iommu(nhi);
1377 nhi_reset(nhi);
1378
1379 res = nhi_init_msi(nhi);
1380 if (res)
1381 return dev_err_probe(dev, res, "cannot enable MSI, aborting\n");
1382
1383 spin_lock_init(&nhi->lock);
1384
1385 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1386 if (res)
1387 return dev_err_probe(dev, res, "failed to set DMA mask\n");
1388
1389 pci_set_master(pdev);
1390
1391 if (nhi->ops && nhi->ops->init) {
1392 res = nhi->ops->init(nhi);
1393 if (res)
1394 return res;
1395 }
1396
1397 tb = nhi_select_cm(nhi);
1398 if (!tb)
1399 return dev_err_probe(dev, -ENODEV,
1400 "failed to determine connection manager, aborting\n");
1401
1402 dev_dbg(dev, "NHI initialized, starting thunderbolt\n");
1403
1404 res = tb_domain_add(tb, host_reset);
1405 if (res) {
1406 /*
1407 * At this point the RX/TX rings might already have been
1408 * activated. Do a proper shutdown.
1409 */
1410 tb_domain_put(tb);
1411 nhi_shutdown(nhi);
1412 return res;
1413 }
1414 pci_set_drvdata(pdev, tb);
1415
1416 device_wakeup_enable(&pdev->dev);
1417
1418 pm_runtime_allow(&pdev->dev);
1419 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1420 pm_runtime_use_autosuspend(&pdev->dev);
1421 pm_runtime_put_autosuspend(&pdev->dev);
1422
1423 return 0;
1424 }
1425
nhi_remove(struct pci_dev * pdev)1426 static void nhi_remove(struct pci_dev *pdev)
1427 {
1428 struct tb *tb = pci_get_drvdata(pdev);
1429 struct tb_nhi *nhi = tb->nhi;
1430
1431 pm_runtime_get_sync(&pdev->dev);
1432 pm_runtime_dont_use_autosuspend(&pdev->dev);
1433 pm_runtime_forbid(&pdev->dev);
1434
1435 tb_domain_remove(tb);
1436 nhi_shutdown(nhi);
1437 }
1438
1439 /*
1440 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1441 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1442 * resume_noirq until we are done.
1443 */
1444 static const struct dev_pm_ops nhi_pm_ops = {
1445 .suspend_noirq = nhi_suspend_noirq,
1446 .resume_noirq = nhi_resume_noirq,
1447 .freeze_noirq = nhi_freeze_noirq, /*
1448 * we just disable hotplug, the
1449 * pci-tunnels stay alive.
1450 */
1451 .thaw_noirq = nhi_thaw_noirq,
1452 .restore_noirq = nhi_resume_noirq,
1453 .suspend = nhi_suspend,
1454 .poweroff_noirq = nhi_poweroff_noirq,
1455 .poweroff = nhi_suspend,
1456 .complete = nhi_complete,
1457 .runtime_suspend = nhi_runtime_suspend,
1458 .runtime_resume = nhi_runtime_resume,
1459 };
1460
1461 static struct pci_device_id nhi_ids[] = {
1462 /*
1463 * We have to specify class, the TB bridges use the same device and
1464 * vendor (sub)id on gen 1 and gen 2 controllers.
1465 */
1466 {
1467 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1468 .vendor = PCI_VENDOR_ID_INTEL,
1469 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1470 .subvendor = 0x2222, .subdevice = 0x1111,
1471 },
1472 {
1473 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1474 .vendor = PCI_VENDOR_ID_INTEL,
1475 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1476 .subvendor = 0x2222, .subdevice = 0x1111,
1477 },
1478 {
1479 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1480 .vendor = PCI_VENDOR_ID_INTEL,
1481 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1482 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1483 },
1484 {
1485 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1486 .vendor = PCI_VENDOR_ID_INTEL,
1487 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1488 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1489 },
1490
1491 /* Thunderbolt 3 */
1492 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1493 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1494 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1495 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1496 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1497 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1498 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1499 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1500 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1501 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1502 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1503 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1504 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1505 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1506 /* Thunderbolt 4 */
1507 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1508 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1509 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1510 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1511 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
1512 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1513 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
1514 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1515 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0),
1516 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1517 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1),
1518 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1519 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0),
1520 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1521 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1),
1522 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1523 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0),
1524 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1525 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0),
1526 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1527 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1),
1528 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1529 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI0),
1530 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1531 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI1),
1532 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1533 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI0),
1534 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1535 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI1),
1536 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1537 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI0),
1538 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1539 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI1),
1540 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1541 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) },
1542 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) },
1543
1544 /* Any USB4 compliant host */
1545 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1546
1547 { 0,}
1548 };
1549
1550 MODULE_DEVICE_TABLE(pci, nhi_ids);
1551 MODULE_DESCRIPTION("Thunderbolt/USB4 core driver");
1552 MODULE_LICENSE("GPL");
1553
1554 static struct pci_driver nhi_driver = {
1555 .name = "thunderbolt",
1556 .id_table = nhi_ids,
1557 .probe = nhi_probe,
1558 .remove = nhi_remove,
1559 .shutdown = nhi_remove,
1560 .driver.pm = &nhi_pm_ops,
1561 };
1562
nhi_init(void)1563 static int __init nhi_init(void)
1564 {
1565 int ret;
1566
1567 ret = tb_domain_init();
1568 if (ret)
1569 return ret;
1570 ret = pci_register_driver(&nhi_driver);
1571 if (ret)
1572 tb_domain_exit();
1573 return ret;
1574 }
1575
nhi_unload(void)1576 static void __exit nhi_unload(void)
1577 {
1578 pci_unregister_driver(&nhi_driver);
1579 tb_domain_exit();
1580 }
1581
1582 rootfs_initcall(nhi_init);
1583 module_exit(nhi_unload);
1584