1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * * Neither the name of Intel Corporation nor the names of its 40 * contributors may be used to endorse or promote products derived 41 * from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #ifndef _SCU_REGISTERS_H_ 57 #define _SCU_REGISTERS_H_ 58 59 /** 60 * This file contains the constants and structures for the SCU memory mapped 61 * registers. 62 * 63 * 64 */ 65 66 #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000) 67 #define SCU_VIIT_ENTRY_ID_SHIFT (30) 68 69 #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000) 70 #define SCU_VIIT_ENTRY_FUNCTION_SHIFT (20) 71 72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800) 73 #define SCU_VIIT_ENTRY_IPPTMODE_SHIFT (12) 74 75 #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00) 76 #define SCU_VIIT_ENTRY_LPVIE_SHIFT (8) 77 78 #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF) 79 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0) 80 81 #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT) 82 #define SCU_VIIT_ENTRY_ID_VIIT (1 << SCU_VIIT_ENTRY_ID_SHIFT) 83 #define SCU_VIIT_ENTRY_ID_IIT (2 << SCU_VIIT_ENTRY_ID_SHIFT) 84 #define SCU_VIIT_ENTRY_ID_VIRT_EXP (3 << SCU_VIIT_ENTRY_ID_SHIFT) 85 86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT) 87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT) 88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT) 89 #define SCU_VIIT_IPPT_INITIATOR \ 90 (\ 91 SCU_VIIT_IPPT_SSP_INITIATOR \ 92 | SCU_VIIT_IPPT_SMP_INITIATOR \ 93 | SCU_VIIT_IPPT_STP_INITIATOR \ 94 ) 95 96 #define SCU_VIIT_STATUS_RNC_VALID (0x01 << SCU_VIIT_ENTRY_STATUS_SHIFT) 97 #define SCU_VIIT_STATUS_ADDRESS_VALID (0x02 << SCU_VIIT_ENTRY_STATUS_SHIFT) 98 #define SCU_VIIT_STATUS_RNI_VALID (0x04 << SCU_VIIT_ENTRY_STATUS_SHIFT) 99 #define SCU_VIIT_STATUS_ALL_VALID \ 100 (\ 101 SCU_VIIT_STATUS_RNC_VALID \ 102 | SCU_VIIT_STATUS_ADDRESS_VALID \ 103 | SCU_VIIT_STATUS_RNI_VALID \ 104 ) 105 106 #define SCU_VIIT_IPPT_SMP_TARGET (0x10 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT) 107 108 /** 109 * struct scu_viit_entry - This is the SCU Virtual Initiator Table Entry 110 * 111 * 112 */ 113 struct scu_viit_entry { 114 /** 115 * This must be encoded as to the type of initiator that is being constructed 116 * for this port. 117 */ 118 u32 status; 119 120 /** 121 * Virtual initiator high SAS Address 122 */ 123 u32 initiator_sas_address_hi; 124 125 /** 126 * Virtual initiator low SAS Address 127 */ 128 u32 initiator_sas_address_lo; 129 130 /** 131 * This must be 0 132 */ 133 u32 reserved; 134 135 }; 136 137 138 /* IIT Status Defines */ 139 #define SCU_IIT_ENTRY_ID_MASK (0xC0000000) 140 #define SCU_IIT_ENTRY_ID_SHIFT (30) 141 142 #define SCU_IIT_ENTRY_STATUS_UPDATE_MASK (0x20000000) 143 #define SCU_IIT_ENTRY_STATUS_UPDATE_SHIFT (29) 144 145 #define SCU_IIT_ENTRY_LPI_MASK (0x00000F00) 146 #define SCU_IIT_ENTRY_LPI_SHIFT (8) 147 148 #define SCU_IIT_ENTRY_STATUS_MASK (0x000000FF) 149 #define SCU_IIT_ENTRY_STATUS_SHIFT (0) 150 151 /* IIT Remote Initiator Defines */ 152 #define SCU_IIT_ENTRY_REMOTE_TAG_MASK (0x0000FFFF) 153 #define SCU_IIT_ENTRY_REMOTE_TAG_SHIFT (0) 154 155 #define SCU_IIT_ENTRY_REMOTE_RNC_MASK (0x0FFF0000) 156 #define SCU_IIT_ENTRY_REMOTE_RNC_SHIFT (16) 157 158 #define SCU_IIT_ENTRY_ID_INVALID (0 << SCU_IIT_ENTRY_ID_SHIFT) 159 #define SCU_IIT_ENTRY_ID_VIIT (1 << SCU_IIT_ENTRY_ID_SHIFT) 160 #define SCU_IIT_ENTRY_ID_IIT (2 << SCU_IIT_ENTRY_ID_SHIFT) 161 #define SCU_IIT_ENTRY_ID_VIRT_EXP (3 << SCU_IIT_ENTRY_ID_SHIFT) 162 163 /** 164 * struct scu_iit_entry - This will be implemented later when we support 165 * virtual functions 166 * 167 * 168 */ 169 struct scu_iit_entry { 170 u32 status; 171 u32 remote_initiator_sas_address_hi; 172 u32 remote_initiator_sas_address_lo; 173 u32 remote_initiator; 174 175 }; 176 177 /* Generate a value for an SCU register */ 178 #define SCU_GEN_VALUE(name, value) \ 179 (((value) << name ## _SHIFT) & (name ## _MASK)) 180 181 /* 182 * Generate a bit value for an SCU register 183 * Make sure that the register MASK is just a single bit */ 184 #define SCU_GEN_BIT(name) \ 185 SCU_GEN_VALUE(name, ((u32)1)) 186 187 #define SCU_SET_BIT(name, reg_value) \ 188 ((reg_value) | SCU_GEN_BIT(name)) 189 190 #define SCU_CLEAR_BIT(name, reg_value) \ 191 ((reg_value)$ ~(SCU_GEN_BIT(name))) 192 193 /* 194 * ***************************************************************************** 195 * Unions for bitfield definitions of SCU Registers 196 * SMU Post Context Port 197 * ***************************************************************************** */ 198 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0) 199 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFF) 200 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT (12) 201 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000) 202 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT (16) 203 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000) 204 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT (18) 205 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000) 206 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000) 207 208 #define SMU_PCP_GEN_VAL(name, value) \ 209 SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_ ## name, value) 210 211 /* ***************************************************************************** */ 212 #define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT (31) 213 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000) 214 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT (1) 215 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002) 216 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0) 217 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001) 218 #define SMU_INTERRUPT_STATUS_RESERVED_MASK (0x7FFFFFFC) 219 220 #define SMU_ISR_GEN_BIT(name) \ 221 SCU_GEN_BIT(SMU_INTERRUPT_STATUS_ ## name) 222 223 #define SMU_ISR_QUEUE_ERROR SMU_ISR_GEN_BIT(QUEUE_ERROR) 224 #define SMU_ISR_QUEUE_SUSPEND SMU_ISR_GEN_BIT(QUEUE_SUSPEND) 225 #define SMU_ISR_COMPLETION SMU_ISR_GEN_BIT(COMPLETION) 226 227 /* ***************************************************************************** */ 228 #define SMU_INTERRUPT_MASK_COMPLETION_SHIFT (31) 229 #define SMU_INTERRUPT_MASK_COMPLETION_MASK (0x80000000) 230 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT (1) 231 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK (0x00000002) 232 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0) 233 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK (0x00000001) 234 #define SMU_INTERRUPT_MASK_RESERVED_MASK (0x7FFFFFFC) 235 236 #define SMU_IMR_GEN_BIT(name) \ 237 SCU_GEN_BIT(SMU_INTERRUPT_MASK_ ## name) 238 239 #define SMU_IMR_QUEUE_ERROR SMU_IMR_GEN_BIT(QUEUE_ERROR) 240 #define SMU_IMR_QUEUE_SUSPEND SMU_IMR_GEN_BIT(QUEUE_SUSPEND) 241 #define SMU_IMR_COMPLETION SMU_IMR_GEN_BIT(COMPLETION) 242 243 /* ***************************************************************************** */ 244 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT (0) 245 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK (0x0000001F) 246 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT (8) 247 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK (0x0000FF00) 248 #define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK (0xFFFF00E0) 249 250 #define SMU_ICC_GEN_VAL(name, value) \ 251 SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_ ## name, value) 252 253 /* ***************************************************************************** */ 254 #define SMU_TASK_CONTEXT_RANGE_START_SHIFT (0) 255 #define SMU_TASK_CONTEXT_RANGE_START_MASK (0x00000FFF) 256 #define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT (16) 257 #define SMU_TASK_CONTEXT_RANGE_ENDING_MASK (0x0FFF0000) 258 #define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT (31) 259 #define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK (0x80000000) 260 #define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK (0x7000F000) 261 262 #define SMU_TCR_GEN_VAL(name, value) \ 263 SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_ ## name, value) 264 265 #define SMU_TCR_GEN_BIT(name, value) \ 266 SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_ ## name) 267 268 /* ***************************************************************************** */ 269 270 #define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT (0) 271 #define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK (0x00003FFF) 272 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT (15) 273 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK (0x00008000) 274 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT (16) 275 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK (0x03FF0000) 276 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT (26) 277 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK (0x04000000) 278 #define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK (0xF8004000) 279 280 #define SMU_CQPR_GEN_VAL(name, value) \ 281 SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_ ## name, value) 282 283 #define SMU_CQPR_GEN_BIT(name) \ 284 SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_ ## name) 285 286 /* ***************************************************************************** */ 287 288 #define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT (0) 289 #define SMU_COMPLETION_QUEUE_GET_POINTER_MASK (0x00003FFF) 290 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT (15) 291 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK (0x00008000) 292 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT (16) 293 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK (0x03FF0000) 294 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT (26) 295 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK (0x04000000) 296 #define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT (30) 297 #define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK (0x40000000) 298 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT (31) 299 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK (0x80000000) 300 #define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK (0x38004000) 301 302 #define SMU_CQGR_GEN_VAL(name, value) \ 303 SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_ ## name, value) 304 305 #define SMU_CQGR_GEN_BIT(name) \ 306 SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_ ## name) 307 308 #define SMU_CQGR_CYCLE_BIT \ 309 SMU_CQGR_GEN_BIT(CYCLE_BIT) 310 311 #define SMU_CQGR_EVENT_CYCLE_BIT \ 312 SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT) 313 314 #define SMU_CQGR_GET_POINTER_SET(value) \ 315 SMU_CQGR_GEN_VAL(POINTER, value) 316 317 318 /* ***************************************************************************** */ 319 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT (0) 320 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK (0x00003FFF) 321 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT (16) 322 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK (0x03FF0000) 323 #define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK (0xFC00C000) 324 325 #define SMU_CQC_GEN_VAL(name, value) \ 326 SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_ ## name, value) 327 328 #define SMU_CQC_QUEUE_LIMIT_SET(value) \ 329 SMU_CQC_GEN_VAL(QUEUE_LIMIT, value) 330 331 #define SMU_CQC_EVENT_LIMIT_SET(value) \ 332 SMU_CQC_GEN_VAL(EVENT_LIMIT, value) 333 334 335 /* ***************************************************************************** */ 336 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT (0) 337 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK (0x00000FFF) 338 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT (12) 339 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK (0x00007000) 340 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT (15) 341 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK (0x07FF8000) 342 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT (27) 343 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK (0x08000000) 344 #define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK (0xF0000000) 345 346 #define SMU_DCC_GEN_VAL(name, value) \ 347 SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_ ## name, value) 348 349 #define SMU_DCC_GET_MAX_PEG(value) \ 350 (\ 351 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK) \ 352 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \ 353 ) 354 355 #define SMU_DCC_GET_MAX_LP(value) \ 356 (\ 357 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \ 358 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \ 359 ) 360 361 #define SMU_DCC_GET_MAX_TC(value) \ 362 (\ 363 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \ 364 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \ 365 ) 366 367 #define SMU_DCC_GET_MAX_RNC(value) \ 368 (\ 369 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \ 370 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \ 371 ) 372 373 /* -------------------------------------------------------------------------- */ 374 375 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT (0) 376 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK (0x00000001) 377 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT (1) 378 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK (0x00000002) 379 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT (16) 380 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK (0x00010000) 381 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT (17) 382 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK (0x00020000) 383 #define SMU_CONTROL_STATUS_RESERVED_MASK (0xFFFCFFFC) 384 385 #define SMU_SMUCSR_GEN_BIT(name) \ 386 SCU_GEN_BIT(SMU_CONTROL_STATUS_ ## name) 387 388 #define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \ 389 (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED)) 390 391 #define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \ 392 (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED)) 393 394 #define SCU_RAM_INIT_COMPLETED \ 395 (\ 396 SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \ 397 | SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \ 398 ) 399 400 /* -------------------------------------------------------------------------- */ 401 402 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT (0) 403 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK (0x00000001) 404 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT (1) 405 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK (0x00000002) 406 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT (2) 407 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK (0x00000004) 408 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT (3) 409 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK (0x00000008) 410 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT (8) 411 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK (0x00000100) 412 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT (9) 413 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK (0x00000200) 414 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT (10) 415 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK (0x00000400) 416 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT (11) 417 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK (0x00000800) 418 419 #define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \ 420 ((1 << (pe)) << ((peg) * 8)) 421 422 #define SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \ 423 (\ 424 SMU_RESET_PROTOCOL_ENGINE(peg, 0) \ 425 | SMU_RESET_PROTOCOL_ENGINE(peg, 1) \ 426 | SMU_RESET_PROTOCOL_ENGINE(peg, 2) \ 427 | SMU_RESET_PROTOCOL_ENGINE(peg, 3) \ 428 ) 429 430 #define SMU_RESET_ALL_PROTOCOL_ENGINES() \ 431 (\ 432 SMU_RESET_PEG_PROTOCOL_ENGINES(0) \ 433 | SMU_RESET_PEG_PROTOCOL_ENGINES(1) \ 434 ) 435 436 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT (16) 437 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK (0x00010000) 438 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT (17) 439 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK (0x00020000) 440 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT (18) 441 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK (0x00040000) 442 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT (19) 443 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK (0x00080000) 444 445 #define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port) \ 446 ((1 << ((wide_port) / 2)) << ((peg) * 2) << 16) 447 448 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT (20) 449 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK (0x00100000) 450 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT (21) 451 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK (0x00200000) 452 #define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT (22) 453 #define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK (0x00400000) 454 455 /* 456 * It seems to make sense that if you are going to reset the protocol 457 * engine group that you would also reset all of the protocol engines */ 458 #define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg) \ 459 (\ 460 (1 << ((peg) + 20)) \ 461 | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \ 462 | SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \ 463 | SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \ 464 ) 465 466 #define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \ 467 (\ 468 SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \ 469 | SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \ 470 ) 471 472 #define SMU_RESET_SCU() (0xFFFFFFFF) 473 474 475 476 /* ***************************************************************************** */ 477 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT (0) 478 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK (0x00000FFF) 479 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT (16) 480 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK (0x0FFF0000) 481 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT (31) 482 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK (0x80000000) 483 #define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK (0x7000F000) 484 485 #define SMU_TCA_GEN_VAL(name, value) \ 486 SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name, value) 487 488 #define SMU_TCA_GEN_BIT(name) \ 489 SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name) 490 491 /* ***************************************************************************** */ 492 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT (0) 493 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK (0x00000FFF) 494 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK (0xFFFFF000) 495 496 #define SCU_UFQC_GEN_VAL(name, value) \ 497 SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_ ## name, value) 498 499 #define SCU_UFQC_QUEUE_SIZE_SET(value) \ 500 SCU_UFQC_GEN_VAL(QUEUE_SIZE, value) 501 502 /* ***************************************************************************** */ 503 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT (0) 504 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK (0x00000FFF) 505 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT (12) 506 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK (0x00001000) 507 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK (0xFFFFE000) 508 509 #define SCU_UFQPP_GEN_VAL(name, value) \ 510 SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name, value) 511 512 #define SCU_UFQPP_GEN_BIT(name) \ 513 SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name) 514 515 /* 516 * ***************************************************************************** 517 * * SDMA Registers 518 * ***************************************************************************** */ 519 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT (0) 520 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK (0x00000FFF) 521 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT (12) 522 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK (12) 523 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT (31) 524 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK (0x80000000) 525 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK (0x7FFFE000) 526 527 #define SCU_UFQGP_GEN_VAL(name, value) \ 528 SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name, value) 529 530 #define SCU_UFQGP_GEN_BIT(name) \ 531 SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name) 532 533 #define SCU_UFQGP_CYCLE_BIT(value) \ 534 SCU_UFQGP_GEN_BIT(CYCLE_BIT, value) 535 536 #define SCU_UFQGP_GET_POINTER(value) \ 537 SCU_UFQGP_GEN_VALUE(POINTER, value) 538 539 #define SCU_UFQGP_ENABLE(value) \ 540 (SCU_UFQGP_GEN_BIT(ENABLE) | value) 541 542 #define SCU_UFQGP_DISABLE(value) \ 543 (~SCU_UFQGP_GEN_BIT(ENABLE) & value) 544 545 #define SCU_UFQGP_VALUE(bit, value) \ 546 (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value)) 547 548 /* ***************************************************************************** */ 549 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT (0) 550 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK (0x0000FFFF) 551 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (16) 552 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00010000) 553 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT (17) 554 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK (0x00020000) 555 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT (18) 556 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK (0x00040000) 557 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT (19) 558 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK (0x00080000) 559 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT (20) 560 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK (0x00100000) 561 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT (21) 562 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK (0x00200000) 563 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT (22) 564 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK (0x00400000) 565 #define SCU_PDMA_CONFIGURATION_RESERVED_MASK (0xFF800000) 566 567 #define SCU_PDMACR_GEN_VALUE(name, value) \ 568 SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_ ## name, value) 569 570 #define SCU_PDMACR_GEN_BIT(name) \ 571 SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_ ## name) 572 573 #define SCU_PDMACR_BE_GEN_BIT(name) \ 574 SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_ ## name) 575 576 /* ***************************************************************************** */ 577 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (8) 578 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00000100) 579 580 #define SCU_CDMACR_GEN_BIT(name) \ 581 SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_ ## name) 582 583 /* 584 * ***************************************************************************** 585 * * SCU Link Layer Registers 586 * ***************************************************************************** */ 587 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT (0) 588 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK (0x000000FF) 589 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT (8) 590 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK (0x0000FF00) 591 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT (16) 592 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK (0x00FF0000) 593 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT (24) 594 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK (0xFF000000) 595 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK (0x00000000) 596 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK (0x7D00676F) 597 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK (0x00FF0000) 598 599 #define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \ 600 SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_ ## name, value) 601 602 603 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT (2) 604 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK (0x00000004) 605 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT (4) 606 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK (0x00000010) 607 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT (5) 608 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK (0x00000020) 609 #define SCU_LINK_STATUS_RESERVED_MASK (0xFFFFFFCD) 610 611 #define SCU_SAS_LLSTA_GEN_BIT(name) \ 612 SCU_GEN_BIT(SCU_LINK_STATUS_ ## name) 613 614 615 /* TODO: Where is the SATA_PSELTOV register? */ 616 617 /* 618 * ***************************************************************************** 619 * * SCU SAS Maximum Arbitration Wait Time Timeout Register 620 * ***************************************************************************** */ 621 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT (0) 622 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK (0x00007FFF) 623 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT (15) 624 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK (0x00008000) 625 626 #define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \ 627 SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name, value) 628 629 #define SCU_SAS_MAWTTOV_GEN_BIT(name) \ 630 SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name) 631 632 633 /* 634 * TODO: Where is the SAS_LNKTOV regsiter? 635 * TODO: Where is the SAS_PHYTOV register? */ 636 637 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT (1) 638 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK (0x00000002) 639 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT (2) 640 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK (0x00000004) 641 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT (3) 642 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK (0x00000008) 643 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT (8) 644 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK (0x00000100) 645 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT (9) 646 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK (0x00000200) 647 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT (10) 648 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK (0x00000400) 649 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT (11) 650 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK (0x00000800) 651 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT (16) 652 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK (0x000F0000) 653 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT (24) 654 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK (0x0F000000) 655 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT (28) 656 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK (0x70000000) 657 #define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK (0x80F0F1F1) 658 659 #define SCU_SAS_TIID_GEN_VAL(name, value) \ 660 SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name, value) 661 662 #define SCU_SAS_TIID_GEN_BIT(name) \ 663 SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name) 664 665 /* SAS Identify Frame PHY Identifier Register */ 666 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT (16) 667 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK (0x00010000) 668 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT (17) 669 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK (0x00020000) 670 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT (18) 671 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK (0x00040000) 672 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT (24) 673 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK (0xFF000000) 674 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK (0x00F800FF) 675 676 #define SCU_SAS_TIPID_GEN_VALUE(name, value) \ 677 SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name, value) 678 679 #define SCU_SAS_TIPID_GEN_BIT(name) \ 680 SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name) 681 682 683 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT (4) 684 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK (0x00000010) 685 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT (6) 686 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK (0x00000040) 687 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT (7) 688 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK (0x00000080) 689 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT (8) 690 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK (0x00000100) 691 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT (9) 692 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK (0x00000200) 693 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT (11) 694 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK (0x00000800) 695 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT (12) 696 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK (0x00001000) 697 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT (13) 698 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK (0x00002000) 699 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT (14) 700 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK (0x00004000) 701 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT (15) 702 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK (0x00008000) 703 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT (23) 704 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK (0x00800000) 705 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT (27) 706 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK (0x08000000) 707 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT (28) 708 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK (0x10000000) 709 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT (29) 710 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK (0x20000000) 711 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT (30) 712 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK (0x40000000) 713 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT (31) 714 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK (0x80000000) 715 #define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK (0x0100000F) 716 #define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK (0x4180100F) 717 #define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK (0x00000000) 718 719 #define SCU_SAS_PCFG_GEN_BIT(name) \ 720 SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name) 721 722 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT (0) 723 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK (0x000007FF) 724 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT (16) 725 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK (0x00ff0000) 726 727 #define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(name, value) \ 728 SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value) 729 730 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT (0) 731 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK (0x0003FFFF) 732 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT (31) 733 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK (0x80000000) 734 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK (0x7FFC0000) 735 736 #define SCU_ENSPINUP_GEN_VAL(name, value) \ 737 SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name, value) 738 739 #define SCU_ENSPINUP_GEN_BIT(name) \ 740 SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name) 741 742 743 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT (1) 744 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK (0x00000002) 745 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT (4) 746 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK (0x000000F0) 747 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT (8) 748 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK (0x00000100) 749 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT (9) 750 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK (0x00000201) 751 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT (10) 752 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK (0x00000401) 753 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT (11) 754 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK (0x00000801) 755 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT (12) 756 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK (0x00001001) 757 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT (13) 758 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK (0x00002001) 759 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT (31) 760 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK (0x80000000) 761 #define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK (0x00003F01) 762 #define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK (0x00000001) 763 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK (0x7FFFC00D) 764 765 #define SCU_SAS_PHYCAP_GEN_VAL(name, value) \ 766 SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name, value) 767 768 #define SCU_SAS_PHYCAP_GEN_BIT(name) \ 769 SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name) 770 771 772 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT (0) 773 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK (0x000000FF) 774 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT (31) 775 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK (0x80000000) 776 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK (0x7FFFFF00) 777 778 #define SCU_PSZGCR_GEN_VAL(name, value) \ 779 SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name, value) 780 781 #define SCU_PSZGCR_GEN_BIT(name) \ 782 SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name) 783 784 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT (1) 785 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK (0x00000002) 786 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT (2) 787 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK (0x00000004) 788 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT (4) 789 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK (0x00000010) 790 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT (5) 791 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK (0x00000020) 792 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT (16) 793 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK (0x00030000) 794 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT (19) 795 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK (0x00080000) 796 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT (20) 797 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK (0x00300000) 798 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT (23) 799 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK (0x00800000) 800 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT (24) 801 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK (0x03000000) 802 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT (27) 803 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK (0x08000000) 804 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT (28) 805 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK (0x30000000) 806 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT (31) 807 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK (0x80000000) 808 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK (0x4444FFC9) 809 810 #define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \ 811 SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val) 812 813 #define SCU_PEG_SCUVZECR_GEN_BIT(name) \ 814 SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name) 815 816 817 /* 818 * ***************************************************************************** 819 * * Port Task Scheduler registers shift and mask values 820 * ***************************************************************************** */ 821 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT (0) 822 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK (0x0000FFFF) 823 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT (16) 824 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK (0x00FF0000) 825 #define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT (24) 826 #define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK (0x01000000) 827 #define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT (25) 828 #define SCU_PTSG_CONTROL_ETM_ENABLE_MASK (0x02000000) 829 #define SCU_PTSG_CONTROL_DEFAULT_MASK (0x00020002) 830 #define SCU_PTSG_CONTROL_REQUIRED_MASK (0x00000000) 831 #define SCU_PTSG_CONTROL_RESERVED_MASK (0xFC000000) 832 833 #define SCU_PTSGCR_GEN_VAL(name, val) \ 834 SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val) 835 836 #define SCU_PTSGCR_GEN_BIT(name) \ 837 SCU_GEN_BIT(SCU_PTSG_CONTROL_ ## name) 838 839 840 /* ***************************************************************************** */ 841 #define SCU_PTSG_REAL_TIME_CLOCK_SHIFT (0) 842 #define SCU_PTSG_REAL_TIME_CLOCK_MASK (0x0000FFFF) 843 #define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK (0xFFFF0000) 844 845 #define SCU_RTCR_GEN_VAL(name, val) \ 846 SCU_GEN_VALUE(SCU_PTSG_ ## name, val) 847 848 849 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT (0) 850 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK (0x00FFFFFF) 851 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK (0xFF000000) 852 853 #define SCU_RTCCR_GEN_VAL(name, val) \ 854 SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val) 855 856 857 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT (0) 858 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK (0x00000001) 859 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT (1) 860 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK (0x00000002) 861 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK (0xFFFFFFFC) 862 863 #define SCU_PTSxCR_GEN_BIT(name) \ 864 SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ ## name) 865 866 867 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT (0) 868 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK (0x00000001) 869 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT (1) 870 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK (0x00000002) 871 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT (2) 872 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK (0x00000004) 873 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK (0xFFFFFFF8) 874 875 #define SCU_PTSxSR_GEN_BIT(name) \ 876 SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name) 877 878 /* 879 * ***************************************************************************** 880 * * SMU Registers 881 * ***************************************************************************** */ 882 883 /* 884 * ---------------------------------------------------------------------------- 885 * SMU Registers 886 * These registers are based off of BAR0 887 * 888 * To calculate the offset for other functions use 889 * BAR0 + FN# * SystemPageSize * 2 890 * 891 * The TCA is only accessable from FN#0 (Physical Function) and each 892 * is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or 893 * TCA0 for FN#0 is at BAR0 + 0x0400 894 * TCA1 for FN#1 is at BAR0 + 0x0404 895 * etc. 896 * ---------------------------------------------------------------------------- 897 * Accessable to all FN#s */ 898 #define SCU_SMU_PCP_OFFSET 0x0000 899 #define SCU_SMU_AMR_OFFSET 0x0004 900 #define SCU_SMU_ISR_OFFSET 0x0010 901 #define SCU_SMU_IMR_OFFSET 0x0014 902 #define SCU_SMU_ICC_OFFSET 0x0018 903 #define SCU_SMU_HTTLBAR_OFFSET 0x0020 904 #define SCU_SMU_HTTUBAR_OFFSET 0x0024 905 #define SCU_SMU_TCR_OFFSET 0x0028 906 #define SCU_SMU_CQLBAR_OFFSET 0x0030 907 #define SCU_SMU_CQUBAR_OFFSET 0x0034 908 #define SCU_SMU_CQPR_OFFSET 0x0040 909 #define SCU_SMU_CQGR_OFFSET 0x0044 910 #define SCU_SMU_CQC_OFFSET 0x0048 911 /* Accessable to FN#0 only */ 912 #define SCU_SMU_RNCLBAR_OFFSET 0x0080 913 #define SCU_SMU_RNCUBAR_OFFSET 0x0084 914 #define SCU_SMU_DCC_OFFSET 0x0090 915 #define SCU_SMU_DFC_OFFSET 0x0094 916 #define SCU_SMU_SMUCSR_OFFSET 0x0098 917 #define SCU_SMU_SCUSRCR_OFFSET 0x009C 918 #define SCU_SMU_SMAW_OFFSET 0x00A0 919 #define SCU_SMU_SMDW_OFFSET 0x00A4 920 /* Accessable to FN#0 only */ 921 #define SCU_SMU_TCA_OFFSET 0x0400 922 /* Accessable to all FN#s */ 923 #define SCU_SMU_MT_MLAR0_OFFSET 0x2000 924 #define SCU_SMU_MT_MUAR0_OFFSET 0x2004 925 #define SCU_SMU_MT_MDR0_OFFSET 0x2008 926 #define SCU_SMU_MT_VCR0_OFFSET 0x200C 927 #define SCU_SMU_MT_MLAR1_OFFSET 0x2010 928 #define SCU_SMU_MT_MUAR1_OFFSET 0x2014 929 #define SCU_SMU_MT_MDR1_OFFSET 0x2018 930 #define SCU_SMU_MT_VCR1_OFFSET 0x201C 931 #define SCU_SMU_MPBA_OFFSET 0x3000 932 933 /** 934 * struct smu_registers - These are the SMU registers 935 * 936 * 937 */ 938 struct smu_registers { 939 /* 0x0000 PCP */ 940 u32 post_context_port; 941 /* 0x0004 AMR */ 942 u32 address_modifier; 943 u32 reserved_08; 944 u32 reserved_0C; 945 /* 0x0010 ISR */ 946 u32 interrupt_status; 947 /* 0x0014 IMR */ 948 u32 interrupt_mask; 949 /* 0x0018 ICC */ 950 u32 interrupt_coalesce_control; 951 u32 reserved_1C; 952 /* 0x0020 HTTLBAR */ 953 u32 host_task_table_lower; 954 /* 0x0024 HTTUBAR */ 955 u32 host_task_table_upper; 956 /* 0x0028 TCR */ 957 u32 task_context_range; 958 u32 reserved_2C; 959 /* 0x0030 CQLBAR */ 960 u32 completion_queue_lower; 961 /* 0x0034 CQUBAR */ 962 u32 completion_queue_upper; 963 u32 reserved_38; 964 u32 reserved_3C; 965 /* 0x0040 CQPR */ 966 u32 completion_queue_put; 967 /* 0x0044 CQGR */ 968 u32 completion_queue_get; 969 /* 0x0048 CQC */ 970 u32 completion_queue_control; 971 u32 reserved_4C; 972 u32 reserved_5x[4]; 973 u32 reserved_6x[4]; 974 u32 reserved_7x[4]; 975 /* 976 * Accessable to FN#0 only 977 * 0x0080 RNCLBAR */ 978 u32 remote_node_context_lower; 979 /* 0x0084 RNCUBAR */ 980 u32 remote_node_context_upper; 981 u32 reserved_88; 982 u32 reserved_8C; 983 /* 0x0090 DCC */ 984 u32 device_context_capacity; 985 /* 0x0094 DFC */ 986 u32 device_function_capacity; 987 /* 0x0098 SMUCSR */ 988 u32 control_status; 989 /* 0x009C SCUSRCR */ 990 u32 soft_reset_control; 991 /* 0x00A0 SMAW */ 992 u32 mmr_address_window; 993 /* 0x00A4 SMDW */ 994 u32 mmr_data_window; 995 u32 reserved_A8; 996 u32 reserved_AC; 997 /* A whole bunch of reserved space */ 998 u32 reserved_Bx[4]; 999 u32 reserved_Cx[4]; 1000 u32 reserved_Dx[4]; 1001 u32 reserved_Ex[4]; 1002 u32 reserved_Fx[4]; 1003 u32 reserved_1xx[64]; 1004 u32 reserved_2xx[64]; 1005 u32 reserved_3xx[64]; 1006 /* 1007 * Accessable to FN#0 only 1008 * 0x0400 TCA */ 1009 u32 task_context_assignment[256]; 1010 /* MSI-X registers not included */ 1011 }; 1012 1013 /* 1014 * ***************************************************************************** 1015 * SDMA Registers 1016 * ***************************************************************************** */ 1017 #define SCU_SDMA_BASE 0x6000 1018 #define SCU_SDMA_PUFATLHAR_OFFSET 0x0000 1019 #define SCU_SDMA_PUFATUHAR_OFFSET 0x0004 1020 #define SCU_SDMA_UFLHBAR_OFFSET 0x0008 1021 #define SCU_SDMA_UFUHBAR_OFFSET 0x000C 1022 #define SCU_SDMA_UFQC_OFFSET 0x0010 1023 #define SCU_SDMA_UFQPP_OFFSET 0x0014 1024 #define SCU_SDMA_UFQGP_OFFSET 0x0018 1025 #define SCU_SDMA_PDMACR_OFFSET 0x001C 1026 #define SCU_SDMA_CDMACR_OFFSET 0x0080 1027 1028 /** 1029 * struct scu_sdma_registers - These are the SCU SDMA Registers 1030 * 1031 * 1032 */ 1033 struct scu_sdma_registers { 1034 /* 0x0000 PUFATLHAR */ 1035 u32 uf_address_table_lower; 1036 /* 0x0004 PUFATUHAR */ 1037 u32 uf_address_table_upper; 1038 /* 0x0008 UFLHBAR */ 1039 u32 uf_header_base_address_lower; 1040 /* 0x000C UFUHBAR */ 1041 u32 uf_header_base_address_upper; 1042 /* 0x0010 UFQC */ 1043 u32 unsolicited_frame_queue_control; 1044 /* 0x0014 UFQPP */ 1045 u32 unsolicited_frame_put_pointer; 1046 /* 0x0018 UFQGP */ 1047 u32 unsolicited_frame_get_pointer; 1048 /* 0x001C PDMACR */ 1049 u32 pdma_configuration; 1050 /* Reserved until offset 0x80 */ 1051 u32 reserved_0020_007C[0x18]; 1052 /* 0x0080 CDMACR */ 1053 u32 cdma_configuration; 1054 /* Remainder SDMA register space */ 1055 u32 reserved_0084_0400[0xDF]; 1056 1057 }; 1058 1059 /* 1060 * ***************************************************************************** 1061 * * SCU Link Registers 1062 * ***************************************************************************** */ 1063 #define SCU_PEG0_OFFSET 0x0000 1064 #define SCU_PEG1_OFFSET 0x8000 1065 1066 #define SCU_TL0_OFFSET 0x0000 1067 #define SCU_TL1_OFFSET 0x0400 1068 #define SCU_TL2_OFFSET 0x0800 1069 #define SCU_TL3_OFFSET 0x0C00 1070 1071 #define SCU_LL_OFFSET 0x0080 1072 #define SCU_LL0_OFFSET (SCU_TL0_OFFSET + SCU_LL_OFFSET) 1073 #define SCU_LL1_OFFSET (SCU_TL1_OFFSET + SCU_LL_OFFSET) 1074 #define SCU_LL2_OFFSET (SCU_TL2_OFFSET + SCU_LL_OFFSET) 1075 #define SCU_LL3_OFFSET (SCU_TL3_OFFSET + SCU_LL_OFFSET) 1076 1077 /* Transport Layer Offsets (PEG + TL) */ 1078 #define SCU_TLCR_OFFSET 0x0000 1079 #define SCU_TLADTR_OFFSET 0x0004 1080 #define SCU_TLTTMR_OFFSET 0x0008 1081 #define SCU_TLEECR0_OFFSET 0x000C 1082 #define SCU_STPTLDARNI_OFFSET 0x0010 1083 1084 1085 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT (0) 1086 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK (0x00000001) 1087 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT (1) 1088 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK (0x00000002) 1089 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT (3) 1090 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK (0x00000008) 1091 #define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT (4) 1092 #define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK (0x00000010) 1093 #define SCU_TLCR_RESERVED_MASK (0xFFFFFFEB) 1094 1095 #define SCU_TLCR_GEN_BIT(name) \ 1096 SCU_GEN_BIT(SCU_TLCR_ ## name) 1097 1098 /** 1099 * struct scu_transport_layer_registers - These are the SCU Transport Layer 1100 * registers 1101 * 1102 * 1103 */ 1104 struct scu_transport_layer_registers { 1105 /* 0x0000 TLCR */ 1106 u32 control; 1107 /* 0x0004 TLADTR */ 1108 u32 arbitration_delay_timer; 1109 /* 0x0008 TLTTMR */ 1110 u32 timer_test_mode; 1111 /* 0x000C reserved */ 1112 u32 reserved_0C; 1113 /* 0x0010 STPTLDARNI */ 1114 u32 stp_rni; 1115 /* 0x0014 TLFEWPORCTRL */ 1116 u32 tlfe_wpo_read_control; 1117 /* 0x0018 TLFEWPORDATA */ 1118 u32 tlfe_wpo_read_data; 1119 /* 0x001C RXTLSSCSR1 */ 1120 u32 rxtl_single_step_control_status_1; 1121 /* 0x0020 RXTLSSCSR2 */ 1122 u32 rxtl_single_step_control_status_2; 1123 /* 0x0024 AWTRDDCR */ 1124 u32 tlfe_awt_retry_delay_debug_control; 1125 /* Remainder of TL memory space */ 1126 u32 reserved_0028_007F[0x16]; 1127 1128 }; 1129 1130 /* Protocol Engine Group Registers */ 1131 #define SCU_SCUVZECRx_OFFSET 0x1080 1132 1133 /* Link Layer Offsets (PEG + TL + LL) */ 1134 #define SCU_SAS_SPDTOV_OFFSET 0x0000 1135 #define SCU_SAS_LLSTA_OFFSET 0x0004 1136 #define SCU_SATA_PSELTOV_OFFSET 0x0008 1137 #define SCU_SAS_TIMETOV_OFFSET 0x0010 1138 #define SCU_SAS_LOSTOT_OFFSET 0x0014 1139 #define SCU_SAS_LNKTOV_OFFSET 0x0018 1140 #define SCU_SAS_PHYTOV_OFFSET 0x001C 1141 #define SCU_SAS_AFERCNT_OFFSET 0x0020 1142 #define SCU_SAS_WERCNT_OFFSET 0x0024 1143 #define SCU_SAS_TIID_OFFSET 0x0028 1144 #define SCU_SAS_TIDNH_OFFSET 0x002C 1145 #define SCU_SAS_TIDNL_OFFSET 0x0030 1146 #define SCU_SAS_TISSAH_OFFSET 0x0034 1147 #define SCU_SAS_TISSAL_OFFSET 0x0038 1148 #define SCU_SAS_TIPID_OFFSET 0x003C 1149 #define SCU_SAS_TIRES2_OFFSET 0x0040 1150 #define SCU_SAS_ADRSTA_OFFSET 0x0044 1151 #define SCU_SAS_MAWTTOV_OFFSET 0x0048 1152 #define SCU_SAS_FRPLDFIL_OFFSET 0x0054 1153 #define SCU_SAS_RFCNT_OFFSET 0x0060 1154 #define SCU_SAS_TFCNT_OFFSET 0x0064 1155 #define SCU_SAS_RFDCNT_OFFSET 0x0068 1156 #define SCU_SAS_TFDCNT_OFFSET 0x006C 1157 #define SCU_SAS_LERCNT_OFFSET 0x0070 1158 #define SCU_SAS_RDISERRCNT_OFFSET 0x0074 1159 #define SCU_SAS_CRERCNT_OFFSET 0x0078 1160 #define SCU_STPCTL_OFFSET 0x007C 1161 #define SCU_SAS_PCFG_OFFSET 0x0080 1162 #define SCU_SAS_CLKSM_OFFSET 0x0084 1163 #define SCU_SAS_TXCOMWAKE_OFFSET 0x0088 1164 #define SCU_SAS_TXCOMINIT_OFFSET 0x008C 1165 #define SCU_SAS_TXCOMSAS_OFFSET 0x0090 1166 #define SCU_SAS_COMINIT_OFFSET 0x0094 1167 #define SCU_SAS_COMWAKE_OFFSET 0x0098 1168 #define SCU_SAS_COMSAS_OFFSET 0x009C 1169 #define SCU_SAS_SFERCNT_OFFSET 0x00A0 1170 #define SCU_SAS_CDFERCNT_OFFSET 0x00A4 1171 #define SCU_SAS_DNFERCNT_OFFSET 0x00A8 1172 #define SCU_SAS_PRSTERCNT_OFFSET 0x00AC 1173 #define SCU_SAS_CNTCTL_OFFSET 0x00B0 1174 #define SCU_SAS_SSPTOV_OFFSET 0x00B4 1175 #define SCU_FTCTL_OFFSET 0x00B8 1176 #define SCU_FRCTL_OFFSET 0x00BC 1177 #define SCU_FTWMRK_OFFSET 0x00C0 1178 #define SCU_ENSPINUP_OFFSET 0x00C4 1179 #define SCU_SAS_TRNTOV_OFFSET 0x00C8 1180 #define SCU_SAS_PHYCAP_OFFSET 0x00CC 1181 #define SCU_SAS_PHYCTL_OFFSET 0x00D0 1182 #define SCU_SAS_LLCTL_OFFSET 0x00D8 1183 #define SCU_AFE_XCVRCR_OFFSET 0x00DC 1184 #define SCU_AFE_LUTCR_OFFSET 0x00E0 1185 1186 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT (0UL) 1187 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK (0x000000FFUL) 1188 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT (8UL) 1189 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK (0x0000FF00UL) 1190 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT (16UL) 1191 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK (0x00FF0000UL) 1192 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT (24UL) 1193 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK (0xFF000000UL) 1194 1195 #define SCU_SAS_PHYTOV_GEN_VAL(name, value) \ 1196 SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value) 1197 1198 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT (0) 1199 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK (0x00000003) 1200 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1 (0) 1201 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2 (1) 1202 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3 (2) 1203 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT (2) 1204 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK (0x000003FC) 1205 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT (16) 1206 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK (0x00010000) 1207 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT (17) 1208 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK (0x00020000) 1209 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT (24) 1210 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK (0xFF000000) 1211 #define SCU_SAS_LINK_LAYER_CONTROL_RESERVED (0x00FCFC00) 1212 1213 #define SCU_SAS_LLCTL_GEN_VAL(name, value) \ 1214 SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_ ## name, value) 1215 1216 #define SCU_SAS_LLCTL_GEN_BIT(name) \ 1217 SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_ ## name) 1218 1219 1220 /* #define SCU_FRXHECR_DCNT_OFFSET 0x00B0 */ 1221 #define SCU_PSZGCR_OFFSET 0x00E4 1222 #define SCU_SAS_RECPHYCAP_OFFSET 0x00E8 1223 /* #define SCU_TX_LUTSEL_OFFSET 0x00B8 */ 1224 1225 #define SCU_SAS_PTxC_OFFSET 0x00D4 /* Same offset as SAS_TCTSTM */ 1226 1227 /** 1228 * struct scu_link_layer_registers - SCU Link Layer Registers 1229 * 1230 * 1231 */ 1232 struct scu_link_layer_registers { 1233 /* 0x0000 SAS_SPDTOV */ 1234 u32 speed_negotiation_timers; 1235 /* 0x0004 SAS_LLSTA */ 1236 u32 link_layer_status; 1237 /* 0x0008 SATA_PSELTOV */ 1238 u32 port_selector_timeout; 1239 u32 reserved0C; 1240 /* 0x0010 SAS_TIMETOV */ 1241 u32 timeout_unit_value; 1242 /* 0x0014 SAS_RCDTOV */ 1243 u32 rcd_timeout; 1244 /* 0x0018 SAS_LNKTOV */ 1245 u32 link_timer_timeouts; 1246 /* 0x001C SAS_PHYTOV */ 1247 u32 sas_phy_timeouts; 1248 /* 0x0020 SAS_AFERCNT */ 1249 u32 received_address_frame_error_counter; 1250 /* 0x0024 SAS_WERCNT */ 1251 u32 invalid_dword_counter; 1252 /* 0x0028 SAS_TIID */ 1253 u32 transmit_identification; 1254 /* 0x002C SAS_TIDNH */ 1255 u32 sas_device_name_high; 1256 /* 0x0030 SAS_TIDNL */ 1257 u32 sas_device_name_low; 1258 /* 0x0034 SAS_TISSAH */ 1259 u32 source_sas_address_high; 1260 /* 0x0038 SAS_TISSAL */ 1261 u32 source_sas_address_low; 1262 /* 0x003C SAS_TIPID */ 1263 u32 identify_frame_phy_id; 1264 /* 0x0040 SAS_TIRES2 */ 1265 u32 identify_frame_reserved; 1266 /* 0x0044 SAS_ADRSTA */ 1267 u32 received_address_frame; 1268 /* 0x0048 SAS_MAWTTOV */ 1269 u32 maximum_arbitration_wait_timer_timeout; 1270 /* 0x004C SAS_PTxC */ 1271 u32 transmit_primitive; 1272 /* 0x0050 SAS_RORES */ 1273 u32 error_counter_event_notification_control; 1274 /* 0x0054 SAS_FRPLDFIL */ 1275 u32 frxq_payload_fill_threshold; 1276 /* 0x0058 SAS_LLHANG_TOT */ 1277 u32 link_layer_hang_detection_timeout; 1278 u32 reserved_5C; 1279 /* 0x0060 SAS_RFCNT */ 1280 u32 received_frame_count; 1281 /* 0x0064 SAS_TFCNT */ 1282 u32 transmit_frame_count; 1283 /* 0x0068 SAS_RFDCNT */ 1284 u32 received_dword_count; 1285 /* 0x006C SAS_TFDCNT */ 1286 u32 transmit_dword_count; 1287 /* 0x0070 SAS_LERCNT */ 1288 u32 loss_of_sync_error_count; 1289 /* 0x0074 SAS_RDISERRCNT */ 1290 u32 running_disparity_error_count; 1291 /* 0x0078 SAS_CRERCNT */ 1292 u32 received_frame_crc_error_count; 1293 /* 0x007C STPCTL */ 1294 u32 stp_control; 1295 /* 0x0080 SAS_PCFG */ 1296 u32 phy_configuration; 1297 /* 0x0084 SAS_CLKSM */ 1298 u32 clock_skew_management; 1299 /* 0x0088 SAS_TXCOMWAKE */ 1300 u32 transmit_comwake_signal; 1301 /* 0x008C SAS_TXCOMINIT */ 1302 u32 transmit_cominit_signal; 1303 /* 0x0090 SAS_TXCOMSAS */ 1304 u32 transmit_comsas_signal; 1305 /* 0x0094 SAS_COMINIT */ 1306 u32 cominit_control; 1307 /* 0x0098 SAS_COMWAKE */ 1308 u32 comwake_control; 1309 /* 0x009C SAS_COMSAS */ 1310 u32 comsas_control; 1311 /* 0x00A0 SAS_SFERCNT */ 1312 u32 received_short_frame_count; 1313 /* 0x00A4 SAS_CDFERCNT */ 1314 u32 received_frame_without_credit_count; 1315 /* 0x00A8 SAS_DNFERCNT */ 1316 u32 received_frame_after_done_count; 1317 /* 0x00AC SAS_PRSTERCNT */ 1318 u32 phy_reset_problem_count; 1319 /* 0x00B0 SAS_CNTCTL */ 1320 u32 counter_control; 1321 /* 0x00B4 SAS_SSPTOV */ 1322 u32 ssp_timer_timeout_values; 1323 /* 0x00B8 FTCTL */ 1324 u32 ftx_control; 1325 /* 0x00BC FRCTL */ 1326 u32 frx_control; 1327 /* 0x00C0 FTWMRK */ 1328 u32 ftx_watermark; 1329 /* 0x00C4 ENSPINUP */ 1330 u32 notify_enable_spinup_control; 1331 /* 0x00C8 SAS_TRNTOV */ 1332 u32 sas_training_sequence_timer_values; 1333 /* 0x00CC SAS_PHYCAP */ 1334 u32 phy_capabilities; 1335 /* 0x00D0 SAS_PHYCTL */ 1336 u32 phy_control; 1337 u32 reserved_d4; 1338 /* 0x00D8 LLCTL */ 1339 u32 link_layer_control; 1340 /* 0x00DC AFE_XCVRCR */ 1341 u32 afe_xcvr_control; 1342 /* 0x00E0 AFE_LUTCR */ 1343 u32 afe_lookup_table_control; 1344 /* 0x00E4 PSZGCR */ 1345 u32 phy_source_zone_group_control; 1346 /* 0x00E8 SAS_RECPHYCAP */ 1347 u32 receive_phycap; 1348 u32 reserved_ec; 1349 /* 0x00F0 SNAFERXRSTCTL */ 1350 u32 speed_negotiation_afe_rx_reset_control; 1351 /* 0x00F4 SAS_SSIPMCTL */ 1352 u32 power_management_control; 1353 /* 0x00F8 SAS_PSPREQ_PRIM */ 1354 u32 sas_pm_partial_request_primitive; 1355 /* 0x00FC SAS_PSSREQ_PRIM */ 1356 u32 sas_pm_slumber_request_primitive; 1357 /* 0x0100 SAS_PPSACK_PRIM */ 1358 u32 sas_pm_ack_primitive_register; 1359 /* 0x0104 SAS_PSNAK_PRIM */ 1360 u32 sas_pm_nak_primitive_register; 1361 /* 0x0108 SAS_SSIPMTOV */ 1362 u32 sas_primitive_timeout; 1363 u32 reserved_10c; 1364 /* 0x0110 - 0x011C PLAPRDCTRLxREG */ 1365 u32 pla_product_control[4]; 1366 /* 0x0120 PLAPRDSUMREG */ 1367 u32 pla_product_sum; 1368 /* 0x0124 PLACONTROLREG */ 1369 u32 pla_control; 1370 /* Remainder of memory space 896 bytes */ 1371 u32 reserved_0128_037f[0x96]; 1372 1373 }; 1374 1375 /* 1376 * 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC 1377 * u32 primitive_transmit_control; */ 1378 1379 /* 1380 * ---------------------------------------------------------------------------- 1381 * SGPIO 1382 * ---------------------------------------------------------------------------- */ 1383 #define SCU_SGPIO_OFFSET 0x1400 1384 1385 /* #define SCU_SGPIO_OFFSET 0x6000 // later moves to 0x1400 see HSD 652625 */ 1386 #define SCU_SGPIO_SGICR_OFFSET 0x0000 1387 #define SCU_SGPIO_SGPBR_OFFSET 0x0004 1388 #define SCU_SGPIO_SGSDLR_OFFSET 0x0008 1389 #define SCU_SGPIO_SGSDUR_OFFSET 0x000C 1390 #define SCU_SGPIO_SGSIDLR_OFFSET 0x0010 1391 #define SCU_SGPIO_SGSIDUR_OFFSET 0x0014 1392 #define SCU_SGPIO_SGVSCR_OFFSET 0x0018 1393 /* Address from 0x0820 to 0x083C */ 1394 #define SCU_SGPIO_SGODSR_OFFSET 0x0020 1395 1396 /** 1397 * struct scu_sgpio_registers - SCU SGPIO Registers 1398 * 1399 * 1400 */ 1401 struct scu_sgpio_registers { 1402 /* 0x0000 SGPIO_SGICR */ 1403 u32 interface_control; 1404 /* 0x0004 SGPIO_SGPBR */ 1405 u32 blink_rate; 1406 /* 0x0008 SGPIO_SGSDLR */ 1407 u32 start_drive_lower; 1408 /* 0x000C SGPIO_SGSDUR */ 1409 u32 start_drive_upper; 1410 /* 0x0010 SGPIO_SGSIDLR */ 1411 u32 serial_input_lower; 1412 /* 0x0014 SGPIO_SGSIDUR */ 1413 u32 serial_input_upper; 1414 /* 0x0018 SGPIO_SGVSCR */ 1415 u32 vendor_specific_code; 1416 /* 0x001C Reserved */ 1417 u32 reserved_001c; 1418 /* 0x0020 SGPIO_SGODSR */ 1419 u32 output_data_select[8]; 1420 /* Remainder of memory space 256 bytes */ 1421 u32 reserved_1444_14ff[0x30]; 1422 1423 }; 1424 1425 /* 1426 * ***************************************************************************** 1427 * * Defines for VIIT entry offsets 1428 * * Access additional entries by SCU_VIIT_BASE + index * 0x10 1429 * ***************************************************************************** */ 1430 #define SCU_VIIT_BASE 0x1c00 1431 1432 struct scu_viit_registers { 1433 u32 registers[256]; 1434 }; 1435 1436 /* 1437 * ***************************************************************************** 1438 * * SCU PORT TASK SCHEDULER REGISTERS 1439 * ***************************************************************************** */ 1440 1441 #define SCU_PTSG_BASE 0x1000 1442 1443 #define SCU_PTSG_PTSGCR_OFFSET 0x0000 1444 #define SCU_PTSG_RTCR_OFFSET 0x0004 1445 #define SCU_PTSG_RTCCR_OFFSET 0x0008 1446 #define SCU_PTSG_PTS0CR_OFFSET 0x0010 1447 #define SCU_PTSG_PTS0SR_OFFSET 0x0014 1448 #define SCU_PTSG_PTS1CR_OFFSET 0x0018 1449 #define SCU_PTSG_PTS1SR_OFFSET 0x001C 1450 #define SCU_PTSG_PTS2CR_OFFSET 0x0020 1451 #define SCU_PTSG_PTS2SR_OFFSET 0x0024 1452 #define SCU_PTSG_PTS3CR_OFFSET 0x0028 1453 #define SCU_PTSG_PTS3SR_OFFSET 0x002C 1454 #define SCU_PTSG_PCSPE0CR_OFFSET 0x0030 1455 #define SCU_PTSG_PCSPE1CR_OFFSET 0x0034 1456 #define SCU_PTSG_PCSPE2CR_OFFSET 0x0038 1457 #define SCU_PTSG_PCSPE3CR_OFFSET 0x003C 1458 #define SCU_PTSG_ETMTSCCR_OFFSET 0x0040 1459 #define SCU_PTSG_ETMRNSCCR_OFFSET 0x0044 1460 1461 /** 1462 * struct scu_port_task_scheduler_registers - These are the control/stats pairs 1463 * for each Port Task Scheduler. 1464 * 1465 * 1466 */ 1467 struct scu_port_task_scheduler_registers { 1468 u32 control; 1469 u32 status; 1470 }; 1471 1472 /** 1473 * struct scu_port_task_scheduler_group_registers - These are the PORT Task 1474 * Scheduler registers 1475 * 1476 * 1477 */ 1478 struct scu_port_task_scheduler_group_registers { 1479 /* 0x0000 PTSGCR */ 1480 u32 control; 1481 /* 0x0004 RTCR */ 1482 u32 real_time_clock; 1483 /* 0x0008 RTCCR */ 1484 u32 real_time_clock_control; 1485 /* 0x000C */ 1486 u32 reserved_0C; 1487 /* 1488 * 0x0010 PTS0CR 1489 * 0x0014 PTS0SR 1490 * 0x0018 PTS1CR 1491 * 0x001C PTS1SR 1492 * 0x0020 PTS2CR 1493 * 0x0024 PTS2SR 1494 * 0x0028 PTS3CR 1495 * 0x002C PTS3SR */ 1496 struct scu_port_task_scheduler_registers port[4]; 1497 /* 1498 * 0x0030 PCSPE0CR 1499 * 0x0034 PCSPE1CR 1500 * 0x0038 PCSPE2CR 1501 * 0x003C PCSPE3CR */ 1502 u32 protocol_engine[4]; 1503 /* 0x0040 ETMTSCCR */ 1504 u32 tc_scanning_interval_control; 1505 /* 0x0044 ETMRNSCCR */ 1506 u32 rnc_scanning_interval_control; 1507 /* Remainder of memory space 128 bytes */ 1508 u32 reserved_1048_107f[0x0E]; 1509 1510 }; 1511 1512 #define SCU_PTSG_SCUVZECR_OFFSET 0x003C 1513 1514 /* 1515 * ***************************************************************************** 1516 * * AFE REGISTERS 1517 * ***************************************************************************** */ 1518 #define SCU_AFE_MMR_BASE 0xE000 1519 1520 /* 1521 * AFE 0 is at offset 0x0800 1522 * AFE 1 is at offset 0x0900 1523 * AFE 2 is at offset 0x0a00 1524 * AFE 3 is at offset 0x0b00 */ 1525 struct scu_afe_transceiver { 1526 /* 0x0000 AFE_XCVR_CTRL0 */ 1527 u32 afe_xcvr_control0; 1528 /* 0x0004 AFE_XCVR_CTRL1 */ 1529 u32 afe_xcvr_control1; 1530 /* 0x0008 */ 1531 u32 reserved_0008; 1532 /* 0x000c afe_dfx_rx_control0 */ 1533 u32 afe_dfx_rx_control0; 1534 /* 0x0010 AFE_DFX_RX_CTRL1 */ 1535 u32 afe_dfx_rx_control1; 1536 /* 0x0014 */ 1537 u32 reserved_0014; 1538 /* 0x0018 AFE_DFX_RX_STS0 */ 1539 u32 afe_dfx_rx_status0; 1540 /* 0x001c AFE_DFX_RX_STS1 */ 1541 u32 afe_dfx_rx_status1; 1542 /* 0x0020 */ 1543 u32 reserved_0020; 1544 /* 0x0024 AFE_TX_CTRL */ 1545 u32 afe_tx_control; 1546 /* 0x0028 AFE_TX_AMP_CTRL0 */ 1547 u32 afe_tx_amp_control0; 1548 /* 0x002c AFE_TX_AMP_CTRL1 */ 1549 u32 afe_tx_amp_control1; 1550 /* 0x0030 AFE_TX_AMP_CTRL2 */ 1551 u32 afe_tx_amp_control2; 1552 /* 0x0034 AFE_TX_AMP_CTRL3 */ 1553 u32 afe_tx_amp_control3; 1554 /* 0x0038 afe_tx_ssc_control */ 1555 u32 afe_tx_ssc_control; 1556 /* 0x003c */ 1557 u32 reserved_003c; 1558 /* 0x0040 AFE_RX_SSC_CTRL0 */ 1559 u32 afe_rx_ssc_control0; 1560 /* 0x0044 AFE_RX_SSC_CTRL1 */ 1561 u32 afe_rx_ssc_control1; 1562 /* 0x0048 AFE_RX_SSC_CTRL2 */ 1563 u32 afe_rx_ssc_control2; 1564 /* 0x004c AFE_RX_EQ_STS0 */ 1565 u32 afe_rx_eq_status0; 1566 /* 0x0050 AFE_RX_EQ_STS1 */ 1567 u32 afe_rx_eq_status1; 1568 /* 0x0054 AFE_RX_CDR_STS */ 1569 u32 afe_rx_cdr_status; 1570 /* 0x0058 */ 1571 u32 reserved_0058; 1572 /* 0x005c AFE_CHAN_CTRL */ 1573 u32 afe_channel_control; 1574 /* 0x0060-0x006c */ 1575 u32 reserved_0060_006c[0x04]; 1576 /* 0x0070 AFE_XCVR_EC_STS0 */ 1577 u32 afe_xcvr_error_capture_status0; 1578 /* 0x0074 AFE_XCVR_EC_STS1 */ 1579 u32 afe_xcvr_error_capture_status1; 1580 /* 0x0078 AFE_XCVR_EC_STS2 */ 1581 u32 afe_xcvr_error_capture_status2; 1582 /* 0x007c afe_xcvr_ec_status3 */ 1583 u32 afe_xcvr_error_capture_status3; 1584 /* 0x0080 AFE_XCVR_EC_STS4 */ 1585 u32 afe_xcvr_error_capture_status4; 1586 /* 0x0084 AFE_XCVR_EC_STS5 */ 1587 u32 afe_xcvr_error_capture_status5; 1588 /* 0x0088-0x00fc */ 1589 u32 reserved_008c_00fc[0x1e]; 1590 }; 1591 1592 /** 1593 * struct scu_afe_registers - AFE Regsiters 1594 * 1595 * 1596 */ 1597 /* Uaoa AFE registers */ 1598 struct scu_afe_registers { 1599 /* 0Xe000 AFE_BIAS_CTRL */ 1600 u32 afe_bias_control; 1601 u32 reserved_0004; 1602 /* 0x0008 AFE_PLL_CTRL0 */ 1603 u32 afe_pll_control0; 1604 /* 0x000c AFE_PLL_CTRL1 */ 1605 u32 afe_pll_control1; 1606 /* 0x0010 AFE_PLL_CTRL2 */ 1607 u32 afe_pll_control2; 1608 /* 0x0014 AFE_CB_STS */ 1609 u32 afe_common_block_status; 1610 /* 0x0018-0x007c */ 1611 u32 reserved_18_7c[0x1a]; 1612 /* 0x0080 AFE_PMSN_MCTRL0 */ 1613 u32 afe_pmsn_master_control0; 1614 /* 0x0084 AFE_PMSN_MCTRL1 */ 1615 u32 afe_pmsn_master_control1; 1616 /* 0x0088 AFE_PMSN_MCTRL2 */ 1617 u32 afe_pmsn_master_control2; 1618 /* 0x008C-0x00fc */ 1619 u32 reserved_008c_00fc[0x1D]; 1620 /* 0x0100 AFE_DFX_MST_CTRL0 */ 1621 u32 afe_dfx_master_control0; 1622 /* 0x0104 AFE_DFX_MST_CTRL1 */ 1623 u32 afe_dfx_master_control1; 1624 /* 0x0108 AFE_DFX_DCL_CTRL */ 1625 u32 afe_dfx_dcl_control; 1626 /* 0x010c AFE_DFX_DMON_CTRL */ 1627 u32 afe_dfx_digital_monitor_control; 1628 /* 0x0110 AFE_DFX_AMONP_CTRL */ 1629 u32 afe_dfx_analog_p_monitor_control; 1630 /* 0x0114 AFE_DFX_AMONN_CTRL */ 1631 u32 afe_dfx_analog_n_monitor_control; 1632 /* 0x0118 AFE_DFX_NTL_STS */ 1633 u32 afe_dfx_ntl_status; 1634 /* 0x011c AFE_DFX_FIFO_STS0 */ 1635 u32 afe_dfx_fifo_status0; 1636 /* 0x0120 AFE_DFX_FIFO_STS1 */ 1637 u32 afe_dfx_fifo_status1; 1638 /* 0x0124 AFE_DFX_MPAT_CTRL */ 1639 u32 afe_dfx_master_pattern_control; 1640 /* 0x0128 AFE_DFX_P0_CTRL */ 1641 u32 afe_dfx_p0_control; 1642 /* 0x012c-0x01a8 AFE_DFX_P0_DRx */ 1643 u32 afe_dfx_p0_data[32]; 1644 /* 0x01ac */ 1645 u32 reserved_01ac; 1646 /* 0x01b0-0x020c AFE_DFX_P0_IRx */ 1647 u32 afe_dfx_p0_instruction[24]; 1648 /* 0x0210 */ 1649 u32 reserved_0210; 1650 /* 0x0214 AFE_DFX_P1_CTRL */ 1651 u32 afe_dfx_p1_control; 1652 /* 0x0218-0x245 AFE_DFX_P1_DRx */ 1653 u32 afe_dfx_p1_data[16]; 1654 /* 0x0258-0x029c */ 1655 u32 reserved_0258_029c[0x12]; 1656 /* 0x02a0-0x02bc AFE_DFX_P1_IRx */ 1657 u32 afe_dfx_p1_instruction[8]; 1658 /* 0x02c0-0x2fc */ 1659 u32 reserved_02c0_02fc[0x10]; 1660 /* 0x0300 AFE_DFX_TX_PMSN_CTRL */ 1661 u32 afe_dfx_tx_pmsn_control; 1662 /* 0x0304 AFE_DFX_RX_PMSN_CTRL */ 1663 u32 afe_dfx_rx_pmsn_control; 1664 u32 reserved_0308; 1665 /* 0x030c AFE_DFX_NOA_CTRL0 */ 1666 u32 afe_dfx_noa_control0; 1667 /* 0x0310 AFE_DFX_NOA_CTRL1 */ 1668 u32 afe_dfx_noa_control1; 1669 /* 0x0314 AFE_DFX_NOA_CTRL2 */ 1670 u32 afe_dfx_noa_control2; 1671 /* 0x0318 AFE_DFX_NOA_CTRL3 */ 1672 u32 afe_dfx_noa_control3; 1673 /* 0x031c AFE_DFX_NOA_CTRL4 */ 1674 u32 afe_dfx_noa_control4; 1675 /* 0x0320 AFE_DFX_NOA_CTRL5 */ 1676 u32 afe_dfx_noa_control5; 1677 /* 0x0324 AFE_DFX_NOA_CTRL6 */ 1678 u32 afe_dfx_noa_control6; 1679 /* 0x0328 AFE_DFX_NOA_CTRL7 */ 1680 u32 afe_dfx_noa_control7; 1681 /* 0x032c-0x07fc */ 1682 u32 reserved_032c_07fc[0x135]; 1683 1684 /* 0x0800-0x0bfc */ 1685 struct scu_afe_transceiver scu_afe_xcvr[4]; 1686 1687 /* 0x0c00-0x0ffc */ 1688 u32 reserved_0c00_0ffc[0x0100]; 1689 }; 1690 1691 struct scu_protocol_engine_group_registers { 1692 u32 table[0xE0]; 1693 }; 1694 1695 1696 struct scu_viit_iit { 1697 u32 table[256]; 1698 }; 1699 1700 /** 1701 * Placeholder for the ZONE Partition Table information ZONING will not be 1702 * included in the 1.1 release. 1703 * 1704 * 1705 */ 1706 struct scu_zone_partition_table { 1707 u32 table[2048]; 1708 }; 1709 1710 /** 1711 * Placeholder for the CRAM register since I am not sure if we need to 1712 * read/write to these registers as yet. 1713 * 1714 * 1715 */ 1716 struct scu_completion_ram { 1717 u32 ram[128]; 1718 }; 1719 1720 /** 1721 * Placeholder for the FBRAM registers since I am not sure if we need to 1722 * read/write to these registers as yet. 1723 * 1724 * 1725 */ 1726 struct scu_frame_buffer_ram { 1727 u32 ram[128]; 1728 }; 1729 1730 #define scu_scratch_ram_SIZE_IN_DWORDS 256 1731 1732 /** 1733 * Placeholder for the scratch RAM registers. 1734 * 1735 * 1736 */ 1737 struct scu_scratch_ram { 1738 u32 ram[scu_scratch_ram_SIZE_IN_DWORDS]; 1739 }; 1740 1741 /** 1742 * Placeholder since I am not yet sure what these registers are here for. 1743 * 1744 * 1745 */ 1746 struct noa_protocol_engine_partition { 1747 u32 reserved[64]; 1748 }; 1749 1750 /** 1751 * Placeholder since I am not yet sure what these registers are here for. 1752 * 1753 * 1754 */ 1755 struct noa_hub_partition { 1756 u32 reserved[64]; 1757 }; 1758 1759 /** 1760 * Placeholder since I am not yet sure what these registers are here for. 1761 * 1762 * 1763 */ 1764 struct noa_host_interface_partition { 1765 u32 reserved[64]; 1766 }; 1767 1768 /** 1769 * struct transport_link_layer_pair - The SCU Hardware pairs up the TL 1770 * registers with the LL registers so we must place them adjcent to make the 1771 * array of registers in the PEG. 1772 * 1773 * 1774 */ 1775 struct transport_link_layer_pair { 1776 struct scu_transport_layer_registers tl; 1777 struct scu_link_layer_registers ll; 1778 }; 1779 1780 /** 1781 * struct scu_peg_registers - SCU Protocol Engine Memory mapped register space. 1782 * These registers are unique to each protocol engine group. There can be 1783 * at most two PEG for a single SCU part. 1784 * 1785 * 1786 */ 1787 struct scu_peg_registers { 1788 struct transport_link_layer_pair pe[4]; 1789 struct scu_port_task_scheduler_group_registers ptsg; 1790 struct scu_protocol_engine_group_registers peg; 1791 struct scu_sgpio_registers sgpio; 1792 u32 reserved_01500_1BFF[0x1C0]; 1793 struct scu_viit_entry viit[64]; 1794 struct scu_zone_partition_table zpt0; 1795 struct scu_zone_partition_table zpt1; 1796 }; 1797 1798 /** 1799 * struct scu_registers - SCU regsiters including both PEG registers if we turn 1800 * on that compile option. All of these registers are in the memory mapped 1801 * space returned from BAR1. 1802 * 1803 * 1804 */ 1805 struct scu_registers { 1806 /* 0x0000 - PEG 0 */ 1807 struct scu_peg_registers peg0; 1808 1809 /* 0x6000 - SDMA and Miscellaneous */ 1810 struct scu_sdma_registers sdma; 1811 struct scu_completion_ram cram; 1812 struct scu_frame_buffer_ram fbram; 1813 u32 reserved_6800_69FF[0x80]; 1814 struct noa_protocol_engine_partition noa_pe; 1815 struct noa_hub_partition noa_hub; 1816 struct noa_host_interface_partition noa_if; 1817 u32 reserved_6d00_7fff[0x4c0]; 1818 1819 /* 0x8000 - PEG 1 */ 1820 struct scu_peg_registers peg1; 1821 1822 /* 0xE000 - AFE Registers */ 1823 struct scu_afe_registers afe; 1824 1825 /* 0xF000 - reserved */ 1826 u32 reserved_f000_211fff[0x80c00]; 1827 1828 /* 0x212000 - scratch RAM */ 1829 struct scu_scratch_ram scratch_ram; 1830 }; 1831 1832 #endif /* _SCU_REGISTERS_HEADER_ */ 1833