1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "cpu.h"
32 #include "system/system.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
35 #include "hw/qdev-properties.h"
36 #include "elf.h"
37 #include "system/memory.h"
38 #include "exec/tswap.h"
39 #include "hw/char/serial-mm.h"
40 #include "net/net.h"
41 #include "hw/sysbus.h"
42 #include "hw/block/flash.h"
43 #include "chardev/char.h"
44 #include "system/device_tree.h"
45 #include "system/reset.h"
46 #include "system/runstate.h"
47 #include "qemu/error-report.h"
48 #include "qemu/option.h"
49 #include "bootparam.h"
50 #include "xtensa_memory.h"
51 #include "hw/xtensa/mx_pic.h"
52 #include "migration/vmstate.h"
53
54 typedef struct XtfpgaFlashDesc {
55 hwaddr base;
56 size_t size;
57 size_t boot_base;
58 size_t sector_size;
59 } XtfpgaFlashDesc;
60
61 typedef struct XtfpgaBoardDesc {
62 const XtfpgaFlashDesc *flash;
63 size_t sram_size;
64 const hwaddr *io;
65 } XtfpgaBoardDesc;
66
67 typedef struct XtfpgaFpgaState {
68 MemoryRegion iomem;
69 uint32_t freq;
70 uint32_t leds;
71 uint32_t switches;
72 } XtfpgaFpgaState;
73
xtfpga_fpga_reset(void * opaque)74 static void xtfpga_fpga_reset(void *opaque)
75 {
76 XtfpgaFpgaState *s = opaque;
77
78 s->leds = 0;
79 s->switches = 0;
80 }
81
xtfpga_fpga_read(void * opaque,hwaddr addr,unsigned size)82 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
83 unsigned size)
84 {
85 XtfpgaFpgaState *s = opaque;
86
87 switch (addr) {
88 case 0x0: /*build date code*/
89 return 0x09272011;
90
91 case 0x4: /*processor clock frequency, Hz*/
92 return s->freq;
93
94 case 0x8: /*LEDs (off = 0, on = 1)*/
95 return s->leds;
96
97 case 0xc: /*DIP switches (off = 0, on = 1)*/
98 return s->switches;
99 }
100 return 0;
101 }
102
xtfpga_fpga_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)103 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
104 uint64_t val, unsigned size)
105 {
106 XtfpgaFpgaState *s = opaque;
107
108 switch (addr) {
109 case 0x8: /*LEDs (off = 0, on = 1)*/
110 s->leds = val;
111 break;
112
113 case 0x10: /*board reset*/
114 if (val == 0xdead) {
115 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
116 }
117 break;
118 }
119 }
120
121 static const MemoryRegionOps xtfpga_fpga_ops = {
122 .read = xtfpga_fpga_read,
123 .write = xtfpga_fpga_write,
124 .endianness = DEVICE_NATIVE_ENDIAN,
125 };
126
xtfpga_fpga_init(MemoryRegion * address_space,hwaddr base,uint32_t freq)127 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
128 hwaddr base, uint32_t freq)
129 {
130 XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1);
131
132 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
133 "xtfpga.fpga", 0x10000);
134 memory_region_add_subregion(address_space, base, &s->iomem);
135 s->freq = freq;
136 xtfpga_fpga_reset(s);
137 qemu_register_reset(xtfpga_fpga_reset, s);
138 return s;
139 }
140
xtfpga_net_init(MemoryRegion * address_space,hwaddr base,hwaddr descriptors,hwaddr buffers,qemu_irq irq)141 static void xtfpga_net_init(MemoryRegion *address_space,
142 hwaddr base,
143 hwaddr descriptors,
144 hwaddr buffers,
145 qemu_irq irq)
146 {
147 DeviceState *dev;
148 SysBusDevice *s;
149 MemoryRegion *ram;
150
151 dev = qemu_create_nic_device("open_eth", true, NULL);
152 if (!dev) {
153 return;
154 }
155
156 s = SYS_BUS_DEVICE(dev);
157 sysbus_realize_and_unref(s, &error_fatal);
158 sysbus_connect_irq(s, 0, irq);
159 memory_region_add_subregion(address_space, base,
160 sysbus_mmio_get_region(s, 0));
161 memory_region_add_subregion(address_space, descriptors,
162 sysbus_mmio_get_region(s, 1));
163
164 ram = g_malloc(sizeof(*ram));
165 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
166 &error_fatal);
167 vmstate_register_ram_global(ram);
168 memory_region_add_subregion(address_space, buffers, ram);
169 }
170
xtfpga_flash_init(MemoryRegion * address_space,const XtfpgaBoardDesc * board,DriveInfo * dinfo,int be)171 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space,
172 const XtfpgaBoardDesc *board,
173 DriveInfo *dinfo, int be)
174 {
175 SysBusDevice *s;
176 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
177
178 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
179 qdev_prop_set_uint32(dev, "num-blocks",
180 board->flash->size / board->flash->sector_size);
181 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
182 qdev_prop_set_uint8(dev, "width", 2);
183 qdev_prop_set_bit(dev, "big-endian", be);
184 qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
185 s = SYS_BUS_DEVICE(dev);
186 sysbus_realize_and_unref(s, &error_fatal);
187 memory_region_add_subregion(address_space, board->flash->base,
188 sysbus_mmio_get_region(s, 0));
189 return PFLASH_CFI01(dev);
190 }
191
translate_phys_addr(void * opaque,uint64_t addr)192 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
193 {
194 XtensaCPU *cpu = opaque;
195
196 return cpu_get_phys_page_debug(CPU(cpu), addr);
197 }
198
xtfpga_reset(void * opaque)199 static void xtfpga_reset(void *opaque)
200 {
201 XtensaCPU *cpu = opaque;
202
203 cpu_reset(CPU(cpu));
204 }
205
xtfpga_io_read(void * opaque,hwaddr addr,unsigned size)206 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
207 unsigned size)
208 {
209 return 0;
210 }
211
xtfpga_io_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)212 static void xtfpga_io_write(void *opaque, hwaddr addr,
213 uint64_t val, unsigned size)
214 {
215 }
216
217 static const MemoryRegionOps xtfpga_io_ops = {
218 .read = xtfpga_io_read,
219 .write = xtfpga_io_write,
220 .endianness = DEVICE_NATIVE_ENDIAN,
221 };
222
xtfpga_init(const XtfpgaBoardDesc * board,MachineState * machine)223 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
224 {
225 MemoryRegion *system_memory = get_system_memory();
226 XtensaCPU *cpu = NULL;
227 CPUXtensaState *env = NULL;
228 MemoryRegion *system_io;
229 XtensaMxPic *mx_pic = NULL;
230 qemu_irq *extints;
231 DriveInfo *dinfo;
232 PFlashCFI01 *flash = NULL;
233 const char *kernel_filename = machine->kernel_filename;
234 const char *kernel_cmdline = machine->kernel_cmdline;
235 const char *dtb_filename = machine->dtb;
236 const char *initrd_filename = machine->initrd_filename;
237 const unsigned system_io_size = 224 * MiB;
238 uint32_t freq = 10000000;
239 int n;
240 unsigned int smp_cpus = machine->smp.cpus;
241
242 if (smp_cpus > 1) {
243 mx_pic = xtensa_mx_pic_init(31);
244 qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
245 }
246 for (n = 0; n < smp_cpus; n++) {
247 CPUXtensaState *cenv = NULL;
248
249 cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
250 cenv = &cpu->env;
251 if (!env) {
252 env = cenv;
253 freq = env->config->clock_freq_khz * 1000;
254 }
255
256 if (mx_pic) {
257 MemoryRegion *mx_eri;
258
259 mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
260 xtensa_get_extints(cenv),
261 xtensa_get_runstall(cenv));
262 memory_region_add_subregion(xtensa_get_er_region(cenv),
263 0, mx_eri);
264 }
265 cenv->sregs[PRID] = n;
266 xtensa_select_static_vectors(cenv, n != 0);
267 qemu_register_reset(xtfpga_reset, cpu);
268 /* Need MMU initialized prior to ELF loading,
269 * so that ELF gets loaded into virtual addresses
270 */
271 cpu_reset(CPU(cpu));
272 }
273 if (smp_cpus > 1) {
274 extints = xtensa_mx_pic_get_extints(mx_pic);
275 } else {
276 extints = xtensa_get_extints(env);
277 }
278
279 if (env) {
280 XtensaMemory sysram = env->config->sysram;
281
282 sysram.location[0].size = machine->ram_size;
283 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
284 system_memory);
285 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
286 system_memory);
287 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
288 system_memory);
289 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
290 system_memory);
291 xtensa_create_memory_regions(&sysram, "xtensa.sysram",
292 system_memory);
293 }
294
295 system_io = g_malloc(sizeof(*system_io));
296 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
297 system_io_size);
298 memory_region_add_subregion(system_memory, board->io[0], system_io);
299 if (board->io[1]) {
300 MemoryRegion *io = g_malloc(sizeof(*io));
301
302 memory_region_init_alias(io, NULL, "xtfpga.io.cached",
303 system_io, 0, system_io_size);
304 memory_region_add_subregion(system_memory, board->io[1], io);
305 }
306 xtfpga_fpga_init(system_io, 0x0d020000, freq);
307 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, extints[1]);
308
309 serial_mm_init(system_io, 0x0d050020, 2, extints[0],
310 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
311
312 dinfo = drive_get(IF_PFLASH, 0, 0);
313 if (dinfo) {
314 flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN);
315 }
316
317 /* Use presence of kernel file name as 'boot from SRAM' switch. */
318 if (kernel_filename) {
319 uint32_t entry_point = env->pc;
320 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
321 uint32_t tagptr = env->config->sysrom.location[0].addr +
322 board->sram_size;
323 uint32_t cur_tagptr;
324 BpMemInfo memory_location = {
325 .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
326 .start = tswap32(env->config->sysram.location[0].addr),
327 .end = tswap32(env->config->sysram.location[0].addr +
328 machine->ram_size),
329 };
330 uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
331 machine->ram_size : 0x08000000;
332 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
333
334 lowmem_end += env->config->sysram.location[0].addr;
335 cur_lowmem += env->config->sysram.location[0].addr;
336
337 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
338 system_memory);
339
340 if (kernel_cmdline) {
341 bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
342 }
343 if (dtb_filename) {
344 bp_size += get_tag_size(sizeof(uint32_t));
345 }
346 if (initrd_filename) {
347 bp_size += get_tag_size(sizeof(BpMemInfo));
348 }
349
350 /* Put kernel bootparameters to the end of that SRAM */
351 tagptr = (tagptr - bp_size) & ~0xff;
352 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
353 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
354 sizeof(memory_location), &memory_location);
355
356 if (kernel_cmdline) {
357 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
358 strlen(kernel_cmdline) + 1, kernel_cmdline);
359 }
360 if (dtb_filename) {
361 int fdt_size;
362 void *fdt = load_device_tree(dtb_filename, &fdt_size);
363 uint32_t dtb_addr = tswap32(cur_lowmem);
364
365 if (!fdt) {
366 error_report("could not load DTB '%s'", dtb_filename);
367 exit(EXIT_FAILURE);
368 }
369
370 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
371 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
372 sizeof(dtb_addr), &dtb_addr);
373 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
374 g_free(fdt);
375 }
376 if (initrd_filename) {
377 BpMemInfo initrd_location = { 0 };
378 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
379 lowmem_end - cur_lowmem);
380
381 if (initrd_size < 0) {
382 initrd_size = load_image_targphys(initrd_filename,
383 cur_lowmem,
384 lowmem_end - cur_lowmem);
385 }
386 if (initrd_size < 0) {
387 error_report("could not load initrd '%s'", initrd_filename);
388 exit(EXIT_FAILURE);
389 }
390 initrd_location.start = tswap32(cur_lowmem);
391 initrd_location.end = tswap32(cur_lowmem + initrd_size);
392 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
393 sizeof(initrd_location), &initrd_location);
394 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
395 }
396 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
397 env->regs[2] = tagptr;
398
399 uint64_t elf_entry;
400 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
401 &elf_entry, NULL, NULL, NULL,
402 TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB,
403 EM_XTENSA, 0, 0);
404 if (success > 0) {
405 entry_point = elf_entry;
406 } else {
407 hwaddr ep;
408 int is_linux;
409 success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
410 translate_phys_addr, cpu);
411 if (success > 0 && is_linux) {
412 entry_point = ep;
413 } else {
414 error_report("could not load kernel '%s'",
415 kernel_filename);
416 exit(EXIT_FAILURE);
417 }
418 }
419 if (entry_point != env->pc) {
420 uint8_t boot_be[] = {
421 0x60, 0x00, 0x08, /* j 1f */
422 0x00, /* .literal_position */
423 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
424 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
425 /* 1: */
426 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
427 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
428 0x0a, 0x00, 0x00, /* jx a0 */
429 };
430 uint8_t boot_le[] = {
431 0x06, 0x02, 0x00, /* j 1f */
432 0x00, /* .literal_position */
433 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
434 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
435 /* 1: */
436 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
437 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
438 0xa0, 0x00, 0x00, /* jx a0 */
439 };
440 const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be)
441 : sizeof(boot_le);
442 uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le;
443 uint32_t entry_pc = tswap32(entry_point);
444 uint32_t entry_a2 = tswap32(tagptr);
445
446 memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
447 memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
448 cpu_physical_memory_write(env->pc, boot, boot_sz);
449 }
450 } else {
451 if (flash) {
452 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
453 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
454 uint32_t size = env->config->sysrom.location[0].size;
455
456 if (board->flash->size - board->flash->boot_base < size) {
457 size = board->flash->size - board->flash->boot_base;
458 }
459
460 memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
461 flash_mr, board->flash->boot_base, size);
462 memory_region_add_subregion(system_memory,
463 env->config->sysrom.location[0].addr,
464 flash_io);
465 } else {
466 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
467 system_memory);
468 }
469 }
470 }
471
472 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
473
474 static const hwaddr xtfpga_mmu_io[2] = {
475 0xf0000000,
476 };
477
478 static const hwaddr xtfpga_nommu_io[2] = {
479 0x90000000,
480 0x70000000,
481 };
482
483 static const XtfpgaFlashDesc lx60_flash = {
484 .base = 0x08000000,
485 .size = 0x00400000,
486 .sector_size = 0x10000,
487 };
488
xtfpga_lx60_init(MachineState * machine)489 static void xtfpga_lx60_init(MachineState *machine)
490 {
491 static const XtfpgaBoardDesc lx60_board = {
492 .flash = &lx60_flash,
493 .sram_size = 0x20000,
494 .io = xtfpga_mmu_io,
495 };
496 xtfpga_init(&lx60_board, machine);
497 }
498
xtfpga_lx60_nommu_init(MachineState * machine)499 static void xtfpga_lx60_nommu_init(MachineState *machine)
500 {
501 static const XtfpgaBoardDesc lx60_board = {
502 .flash = &lx60_flash,
503 .sram_size = 0x20000,
504 .io = xtfpga_nommu_io,
505 };
506 xtfpga_init(&lx60_board, machine);
507 }
508
509 static const XtfpgaFlashDesc lx200_flash = {
510 .base = 0x08000000,
511 .size = 0x01000000,
512 .sector_size = 0x20000,
513 };
514
xtfpga_lx200_init(MachineState * machine)515 static void xtfpga_lx200_init(MachineState *machine)
516 {
517 static const XtfpgaBoardDesc lx200_board = {
518 .flash = &lx200_flash,
519 .sram_size = 0x2000000,
520 .io = xtfpga_mmu_io,
521 };
522 xtfpga_init(&lx200_board, machine);
523 }
524
xtfpga_lx200_nommu_init(MachineState * machine)525 static void xtfpga_lx200_nommu_init(MachineState *machine)
526 {
527 static const XtfpgaBoardDesc lx200_board = {
528 .flash = &lx200_flash,
529 .sram_size = 0x2000000,
530 .io = xtfpga_nommu_io,
531 };
532 xtfpga_init(&lx200_board, machine);
533 }
534
535 static const XtfpgaFlashDesc ml605_flash = {
536 .base = 0x08000000,
537 .size = 0x01000000,
538 .sector_size = 0x20000,
539 };
540
xtfpga_ml605_init(MachineState * machine)541 static void xtfpga_ml605_init(MachineState *machine)
542 {
543 static const XtfpgaBoardDesc ml605_board = {
544 .flash = &ml605_flash,
545 .sram_size = 0x2000000,
546 .io = xtfpga_mmu_io,
547 };
548 xtfpga_init(&ml605_board, machine);
549 }
550
xtfpga_ml605_nommu_init(MachineState * machine)551 static void xtfpga_ml605_nommu_init(MachineState *machine)
552 {
553 static const XtfpgaBoardDesc ml605_board = {
554 .flash = &ml605_flash,
555 .sram_size = 0x2000000,
556 .io = xtfpga_nommu_io,
557 };
558 xtfpga_init(&ml605_board, machine);
559 }
560
561 static const XtfpgaFlashDesc kc705_flash = {
562 .base = 0x00000000,
563 .size = 0x08000000,
564 .boot_base = 0x06000000,
565 .sector_size = 0x20000,
566 };
567
xtfpga_kc705_init(MachineState * machine)568 static void xtfpga_kc705_init(MachineState *machine)
569 {
570 static const XtfpgaBoardDesc kc705_board = {
571 .flash = &kc705_flash,
572 .sram_size = 0x2000000,
573 .io = xtfpga_mmu_io,
574 };
575 xtfpga_init(&kc705_board, machine);
576 }
577
xtfpga_kc705_nommu_init(MachineState * machine)578 static void xtfpga_kc705_nommu_init(MachineState *machine)
579 {
580 static const XtfpgaBoardDesc kc705_board = {
581 .flash = &kc705_flash,
582 .sram_size = 0x2000000,
583 .io = xtfpga_nommu_io,
584 };
585 xtfpga_init(&kc705_board, machine);
586 }
587
xtfpga_lx60_class_init(ObjectClass * oc,const void * data)588 static void xtfpga_lx60_class_init(ObjectClass *oc, const void *data)
589 {
590 MachineClass *mc = MACHINE_CLASS(oc);
591
592 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
593 mc->init = xtfpga_lx60_init;
594 mc->max_cpus = 32;
595 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
596 mc->default_ram_size = 64 * MiB;
597 }
598
599 static const TypeInfo xtfpga_lx60_type = {
600 .name = MACHINE_TYPE_NAME("lx60"),
601 .parent = TYPE_MACHINE,
602 .class_init = xtfpga_lx60_class_init,
603 };
604
xtfpga_lx60_nommu_class_init(ObjectClass * oc,const void * data)605 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, const void *data)
606 {
607 MachineClass *mc = MACHINE_CLASS(oc);
608
609 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
610 mc->init = xtfpga_lx60_nommu_init;
611 mc->max_cpus = 32;
612 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
613 mc->default_ram_size = 64 * MiB;
614 }
615
616 static const TypeInfo xtfpga_lx60_nommu_type = {
617 .name = MACHINE_TYPE_NAME("lx60-nommu"),
618 .parent = TYPE_MACHINE,
619 .class_init = xtfpga_lx60_nommu_class_init,
620 };
621
xtfpga_lx200_class_init(ObjectClass * oc,const void * data)622 static void xtfpga_lx200_class_init(ObjectClass *oc, const void *data)
623 {
624 MachineClass *mc = MACHINE_CLASS(oc);
625
626 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
627 mc->init = xtfpga_lx200_init;
628 mc->max_cpus = 32;
629 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
630 mc->default_ram_size = 96 * MiB;
631 }
632
633 static const TypeInfo xtfpga_lx200_type = {
634 .name = MACHINE_TYPE_NAME("lx200"),
635 .parent = TYPE_MACHINE,
636 .class_init = xtfpga_lx200_class_init,
637 };
638
xtfpga_lx200_nommu_class_init(ObjectClass * oc,const void * data)639 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, const void *data)
640 {
641 MachineClass *mc = MACHINE_CLASS(oc);
642
643 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
644 mc->init = xtfpga_lx200_nommu_init;
645 mc->max_cpus = 32;
646 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
647 mc->default_ram_size = 96 * MiB;
648 }
649
650 static const TypeInfo xtfpga_lx200_nommu_type = {
651 .name = MACHINE_TYPE_NAME("lx200-nommu"),
652 .parent = TYPE_MACHINE,
653 .class_init = xtfpga_lx200_nommu_class_init,
654 };
655
xtfpga_ml605_class_init(ObjectClass * oc,const void * data)656 static void xtfpga_ml605_class_init(ObjectClass *oc, const void *data)
657 {
658 MachineClass *mc = MACHINE_CLASS(oc);
659
660 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
661 mc->init = xtfpga_ml605_init;
662 mc->max_cpus = 32;
663 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
664 mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
665 }
666
667 static const TypeInfo xtfpga_ml605_type = {
668 .name = MACHINE_TYPE_NAME("ml605"),
669 .parent = TYPE_MACHINE,
670 .class_init = xtfpga_ml605_class_init,
671 };
672
xtfpga_ml605_nommu_class_init(ObjectClass * oc,const void * data)673 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, const void *data)
674 {
675 MachineClass *mc = MACHINE_CLASS(oc);
676
677 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
678 mc->init = xtfpga_ml605_nommu_init;
679 mc->max_cpus = 32;
680 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
681 mc->default_ram_size = 256 * MiB;
682 }
683
684 static const TypeInfo xtfpga_ml605_nommu_type = {
685 .name = MACHINE_TYPE_NAME("ml605-nommu"),
686 .parent = TYPE_MACHINE,
687 .class_init = xtfpga_ml605_nommu_class_init,
688 };
689
xtfpga_kc705_class_init(ObjectClass * oc,const void * data)690 static void xtfpga_kc705_class_init(ObjectClass *oc, const void *data)
691 {
692 MachineClass *mc = MACHINE_CLASS(oc);
693
694 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
695 mc->init = xtfpga_kc705_init;
696 mc->max_cpus = 32;
697 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
698 mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
699 }
700
701 static const TypeInfo xtfpga_kc705_type = {
702 .name = MACHINE_TYPE_NAME("kc705"),
703 .parent = TYPE_MACHINE,
704 .class_init = xtfpga_kc705_class_init,
705 };
706
xtfpga_kc705_nommu_class_init(ObjectClass * oc,const void * data)707 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, const void *data)
708 {
709 MachineClass *mc = MACHINE_CLASS(oc);
710
711 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
712 mc->init = xtfpga_kc705_nommu_init;
713 mc->max_cpus = 32;
714 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
715 mc->default_ram_size = 256 * MiB;
716 }
717
718 static const TypeInfo xtfpga_kc705_nommu_type = {
719 .name = MACHINE_TYPE_NAME("kc705-nommu"),
720 .parent = TYPE_MACHINE,
721 .class_init = xtfpga_kc705_nommu_class_init,
722 };
723
xtfpga_machines_init(void)724 static void xtfpga_machines_init(void)
725 {
726 type_register_static(&xtfpga_lx60_type);
727 type_register_static(&xtfpga_lx200_type);
728 type_register_static(&xtfpga_ml605_type);
729 type_register_static(&xtfpga_kc705_type);
730 type_register_static(&xtfpga_lx60_nommu_type);
731 type_register_static(&xtfpga_lx200_nommu_type);
732 type_register_static(&xtfpga_ml605_nommu_type);
733 type_register_static(&xtfpga_kc705_nommu_type);
734 }
735
736 type_init(xtfpga_machines_init)
737