1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Marvell NFC driver 4 * 5 * Copyright (C) 2014-2015, Marvell International Ltd. 6 */ 7 8 #ifndef _NFCMRVL_H_ 9 #define _NFCMRVL_H_ 10 11 #include "fw_dnld.h" 12 13 struct gpio_desc; 14 15 /* Define private flags: */ 16 #define NFCMRVL_NCI_RUNNING 1 17 #define NFCMRVL_PHY_ERROR 2 18 19 #define NFCMRVL_EXT_COEX_ID 0xE0 20 #define NFCMRVL_NOT_ALLOWED_ID 0xE1 21 #define NFCMRVL_ACTIVE_ID 0xE2 22 #define NFCMRVL_EXT_COEX_ENABLE 1 23 #define NFCMRVL_GPIO_PIN_NFC_NOT_ALLOWED 0xA 24 #define NFCMRVL_GPIO_PIN_NFC_ACTIVE 0xB 25 #define NFCMRVL_NCI_MAX_EVENT_SIZE 260 26 27 /* 28 * NCI FW Parameters 29 */ 30 31 #define NFCMRVL_PB_BAIL_OUT 0x11 32 #define NFCMRVL_PROP_REF_CLOCK 0xF0 33 #define NFCMRVL_PROP_SET_HI_CONFIG 0xF1 34 35 /* 36 * HCI defines 37 */ 38 39 #define NFCMRVL_HCI_EVENT_HEADER_SIZE 0x04 40 #define NFCMRVL_HCI_EVENT_CODE 0x04 41 #define NFCMRVL_HCI_NFC_EVENT_CODE 0xFF 42 #define NFCMRVL_HCI_COMMAND_CODE 0x01 43 #define NFCMRVL_HCI_OGF 0x81 44 #define NFCMRVL_HCI_OCF 0xFE 45 46 enum nfcmrvl_phy { 47 NFCMRVL_PHY_USB = 0, 48 NFCMRVL_PHY_UART = 1, 49 NFCMRVL_PHY_I2C = 2, 50 NFCMRVL_PHY_SPI = 3, 51 }; 52 53 struct nfcmrvl_platform_data { 54 /* 55 * Generic 56 */ 57 58 /* GPIO that is wired to RESET_N signal */ 59 struct gpio_desc *reset_gpio; 60 /* Tell if transport is muxed in HCI one */ 61 bool hci_muxed; 62 63 /* 64 * UART specific 65 */ 66 67 /* Tell if UART needs flow control at init */ 68 bool flow_control; 69 /* Tell if firmware supports break control for power management */ 70 bool break_control; 71 72 73 /* 74 * I2C specific 75 */ 76 77 unsigned int irq; 78 unsigned int irq_polarity; 79 }; 80 81 struct nfcmrvl_private { 82 83 unsigned long flags; 84 85 /* Platform configuration */ 86 struct nfcmrvl_platform_data config; 87 88 /* Parent dev */ 89 struct nci_dev *ndev; 90 91 /* FW download context */ 92 struct nfcmrvl_fw_dnld fw_dnld; 93 94 /* FW download support */ 95 bool support_fw_dnld; 96 97 /* 98 * PHY related information 99 */ 100 101 /* PHY driver context */ 102 void *drv_data; 103 /* PHY device */ 104 struct device *dev; 105 /* PHY type */ 106 enum nfcmrvl_phy phy; 107 /* Low level driver ops */ 108 const struct nfcmrvl_if_ops *if_ops; 109 }; 110 111 struct nfcmrvl_if_ops { 112 int (*nci_open) (struct nfcmrvl_private *priv); 113 int (*nci_close) (struct nfcmrvl_private *priv); 114 int (*nci_send) (struct nfcmrvl_private *priv, struct sk_buff *skb); 115 void (*nci_update_config)(struct nfcmrvl_private *priv, 116 const void *param); 117 }; 118 119 void nfcmrvl_nci_unregister_dev(struct nfcmrvl_private *priv); 120 int nfcmrvl_nci_recv_frame(struct nfcmrvl_private *priv, struct sk_buff *skb); 121 struct nfcmrvl_private *nfcmrvl_nci_register_dev(enum nfcmrvl_phy phy, 122 void *drv_data, 123 const struct nfcmrvl_if_ops *ops, 124 struct device *dev, 125 const struct nfcmrvl_platform_data *pdata); 126 127 128 void nfcmrvl_chip_reset(struct nfcmrvl_private *priv); 129 void nfcmrvl_chip_halt(struct nfcmrvl_private *priv); 130 131 int nfcmrvl_parse_dt(struct device_node *node, 132 struct nfcmrvl_platform_data *pdata); 133 134 #endif 135